opcodes/ChangeLog

   1 2019-10-29  Nick Clifton  <nickc@redhat.com>
   2
   3         * tic30-dis.c (print_branch): Correct size of operand array.
   4
   5 2019-10-29  Nick Clifton  <nickc@redhat.com>
   6
   7         * d30v-dis.c (print_insn): Check that operand index is valid
   8         before attempting to access the operands array.
   9
  10 2019-10-29  Nick Clifton  <nickc@redhat.com>
  11
  12         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
  13         locating the bit to be tested.
  14
  15 2019-10-29  Nick Clifton  <nickc@redhat.com>
  16
  17         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
  18         values.
  19         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
  20         (print_insn_s12z):  Check for illegal size values.
  21
  22 2019-10-28  Nick Clifton  <nickc@redhat.com>
  23
  24         * csky-dis.c (csky_chars_to_number): Check for a negative
  25         count. Use an unsigned integer to construct the return value.
  26
  27 2019-10-28  Nick Clifton  <nickc@redhat.com>
  28
  29         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
  30         operand buffer.  Set value to 15 not 13.
  31         (get_register_operand): Use OPERAND_BUFFER_LEN.
  32         (get_indirect_operand): Likewise.
  33         (print_two_operand): Likewise.
  34         (print_three_operand): Likewise.
  35         (print_oar_insn): Likewise.
  36
  37 2019-10-28  Nick Clifton  <nickc@redhat.com>
  38
  39         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  40         (bit_extract_simple): Likewise.
  41         (bit_copy): Likewise.
  42         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  43         index_offset array are not accessed.
  44
  45 2019-10-28  Nick Clifton  <nickc@redhat.com>
  46
  47         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  48         operand.
  49
  50 2019-10-25  Nick Clifton  <nickc@redhat.com>
  51
  52         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  53         access to opcodes.op array element.
  54
  55 2019-10-23  Nick Clifton  <nickc@redhat.com>
  56
  57         * rx-dis.c (get_register_name): Fix spelling typo in error
  58         message.
  59         (get_condition_name, get_flag_name, get_double_register_name)
  60         (get_double_register_high_name, get_double_register_low_name)
  61         (get_double_control_register_name, get_double_condition_name)
  62         (get_opsize_name, get_size_name): Likewise.
  63
  64 2019-10-22  Nick Clifton  <nickc@redhat.com>
  65
  66         * rx-dis.c (get_size_name): New function.  Provides safe
  67         access to name array.
  68         (get_opsize_name): Likewise.
  69         (print_insn_rx): Use the accessor functions.
  70
  71 2019-10-16  Nick Clifton  <nickc@redhat.com>
  72
  73         * rx-dis.c (get_register_name): New function.  Provides safe
  74         access to name array.
  75         (get_condition_name, get_flag_name, get_double_register_name)
  76         (get_double_register_high_name, get_double_register_low_name)
  77         (get_double_control_register_name, get_double_condition_name):
  78         Likewise.
  79         (print_insn_rx): Use the accessor functions.
  80
  81 2019-10-09  Nick Clifton  <nickc@redhat.com>
  82
  83         PR 25041
  84         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  85         instructions.
  86
  87 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  88
  89         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  90         (cmpsd): Likewise. Move EsSeg to other operand.
  91         * opcodes/i386-tbl.h: Re-generate.
  92
  93 2019-09-23  Alan Modra  <amodra@gmail.com>
  94
  95         * m68k-dis.c: Include cpu-m68k.h
  96
  97 2019-09-23  Alan Modra  <amodra@gmail.com>
  98
  99         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 100         "elf/mips.h" earlier.
 101
 102 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 103
 104         PR gas/25012
 105         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 106         with SReg operand.
 107         * i386-tbl.h: Re-generate.
 108
 109 2019-09-18  Alan Modra  <amodra@gmail.com>
 110
 111         * arc-ext.c: Update throughout for bfd section macro changes.
 112
 113 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 114
 115         * Makefile.in: Re-generate.
 116         * configure: Re-generate.
 117
 118 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 119
 120         * riscv-opc.c (riscv_opcodes): Change subset field
 121         to insn_class field for all instructions.
 122         (riscv_insn_types): Likewise.
 123
 124 2019-09-16  Phil Blundell  <pb@pbcl.net>
 125
 126         * configure: Regenerated.
 127
 128 2019-09-10  Miod Vallat  <miod@online.fr>
 129
 130         PR 24982
 131         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 132
 133 2019-09-09  Phil Blundell  <pb@pbcl.net>
 134
 135         binutils 2.33 branch created.
 136
 137 2019-09-03  Nick Clifton  <nickc@redhat.com>
 138
 139         PR 24961
 140         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 141         greater than zero before indexing via (bufcnt -1).
 142
 143 2019-09-03  Nick Clifton  <nickc@redhat.com>
 144
 145         PR 24958
 146         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 147         (MAX_SPEC_REG_NAME_LEN): Define.
 148         (struct mmix_dis_info): Use defined constants for array lengths.
 149         (get_reg_name): New function.
 150         (get_sprec_reg_name): New function.
 151         (print_insn_mmix): Use new functions.
 152
 153 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 154
 155         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 156         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 157         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 158
 159 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 160
 161         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 162         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 163         (aarch64_sys_reg_supported_p): Update checks for the above.
 164
 165 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 166
 167         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 168         cases MVE_SQRSHRL and MVE_UQRSHLL.
 169         (print_insn_mve): Add case for specifier 'k' to check
 170         specific bit of the instruction.
 171
 172 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 173
 174         PR 24854
 175         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 176         encountering an unknown machine type.
 177         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 178         cases return -1 rather than calling abort.
 179
 180 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 183         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 184         IgnoreSize.
 185         * i386-tbl.h: Re-generate.
 186
 187 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 188
 189         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 190         instructions.
 191
 192 2019-07-30  Mel Chen <mel.chen@sifive.com>
 193
 194         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 195         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 196
 197         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 198         fscsr.
 199
 200 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 201
 202         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 203         and MPY class instructions.
 204         (parse_option): Add nps400 option.
 205         (print_arc_disassembler_options): Add nps400 info.
 206
 207 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 208
 209         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 210         (bspop): Likewise.
 211         (modapp): Likewise.
 212         * arc-opc.c (RAD_CHK): Add.
 213         * arc-tbl.h: Regenerate.
 214
 215 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 216
 217         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 218         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 219
 220 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 221
 222         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 223         instructions as UNPREDICTABLE.
 224
 225 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 226
 227         * bpf-desc.c: Regenerated.
 228
 229 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-gen.c (static_assert): Define.
 232         (main): Use it.
 233         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 234         (Opcode_Modifier_Num): ... this.
 235         (Mem): Delete.
 236
 237 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-gen.c (operand_types): Move RegMem ...
 240         (opcode_modifiers): ... here.
 241         * i386-opc.h (RegMem): Move to opcode modifer enum.
 242         (union i386_operand_type): Move regmem field ...
 243         (struct i386_opcode_modifier): ... here.
 244         * i386-opc.tbl (RegMem): Define.
 245         (mov, movq): Move RegMem on segment, control, debug, and test
 246         register flavors.
 247         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 248         to non-SSE2AVX flavor.
 249         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 250         Move RegMem on register only flavors. Drop IgnoreSize from
 251         legacy encoding flavors.
 252         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 253         flavors.
 254         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 255         register only flavors.
 256         (vmovd): Move RegMem and drop IgnoreSize on register only
 257         flavor. Change opcode and operand order to store form.
 258         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 259
 260 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 263         entries.
 264         * i386-opc.h (SReg2, SReg3): Replace by ...
 265         (SReg): ... this.
 266         (union i386_operand_type): Replace sreg fields.
 267         * i386-opc.tbl (mov, ): Use SReg.
 268         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 269         register flavors.
 270         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 271         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 272
 273 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 274
 275         * bpf-desc.c: Regenerate.
 276         * bpf-opc.c: Likewise.
 277         * bpf-opc.h: Likewise.
 278
 279 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 280
 281         * bpf-desc.c: Regenerate.
 282         * bpf-opc.c: Likewise.
 283
 284 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 285
 286         * arm-dis.c (print_insn_coprocessor): Rename index to
 287         index_operand.
 288
 289 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 290
 291         * riscv-opc.c (riscv_insn_types): Add r4 type.
 292
 293         * riscv-opc.c (riscv_insn_types): Add b and j type.
 294
 295         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 296         format for sb type and correct s type.
 297
 298 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 299
 300         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 301         SVE FMOV alias of FCPY.
 302
 303 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 304
 305         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 306         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 307
 308 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 309
 310         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 311         registers in an instruction prefixed by MOVPRFX.
 312
 313 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 314
 315         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 316         sve_size_13 icode to account for variant behaviour of
 317         pmull{t,b}.
 318         * aarch64-dis-2.c: Regenerate.
 319         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 320         sve_size_13 icode to account for variant behaviour of
 321         pmull{t,b}.
 322         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 323         (OP_SVE_VVV_Q_D): Add new qualifier.
 324         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 325         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 326         AES and those not.
 327
 328 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 329
 330         * opcodes/i386-gen.c (operand_type_init): Remove
 331         OPERAND_TYPE_VEC_IMM4 entry.
 332         (operand_types): Remove Vec_Imm4.
 333         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 334         (union i386_operand_type): Remove vec_imm4.
 335         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 336         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 337
 338 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 339
 340         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 341         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 342         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 343         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 344         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 345         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 346         * i386-tbl.h: Re-generate.
 347
 348 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 351         register operands.
 352         * i386-tbl.h: Re-generate.
 353
 354 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-opc.tbl (C): New.
 357         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 358         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 359         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 360         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 361         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 362         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 363         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 364         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 365         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 366         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 367         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 368         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 369         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 370         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 371         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 372         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 373         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 374         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 375         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 376         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 377         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 378         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 379         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 380         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 381         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 382         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 383         flavors.
 384         * i386-tbl.h: Re-generate.
 385
 386 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 389         register operands.
 390         * i386-tbl.h: Re-generate.
 391
 392 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 395         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 396         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 397         * i386-tbl.h: Re-generate.
 398
 399 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 400
 401         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 402         Disp8MemShift from register only templates.
 403         * i386-tbl.h: Re-generate.
 404
 405 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 408         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 409         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 410         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 411         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 412         EVEX_W_0F11_P_3_M_1): Delete.
 413         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 414         EVEX_W_0F11_P_3): New.
 415         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 416         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 417         MOD_EVEX_0F11_PREFIX_3 table entries.
 418         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 419         PREFIX_EVEX_0F11 table entries.
 420         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 421         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 422         EVEX_W_0F11_P_3_M_{0,1} table entries.
 423
 424 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 427         Delete.
 428
 429 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 430
 431         PR binutils/24719
 432         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 433         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 434         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 435         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 436         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 437         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 438         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 439         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 440         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 441         PREFIX_EVEX_0F38C6_REG_6 entries.
 442         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 443         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 444         EVEX_W_0F38C7_R_6_P_2 entries.
 445         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 446         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 447         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 448         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 449         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 450         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 451         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 452
 453 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 454
 455         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 456         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 457         VEX_LEN_0F2D_P_3): Delete.
 458         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 459         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 460         (prefix_table): ... here.
 461
 462 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-dis.c (Iq): Delete.
 465         (Id): New.
 466         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 467         TBM insns.
 468         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 469         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 470         (OP_E_memory): Also honor needindex when deciding whether an
 471         address size prefix needs printing.
 472         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 473
 474 2019-06-26  Jim Wilson  <jimw@sifive.com>
 475
 476         PR binutils/24739
 477         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 478         Set info->display_endian to info->endian_code.
 479
 480 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 483         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 484         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 485         OPERAND_TYPE_ACC64 entries.
 486         * i386-init.h: Re-generate.
 487
 488 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 491         Delete.
 492         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 493         of dqa_mode.
 494         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 495         entries here.
 496         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 497         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 498
 499 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 502         variables.
 503
 504 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 507         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 508         movnti.
 509         * i386-opc.tbl (movnti): Add IgnoreSize.
 510         * i386-tbl.h: Re-generate.
 511
 512 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 515         * i386-tbl.h: Re-generate.
 516
 517 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 518
 519         * i386-dis-evex.h: Break into ...
 520         * i386-dis-evex-len.h: New file.
 521         * i386-dis-evex-mod.h: Likewise.
 522         * i386-dis-evex-prefix.h: Likewise.
 523         * i386-dis-evex-reg.h: Likewise.
 524         * i386-dis-evex-w.h: Likewise.
 525         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 526         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 527         i386-dis-evex-mod.h.
 528
 529 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         PR binutils/24700
 532         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 533         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 534         EVEX_W_0F385B_P_2.
 535         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 536         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 537         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 538         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 539         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 540         EVEX_LEN_0F385B_P_2_W_1.
 541         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 542         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 543         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 544         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 545         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 546         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 547         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 548         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 549         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 550         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 551
 552 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         PR binutils/24691
 555         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 556         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 557         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 558         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 559         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 560         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 561         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 562         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 563         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 564         EVEX_LEN_0F3A43_P_2_W_1.
 565         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 566         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 567         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 568         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 569         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 570         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 571         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 572         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 573         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 574         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 575         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 576         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 577
 578 2019-06-14  Nick Clifton  <nickc@redhat.com>
 579
 580         * po/fr.po; Updated French translation.
 581
 582 2019-06-13  Stafford Horne  <shorne@gmail.com>
 583
 584         * or1k-asm.c: Regenerated.
 585         * or1k-desc.c: Regenerated.
 586         * or1k-desc.h: Regenerated.
 587         * or1k-dis.c: Regenerated.
 588         * or1k-ibld.c: Regenerated.
 589         * or1k-opc.c: Regenerated.
 590         * or1k-opc.h: Regenerated.
 591         * or1k-opinst.c: Regenerated.
 592
 593 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 594
 595         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 596
 597 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 598
 599         PR binutils/24633
 600         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 601         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 602         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 603         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 604         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 605         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 606         EVEX_LEN_0F3A1B_P_2_W_1.
 607         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 608         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 609         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 610         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 611         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 612         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 613         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 614         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 615
 616 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 617
 618         PR binutils/24626
 619         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 620         EVEX.vvvv when disassembling VEX and EVEX instructions.
 621         (OP_VEX): Set vex.register_specifier to 0 after readding
 622         vex.register_specifier.
 623         (OP_Vex_2src_1): Likewise.
 624         (OP_Vex_2src_2): Likewise.
 625         (OP_LWP_E): Likewise.
 626         (OP_EX_Vex): Don't check vex.register_specifier.
 627         (OP_XMM_Vex): Likewise.
 628
 629 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 630             Lili Cui  <lili.cui@intel.com>
 631
 632         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 633         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 634         instructions.
 635         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 636         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 637         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 638         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 639         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 640         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 641         * i386-init.h: Regenerated.
 642         * i386-tbl.h: Likewise.
 643
 644 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 645             Lili Cui  <lili.cui@intel.com>
 646
 647         * doc/c-i386.texi: Document enqcmd.
 648         * testsuite/gas/i386/enqcmd-intel.d: New file.
 649         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 650         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 651         * testsuite/gas/i386/enqcmd.d: Likewise.
 652         * testsuite/gas/i386/enqcmd.s: Likewise.
 653         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 654         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 655         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 656         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 657         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 658         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 659         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 660         and x86-64-enqcmd.
 661
 662 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 663
 664         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 665
 666 2019-06-03  Alan Modra  <amodra@gmail.com>
 667
 668         * ppc-dis.c (prefix_opcd_indices): Correct size.
 669
 670 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 671
 672         PR gas/24625
 673         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 674         Disp8ShiftVL.
 675         * i386-tbl.h: Regenerated.
 676
 677 2019-05-24  Alan Modra  <amodra@gmail.com>
 678
 679         * po/POTFILES.in: Regenerate.
 680
 681 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 682             Alan Modra  <amodra@gmail.com>
 683
 684         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 685         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 686         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 687         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 688         XTOP>): Define and add entries.
 689         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 690         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 691         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 692         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 693
 694 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 695             Alan Modra  <amodra@gmail.com>
 696
 697         * ppc-dis.c (ppc_opts): Add "future" entry.
 698         (PREFIX_OPCD_SEGS): Define.
 699         (prefix_opcd_indices): New array.
 700         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 701         (lookup_prefix): New function.
 702         (print_insn_powerpc): Handle 64-bit prefix instructions.
 703         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 704         (PMRR, POWERXX): Define.
 705         (prefix_opcodes): New instruction table.
 706         (prefix_num_opcodes): New constant.
 707
 708 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 709
 710         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 711         * configure: Regenerated.
 712         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 713         and cpu/bpf.opc.
 714         (HFILES): Add bpf-desc.h and bpf-opc.h.
 715         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 716         bpf-ibld.c and bpf-opc.c.
 717         (BPF_DEPS): Define.
 718         * Makefile.in: Regenerated.
 719         * disassemble.c (ARCH_bpf): Define.
 720         (disassembler): Add case for bfd_arch_bpf.
 721         (disassemble_init_for_target): Likewise.
 722         (enum epbf_isa_attr): Define.
 723         * disassemble.h: extern print_insn_bpf.
 724         * bpf-asm.c: Generated.
 725         * bpf-opc.h: Likewise.
 726         * bpf-opc.c: Likewise.
 727         * bpf-ibld.c: Likewise.
 728         * bpf-dis.c: Likewise.
 729         * bpf-desc.h: Likewise.
 730         * bpf-desc.c: Likewise.
 731
 732 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 733
 734         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 735         and VMSR with the new operands.
 736
 737 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 738
 739         * arm-dis.c (enum mve_instructions): New enum
 740         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 741         and cneg.
 742         (mve_opcodes): New instructions as above.
 743         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 744         csneg and csel.
 745         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 746
 747 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 748
 749         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 750         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 751         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 752         uqshl, urshrl and urshr.
 753         (is_mve_okay_in_it): Add new instructions to TRUE list.
 754         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 755         (print_insn_mve): Updated to accept new %j,
 756         %<bitfield>m and %<bitfield>n patterns.
 757
 758 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 759
 760         * mips-opc.c (mips_builtin_opcodes): Change source register
 761         constraint for DAUI.
 762
 763 2019-05-20  Nick Clifton  <nickc@redhat.com>
 764
 765         * po/fr.po: Updated French translation.
 766
 767 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 768             Michael Collison <michael.collison@arm.com>
 769
 770         * arm-dis.c (thumb32_opcodes): Add new instructions.
 771         (enum mve_instructions): Likewise.
 772         (enum mve_undefined): Add new reasons.
 773         (is_mve_encoding_conflict): Handle new instructions.
 774         (is_mve_undefined): Likewise.
 775         (is_mve_unpredictable): Likewise.
 776         (print_mve_undefined): Likewise.
 777         (print_mve_size): Likewise.
 778
 779 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 780             Michael Collison <michael.collison@arm.com>
 781
 782         * arm-dis.c (thumb32_opcodes): Add new instructions.
 783         (enum mve_instructions): Likewise.
 784         (is_mve_encoding_conflict): Handle new instructions.
 785         (is_mve_undefined): Likewise.
 786         (is_mve_unpredictable): Likewise.
 787         (print_mve_size): Likewise.
 788
 789 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 790             Michael Collison <michael.collison@arm.com>
 791
 792         * arm-dis.c (thumb32_opcodes): Add new instructions.
 793         (enum mve_instructions): Likewise.
 794         (is_mve_encoding_conflict): Likewise.
 795         (is_mve_unpredictable): Likewise.
 796         (print_mve_size): Likewise.
 797
 798 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 799             Michael Collison <michael.collison@arm.com>
 800
 801         * arm-dis.c (thumb32_opcodes): Add new instructions.
 802         (enum mve_instructions): Likewise.
 803         (is_mve_encoding_conflict): Handle new instructions.
 804         (is_mve_undefined): Likewise.
 805         (is_mve_unpredictable): Likewise.
 806         (print_mve_size): Likewise.
 807
 808 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 809             Michael Collison <michael.collison@arm.com>
 810
 811         * arm-dis.c (thumb32_opcodes): Add new instructions.
 812         (enum mve_instructions): Likewise.
 813         (is_mve_encoding_conflict): Handle new instructions.
 814         (is_mve_undefined): Likewise.
 815         (is_mve_unpredictable): Likewise.
 816         (print_mve_size): Likewise.
 817         (print_insn_mve): Likewise.
 818
 819 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 820             Michael Collison <michael.collison@arm.com>
 821
 822         * arm-dis.c (thumb32_opcodes): Add new instructions.
 823         (print_insn_thumb32): Handle new instructions.
 824
 825 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 826             Michael Collison <michael.collison@arm.com>
 827
 828         * arm-dis.c (enum mve_instructions): Add new instructions.
 829         (enum mve_undefined): Add new reasons.
 830         (is_mve_encoding_conflict): Handle new instructions.
 831         (is_mve_undefined): Likewise.
 832         (is_mve_unpredictable): Likewise.
 833         (print_mve_undefined): Likewise.
 834         (print_mve_size): Likewise.
 835         (print_mve_shift_n): Likewise.
 836         (print_insn_mve): Likewise.
 837
 838 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 839             Michael Collison <michael.collison@arm.com>
 840
 841         * arm-dis.c (enum mve_instructions): Add new instructions.
 842         (is_mve_encoding_conflict): Handle new instructions.
 843         (is_mve_unpredictable): Likewise.
 844         (print_mve_rotate): Likewise.
 845         (print_mve_size): Likewise.
 846         (print_insn_mve): Likewise.
 847
 848 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 849             Michael Collison <michael.collison@arm.com>
 850
 851         * arm-dis.c (enum mve_instructions): Add new instructions.
 852         (is_mve_encoding_conflict): Handle new instructions.
 853         (is_mve_unpredictable): Likewise.
 854         (print_mve_size): Likewise.
 855         (print_insn_mve): Likewise.
 856
 857 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 858             Michael Collison <michael.collison@arm.com>
 859
 860         * arm-dis.c (enum mve_instructions): Add new instructions.
 861         (enum mve_undefined): Add new reasons.
 862         (is_mve_encoding_conflict): Handle new instructions.
 863         (is_mve_undefined): Likewise.
 864         (is_mve_unpredictable): Likewise.
 865         (print_mve_undefined): Likewise.
 866         (print_mve_size): Likewise.
 867         (print_insn_mve): Likewise.
 868
 869 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 870             Michael Collison <michael.collison@arm.com>
 871
 872         * arm-dis.c (enum mve_instructions): Add new instructions.
 873         (is_mve_encoding_conflict): Handle new instructions.
 874         (is_mve_undefined): Likewise.
 875         (is_mve_unpredictable): Likewise.
 876         (print_mve_size): Likewise.
 877         (print_insn_mve): Likewise.
 878
 879 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 880             Michael Collison <michael.collison@arm.com>
 881
 882         * arm-dis.c (enum mve_instructions): Add new instructions.
 883         (enum mve_unpredictable): Add new reasons.
 884         (enum mve_undefined): Likewise.
 885         (is_mve_okay_in_it): Handle new isntructions.
 886         (is_mve_encoding_conflict): Likewise.
 887         (is_mve_undefined): Likewise.
 888         (is_mve_unpredictable): Likewise.
 889         (print_mve_vmov_index): Likewise.
 890         (print_simd_imm8): Likewise.
 891         (print_mve_undefined): Likewise.
 892         (print_mve_unpredictable): Likewise.
 893         (print_mve_size): Likewise.
 894         (print_insn_mve): Likewise.
 895
 896 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 897             Michael Collison <michael.collison@arm.com>
 898
 899         * arm-dis.c (enum mve_instructions): Add new instructions.
 900         (enum mve_unpredictable): Add new reasons.
 901         (enum mve_undefined): Likewise.
 902         (is_mve_encoding_conflict): Handle new instructions.
 903         (is_mve_undefined): Likewise.
 904         (is_mve_unpredictable): Likewise.
 905         (print_mve_undefined): Likewise.
 906         (print_mve_unpredictable): Likewise.
 907         (print_mve_rounding_mode): Likewise.
 908         (print_mve_vcvt_size): Likewise.
 909         (print_mve_size): Likewise.
 910         (print_insn_mve): Likewise.
 911
 912 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 913             Michael Collison <michael.collison@arm.com>
 914
 915         * arm-dis.c (enum mve_instructions): Add new instructions.
 916         (enum mve_unpredictable): Add new reasons.
 917         (enum mve_undefined): Likewise.
 918         (is_mve_undefined): Handle new instructions.
 919         (is_mve_unpredictable): Likewise.
 920         (print_mve_undefined): Likewise.
 921         (print_mve_unpredictable): Likewise.
 922         (print_mve_size): Likewise.
 923         (print_insn_mve): Likewise.
 924
 925 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 926             Michael Collison <michael.collison@arm.com>
 927
 928         * arm-dis.c (enum mve_instructions): Add new instructions.
 929         (enum mve_undefined): Add new reasons.
 930         (insns): Add new instructions.
 931         (is_mve_encoding_conflict):
 932         (print_mve_vld_str_addr): New print function.
 933         (is_mve_undefined): Handle new instructions.
 934         (is_mve_unpredictable): Likewise.
 935         (print_mve_undefined): Likewise.
 936         (print_mve_size): Likewise.
 937         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 938         (print_insn_mve):  Handle new operands.
 939
 940 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 941             Michael Collison <michael.collison@arm.com>
 942
 943         * arm-dis.c (enum mve_instructions): Add new instructions.
 944         (enum mve_unpredictable): Add new reasons.
 945         (is_mve_encoding_conflict): Handle new instructions.
 946         (is_mve_unpredictable): Likewise.
 947         (mve_opcodes): Add new instructions.
 948         (print_mve_unpredictable): Handle new reasons.
 949         (print_mve_register_blocks): New print function.
 950         (print_mve_size): Handle new instructions.
 951         (print_insn_mve): Likewise.
 952
 953 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 954             Michael Collison <michael.collison@arm.com>
 955
 956         * arm-dis.c (enum mve_instructions): Add new instructions.
 957         (enum mve_unpredictable): Add new reasons.
 958         (enum mve_undefined): Likewise.
 959         (is_mve_encoding_conflict): Handle new instructions.
 960         (is_mve_undefined): Likewise.
 961         (is_mve_unpredictable): Likewise.
 962         (coprocessor_opcodes): Move NEON VDUP from here...
 963         (neon_opcodes): ... to here.
 964         (mve_opcodes): Add new instructions.
 965         (print_mve_undefined):  Handle new reasons.
 966         (print_mve_unpredictable): Likewise.
 967         (print_mve_size): Handle new instructions.
 968         (print_insn_neon): Handle vdup.
 969         (print_insn_mve): Handle new operands.
 970
 971 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 972             Michael Collison <michael.collison@arm.com>
 973
 974         * arm-dis.c (enum mve_instructions): Add new instructions.
 975         (enum mve_unpredictable): Add new values.
 976         (mve_opcodes): Add new instructions.
 977         (vec_condnames): New array with vector conditions.
 978         (mve_predicatenames): New array with predicate suffixes.
 979         (mve_vec_sizename): New array with vector sizes.
 980         (enum vpt_pred_state): New enum with vector predication states.
 981         (struct vpt_block): New struct type for vpt blocks.
 982         (vpt_block_state): Global struct to keep track of state.
 983         (mve_extract_pred_mask): New helper function.
 984         (num_instructions_vpt_block): Likewise.
 985         (mark_outside_vpt_block): Likewise.
 986         (mark_inside_vpt_block): Likewise.
 987         (invert_next_predicate_state): Likewise.
 988         (update_next_predicate_state): Likewise.
 989         (update_vpt_block_state): Likewise.
 990         (is_vpt_instruction): Likewise.
 991         (is_mve_encoding_conflict): Add entries for new instructions.
 992         (is_mve_unpredictable): Likewise.
 993         (print_mve_unpredictable): Handle new cases.
 994         (print_instruction_predicate): Likewise.
 995         (print_mve_size): New function.
 996         (print_vec_condition): New function.
 997         (print_insn_mve): Handle vpt blocks and new print operands.
 998
 999 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1000
1001         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1002         8, 14 and 15 for Armv8.1-M Mainline.
1003
1004 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1005             Michael Collison <michael.collison@arm.com>
1006
1007         * arm-dis.c (enum mve_instructions): New enum.
1008         (enum mve_unpredictable): Likewise.
1009         (enum mve_undefined): Likewise.
1010         (struct mopcode32): New struct.
1011         (is_mve_okay_in_it): New function.
1012         (is_mve_architecture): Likewise.
1013         (arm_decode_field): Likewise.
1014         (arm_decode_field_multiple): Likewise.
1015         (is_mve_encoding_conflict): Likewise.
1016         (is_mve_undefined): Likewise.
1017         (is_mve_unpredictable): Likewise.
1018         (print_mve_undefined): Likewise.
1019         (print_mve_unpredictable): Likewise.
1020         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1021         (print_insn_mve): New function.
1022         (print_insn_thumb32): Handle MVE architecture.
1023         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1024
1025 2019-05-10  Nick Clifton  <nickc@redhat.com>
1026
1027         PR 24538
1028         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1029         end of the table prematurely.
1030
1031 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1032
1033         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1034         macros for R6.
1035
1036 2019-05-11  Alan Modra  <amodra@gmail.com>
1037
1038         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1039         when -Mraw is in effect.
1040
1041 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1042
1043         * aarch64-dis-2.c: Regenerate.
1044         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1045         (OP_SVE_BBB): New variant set.
1046         (OP_SVE_DDDD): New variant set.
1047         (OP_SVE_HHH): New variant set.
1048         (OP_SVE_HHHU): New variant set.
1049         (OP_SVE_SSS): New variant set.
1050         (OP_SVE_SSSU): New variant set.
1051         (OP_SVE_SHH): New variant set.
1052         (OP_SVE_SBBU): New variant set.
1053         (OP_SVE_DSS): New variant set.
1054         (OP_SVE_DHHU): New variant set.
1055         (OP_SVE_VMV_HSD_BHS): New variant set.
1056         (OP_SVE_VVU_HSD_BHS): New variant set.
1057         (OP_SVE_VVVU_SD_BH): New variant set.
1058         (OP_SVE_VVVU_BHSD): New variant set.
1059         (OP_SVE_VVV_QHD_DBS): New variant set.
1060         (OP_SVE_VVV_HSD_BHS): New variant set.
1061         (OP_SVE_VVV_HSD_BHS2): New variant set.
1062         (OP_SVE_VVV_BHS_HSD): New variant set.
1063         (OP_SVE_VV_BHS_HSD): New variant set.
1064         (OP_SVE_VVV_SD): New variant set.
1065         (OP_SVE_VVU_BHS_HSD): New variant set.
1066         (OP_SVE_VZVV_SD): New variant set.
1067         (OP_SVE_VZVV_BH): New variant set.
1068         (OP_SVE_VZV_SD): New variant set.
1069         (aarch64_opcode_table): Add sve2 instructions.
1070
1071 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1072
1073         * aarch64-asm-2.c: Regenerated.
1074         * aarch64-dis-2.c: Regenerated.
1075         * aarch64-opc-2.c: Regenerated.
1076         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1077         for SVE_SHLIMM_UNPRED_22.
1078         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1079         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1080         operand.
1081
1082 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1083
1084         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1085         sve_size_tsz_bhs iclass encode.
1086         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1087         sve_size_tsz_bhs iclass decode.
1088
1089 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1090
1091         * aarch64-asm-2.c: Regenerated.
1092         * aarch64-dis-2.c: Regenerated.
1093         * aarch64-opc-2.c: Regenerated.
1094         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1095         for SVE_Zm4_11_INDEX.
1096         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1097         (fields): Handle SVE_i2h field.
1098         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1099         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1100
1101 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1102
1103         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1104         sve_shift_tsz_bhsd iclass encode.
1105         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1106         sve_shift_tsz_bhsd iclass decode.
1107
1108 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1109
1110         * aarch64-asm-2.c: Regenerated.
1111         * aarch64-dis-2.c: Regenerated.
1112         * aarch64-opc-2.c: Regenerated.
1113         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1114         (aarch64_encode_variant_using_iclass): Handle
1115         sve_shift_tsz_hsd iclass encode.
1116         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1117         sve_shift_tsz_hsd iclass decode.
1118         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1119         for SVE_SHRIMM_UNPRED_22.
1120         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1121         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1122         operand.
1123
1124 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1125
1126         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1127         sve_size_013 iclass encode.
1128         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1129         sve_size_013 iclass decode.
1130
1131 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1132
1133         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1134         sve_size_bh iclass encode.
1135         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1136         sve_size_bh iclass decode.
1137
1138 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1139
1140         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1141         sve_size_sd2 iclass encode.
1142         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1143         sve_size_sd2 iclass decode.
1144         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1145         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1146
1147 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1148
1149         * aarch64-asm-2.c: Regenerated.
1150         * aarch64-dis-2.c: Regenerated.
1151         * aarch64-opc-2.c: Regenerated.
1152         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1153         for SVE_ADDR_ZX.
1154         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1155         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1156
1157 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1158
1159         * aarch64-asm-2.c: Regenerated.
1160         * aarch64-dis-2.c: Regenerated.
1161         * aarch64-opc-2.c: Regenerated.
1162         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1163         for SVE_Zm3_11_INDEX.
1164         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1165         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1166         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1167         fields.
1168         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1169
1170 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1171
1172         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1173         sve_size_hsd2 iclass encode.
1174         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1175         sve_size_hsd2 iclass decode.
1176         * aarch64-opc.c (fields): Handle SVE_size field.
1177         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1178
1179 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1180
1181         * aarch64-asm-2.c: Regenerated.
1182         * aarch64-dis-2.c: Regenerated.
1183         * aarch64-opc-2.c: Regenerated.
1184         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1185         for SVE_IMM_ROT3.
1186         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1187         (fields): Handle SVE_rot3 field.
1188         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1189         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1190
1191 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1192
1193         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1194         instructions.
1195
1196 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1197
1198         * aarch64-tbl.h
1199         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1200         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1201         aarch64_feature_sve2bitperm): New feature sets.
1202         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1203         for feature set addresses.
1204         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1205         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1206
1207 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1208             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1209
1210         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1211         argument and set ASE_EVA_R6 appropriately.
1212         (set_default_mips_dis_options): Pass ISA to above.
1213         (parse_mips_dis_option): Likewise.
1214         * mips-opc.c (EVAR6): New macro.
1215         (mips_builtin_opcodes): Add llwpe, scwpe.
1216
1217 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1218
1219         * aarch64-asm-2.c: Regenerated.
1220         * aarch64-dis-2.c: Regenerated.
1221         * aarch64-opc-2.c: Regenerated.
1222         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1223         AARCH64_OPND_TME_UIMM16.
1224         (aarch64_print_operand): Likewise.
1225         * aarch64-tbl.h (QL_IMM_NIL): New.
1226         (TME): New.
1227         (_TME_INSN): New.
1228         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1229
1230 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1231
1232         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1233
1234 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1235             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1236
1237         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1238
1239 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1240
1241         * s12z-opc.h: Add extern "C" bracketing to help
1242         users who wish to use this interface in c++ code.
1243
1244 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1245
1246         * s12z-opc.c (bm_decode): Handle bit map operations with the
1247         "reserved0" mode.
1248
1249 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1250
1251         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1252         specifier.  Add entries for VLDR and VSTR of system registers.
1253         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1254         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1255         of %J and %K format specifier.
1256
1257 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1258
1259         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1260         Add new entries for VSCCLRM instruction.
1261         (print_insn_coprocessor): Handle new %C format control code.
1262
1263 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1264
1265         * arm-dis.c (enum isa): New enum.
1266         (struct sopcode32): New structure.
1267         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1268         set isa field of all current entries to ANY.
1269         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1270         Only match an entry if its isa field allows the current mode.
1271
1272 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1273
1274         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1275         CLRM.
1276         (print_insn_thumb32): Add logic to print %n CLRM register list.
1277
1278 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1279
1280         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1281         and %Q patterns.
1282
1283 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1284
1285         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1286         (print_insn_thumb32): Edit the switch case for %Z.
1287
1288 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1289
1290         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1291
1292 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1293
1294         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1295
1296 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1297
1298         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1299
1300 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1301
1302         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1303         Arm register with r13 and r15 unpredictable.
1304         (thumb32_opcodes): New instructions for bfx and bflx.
1305
1306 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1307
1308         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1309
1310 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1311
1312         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1313
1314 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1315
1316         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1317
1318 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1319
1320         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1321
1322 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1323
1324         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1325         "optr". ("operator" is a reserved word in c++).
1326
1327 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1328
1329         * aarch64-opc.c (aarch64_print_operand): Add case for
1330         AARCH64_OPND_Rt_SP.
1331         (verify_constraints): Likewise.
1332         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1333         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1334         to accept Rt|SP as first operand.
1335         (AARCH64_OPERANDS): Add new Rt_SP.
1336         * aarch64-asm-2.c: Regenerated.
1337         * aarch64-dis-2.c: Regenerated.
1338         * aarch64-opc-2.c: Regenerated.
1339
1340 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1341
1342         * aarch64-asm-2.c: Regenerated.
1343         * aarch64-dis-2.c: Likewise.
1344         * aarch64-opc-2.c: Likewise.
1345         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1346
1347 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1348
1349         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1350
1351 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1352
1353         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1354         * i386-init.h: Regenerated.
1355
1356 2019-04-07  Alan Modra  <amodra@gmail.com>
1357
1358         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1359         op_separator to control printing of spaces, comma and parens
1360         rather than need_comma, need_paren and spaces vars.
1361
1362 2019-04-07  Alan Modra  <amodra@gmail.com>
1363
1364         PR 24421
1365         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1366         (print_insn_neon, print_insn_arm): Likewise.
1367
1368 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1369
1370         * i386-dis-evex.h (evex_table): Updated to support BF16
1371         instructions.
1372         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1373         and EVEX_W_0F3872_P_3.
1374         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1375         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1376         * i386-opc.h (enum): Add CpuAVX512_BF16.
1377         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1378         * i386-opc.tbl: Add AVX512 BF16 instructions.
1379         * i386-init.h: Regenerated.
1380         * i386-tbl.h: Likewise.
1381
1382 2019-04-05  Alan Modra  <amodra@gmail.com>
1383
1384         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1385         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1386         to favour printing of "-" branch hint when using the "y" bit.
1387         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1388
1389 2019-04-05  Alan Modra  <amodra@gmail.com>
1390
1391         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1392         opcode until first operand is output.
1393
1394 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1395
1396         PR gas/24349
1397         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1398         (valid_bo_post_v2): Add support for 'at' branch hints.
1399         (insert_bo): Only error on branch on ctr.
1400         (get_bo_hint_mask): New function.
1401         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1402         for inserting 'at' branch hints.
1403         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1404         for extracting 'at' branch hints.
1405         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1406         (BOE): Delete operand.
1407         (BOM, BOP): New operands.
1408         (RM): Update value.
1409         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1410         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1411         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1412         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1413         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1414         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1415         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1416         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1417         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1418         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1419         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1420         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1421         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1422         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1423         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1424         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1425         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1426         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1427         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1428         bttarl+>: New extended mnemonics.
1429
1430 2019-03-28  Alan Modra  <amodra@gmail.com>
1431
1432         PR 24390
1433         * ppc-opc.c (BTF): Define.
1434         (powerpc_opcodes): Use for mtfsb*.
1435         * ppc-dis.c (print_insn_powerpc): Print fields with both
1436         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1437
1438 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1439
1440         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1441         (mapping_symbol_for_insn): Implement new algorithm.
1442         (print_insn): Remove duplicate code.
1443
1444 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1445
1446         * aarch64-dis.c (print_insn_aarch64):
1447         Implement override.
1448
1449 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1450
1451         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1452         order.
1453
1454 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1455
1456         * aarch64-dis.c (last_stop_offset): New.
1457         (print_insn_aarch64): Use stop_offset.
1458
1459 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1460
1461         PR gas/24359
1462         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1463         CPU_ANY_AVX2_FLAGS.
1464         * i386-init.h: Regenerated.
1465
1466 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1467
1468         PR gas/24348
1469         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1470         vmovdqu16, vmovdqu32 and vmovdqu64.
1471         * i386-tbl.h: Regenerated.
1472
1473 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1474
1475         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1476         from vstrszb, vstrszh, and vstrszf.
1477
1478 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1479
1480         * s390-opc.txt: Add instruction descriptions.
1481
1482 2019-02-08  Jim Wilson  <jimw@sifive.com>
1483
1484         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1485         <bne>: Likewise.
1486
1487 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1488
1489         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1490
1491 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1492
1493         PR binutils/23212
1494         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1495         * aarch64-opc.c (verify_elem_sd): New.
1496         (fields): Add FLD_sz entr.
1497         * aarch64-tbl.h (_SIMD_INSN): New.
1498         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1499         fmulx scalar and vector by element isns.
1500
1501 2019-02-07  Nick Clifton  <nickc@redhat.com>
1502
1503         * po/sv.po: Updated Swedish translation.
1504
1505 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1506
1507         * s390-mkopc.c (main): Accept arch13 as cpu string.
1508         * s390-opc.c: Add new instruction formats and instruction opcode
1509         masks.
1510         * s390-opc.txt: Add new arch13 instructions.
1511
1512 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1513
1514         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1515         (aarch64_opcode): Change encoding for stg, stzg
1516         st2g and st2zg.
1517         * aarch64-asm-2.c: Regenerated.
1518         * aarch64-dis-2.c: Regenerated.
1519         * aarch64-opc-2.c: Regenerated.
1520
1521 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1522
1523         * aarch64-asm-2.c: Regenerated.
1524         * aarch64-dis-2.c: Likewise.
1525         * aarch64-opc-2.c: Likewise.
1526         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1527
1528 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1529             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1530
1531         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1532         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1533         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1534         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1535         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1536         case for ldstgv_indexed.
1537         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1538         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1539         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1540         * aarch64-asm-2.c: Regenerated.
1541         * aarch64-dis-2.c: Regenerated.
1542         * aarch64-opc-2.c: Regenerated.
1543
1544 2019-01-23  Nick Clifton  <nickc@redhat.com>
1545
1546         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1547
1548 2019-01-21  Nick Clifton  <nickc@redhat.com>
1549
1550         * po/de.po: Updated German translation.
1551         * po/uk.po: Updated Ukranian translation.
1552
1553 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1554         * mips-dis.c (mips_arch_choices): Fix typo in
1555         gs464, gs464e and gs264e descriptors.
1556
1557 2019-01-19  Nick Clifton  <nickc@redhat.com>
1558
1559         * configure: Regenerate.
1560         * po/opcodes.pot: Regenerate.
1561
1562 2018-06-24  Nick Clifton  <nickc@redhat.com>
1563
1564         2.32 branch created.
1565
1566 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1567
1568         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1569         if it is null.
1570         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1571         zero.
1572
1573 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1574
1575         * configure: Regenerate.
1576
1577 2019-01-07  Alan Modra  <amodra@gmail.com>
1578
1579         * configure: Regenerate.
1580         * po/POTFILES.in: Regenerate.
1581
1582 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1583
1584         * s12z-opc.c: New file.
1585         * s12z-opc.h: New file.
1586         * s12z-dis.c: Removed all code not directly related to display
1587         of instructions.  Used the interface provided by the new files
1588         instead.
1589         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1590         * Makefile.in: Regenerate.
1591         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1592         * configure: Regenerate.
1593
1594 2019-01-01  Alan Modra  <amodra@gmail.com>
1595
1596         Update year range in copyright notice of all files.
1597
1598 For older changes see ChangeLog-2018
1599 \f
1600 Copyright (C) 2019 Free Software Foundation, Inc.
1601
1602 Copying and distribution of this file, with or without modification,
1603 are permitted in any medium without royalty provided the copyright
1604 notice and this notice are preserved.
1605
1606 Local Variables:
1607 mode: change-log
1608 left-margin: 8
1609 fill-column: 74
1610 version-control: never
1611 End: