opcodes/ChangeLog

   1 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
   2
   3         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
   4         replacing NODS.
   5
   6 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
   7
   8         PR binutils/15834
   9         * aarch64-asm.c: Fix typos.
  10         * aarch64-dis.c: Likewise.
  11         * msp430-dis.c: Likewise.
  12
  13 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  14
  15         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
  16         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
  17         Use +H rather than +C for the real "dext".
  18         * mips-opc.c (mips_builtin_opcodes): Likewise.
  19
  20 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
  21
  22         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
  23         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
  24         and OPTIONAL_MAPPED_REG.
  25         * mips-opc.c (decode_mips_operand): Likewise.
  26         * mips16-opc.c (decode_mips16_operand): Likewise.
  27         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
  28
  29 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
  32         (PREFIX_EVEX_0F3A3F): Likewise.
  33         * i386-dis-evex.h (evex_table): Updated.
  34
  35 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
  36
  37         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
  38         VCLIPW.
  39
  40 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
  41             Konrad Eisele  <konrad@gaisler.com>
  42
  43         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
  44         bfd_mach_sparc.
  45         * sparc-opc.c (MASK_LEON): Define.
  46         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
  47         (letandleon): New macro.
  48         (v9andleon): Likewise.
  49         (sparc_opc): Add leon.
  50         (umac): Enable for letandleon.
  51         (smac): Likewise.
  52         (casa): Enable for v9andleon.
  53         (cas): Likewise.
  54         (casl): Likewise.
  55
  56 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
  57             Richard Sandiford  <rdsandiford@googlemail.com>
  58
  59         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
  60         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
  61         (print_vu0_channel): New function.
  62         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
  63         (print_insn_args): Handle '#'.
  64         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  65         * mips-opc.c (mips_vu0_channel_mask): New constant.
  66         (decode_mips_operand): Handle new VU0 operand types.
  67         (VU0, VU0CH): New macros.
  68         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
  69         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
  70         Use "+6" rather than "G" for QMFC2 and QMTC2.
  71
  72 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  73
  74         * mips-formats.h (PCREL): Reorder parameters and update the definition
  75         to match new mips_pcrel_operand layout.
  76         (JUMP, JALX, BRANCH): Update accordingly.
  77         * mips16-opc.c (decode_mips16_operand): Likewise.
  78
  79 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  80
  81         * micromips-opc.c (WR_s): Delete.
  82
  83 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  84
  85         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
  86         New macros.
  87         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
  88         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
  89         (mips_builtin_opcodes): Use the new position-based read-write flags
  90         instead of field-based ones.  Use UDI for "udi..." instructions.
  91         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  92         New macros.
  93         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
  94         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
  95         (WR_SP, RD_16): New macros.
  96         (RD_SP): Redefine as an INSN2_* flag.
  97         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
  98         (mips16_opcodes): Use the new position-based read-write flags
  99         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 100         pinfo2 field.
 101         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 102         New macros.
 103         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 104         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 105         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 106         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 107         (micromips_opcodes): Use the new position-based read-write flags
 108         instead of field-based ones.
 109         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 110         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 111         of field-based flags.
 112
 113 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 114
 115         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 116         (WR_SP): Replace with...
 117         (MOD_SP): ...this.
 118         (mips16_opcodes): Update accordingly.
 119         * mips-dis.c (print_insn_mips16): Likewise.
 120
 121 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 122
 123         * mips16-opc.c (mips16_opcodes): Reformat.
 124
 125 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 126
 127         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 128         for operands that are hard-coded to $0.
 129         * micromips-opc.c (micromips_opcodes): Likewise.
 130
 131 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 132
 133         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 134         for the single-operand forms of JALR and JALR.HB.
 135         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 136         and JALRS.HB.
 137
 138 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 139
 140         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 141         instructions.  Fix them to use WR_MACC instead of WR_CC and
 142         add missing RD_MACCs.
 143
 144 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 145
 146         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 147
 148 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 149
 150         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 151
 152 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 153             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 154             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 155             Sergey Lega  <sergey.s.lega@intel.com>
 156             Anna Tikhonova  <anna.tikhonova@intel.com>
 157             Ilya Tocar  <ilya.tocar@intel.com>
 158             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 159             Ilya Verbin  <ilya.verbin@intel.com>
 160             Kirill Yukhin  <kirill.yukhin@intel.com>
 161             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 162
 163         * i386-dis-evex.h: New.
 164         * i386-dis.c (OP_Rounding): New.
 165         (VPCMP_Fixup): New.
 166         (OP_Mask): New.
 167         (Rdq): New.
 168         (XMxmmq): New.
 169         (EXdScalarS): New.
 170         (EXymm): New.
 171         (EXEvexHalfBcstXmmq): New.
 172         (EXxmm_mdq): New.
 173         (EXEvexXGscat): New.
 174         (EXEvexXNoBcst): New.
 175         (VPCMP): New.
 176         (EXxEVexR): New.
 177         (EXxEVexS): New.
 178         (XMask): New.
 179         (MaskG): New.
 180         (MaskE): New.
 181         (MaskR): New.
 182         (MaskVex): New.
 183         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 184         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 185         evex_rounding_mode, evex_sae_mode, mask_mode.
 186         (USE_EVEX_TABLE): New.
 187         (EVEX_TABLE): New.
 188         (EVEX enum): New.
 189         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 190         REG_EVEX_0F38C7.
 191         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 192         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 193         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 194         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 195         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 196         MOD_EVEX_0F38C7_REG_6.
 197         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 198         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 199         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 200         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 201         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 202         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 203         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 204         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 205         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 206         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 207         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 208         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 209         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 210         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 211         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 212         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 213         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 214         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 215         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 216         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 217         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 218         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 219         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 220         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 221         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 222         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 223         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 224         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 225         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 226         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 227         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 228         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 229         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 230         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 231         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 232         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 233         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 234         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 235         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 236         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 237         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 238         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 239         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 240         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 241         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 242         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 243         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 244         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 245         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 246         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 247         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 248         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 249         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 250         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 251         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 252         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 253         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 254         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 255         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 256         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 257         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 258         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 259         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 260         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 261         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 262         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 263         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 264         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 265         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 266         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 267         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 268         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 269         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 270         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 271         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 272         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 273         PREFIX_EVEX_0F3A55.
 274         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 275         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 276         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 277         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 278         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 279         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 280         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 281         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 282         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 283         VEX_W_0F3A32_P_2_LEN_0.
 284         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 285         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 286         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 287         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 288         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 289         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 290         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 291         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 292         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 293         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 294         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 295         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 296         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 297         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 298         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 299         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 300         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 301         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 302         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 303         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 304         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 305         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 306         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 307         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 308         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 309         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 310         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 311         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 312         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 313         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 314         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 315         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 316         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 317         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 318         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 319         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 320         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 321         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 322         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 323         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 324         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 325         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 326         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 327         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 328         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 329         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 330         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 331         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 332         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 333         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 334         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 335         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 336         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 337         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 338         (struct vex): Add fields evex, r, v, mask_register_specifier,
 339         zeroing, ll, b.
 340         (intel_names_xmm): Add upper 16 registers.
 341         (att_names_xmm): Ditto.
 342         (intel_names_ymm): Ditto.
 343         (att_names_ymm): Ditto.
 344         (names_zmm): New.
 345         (intel_names_zmm): Ditto.
 346         (att_names_zmm): Ditto.
 347         (names_mask): Ditto.
 348         (intel_names_mask): Ditto.
 349         (att_names_mask): Ditto.
 350         (names_rounding): Ditto.
 351         (names_broadcast): Ditto.
 352         (x86_64_table): Add escape to evex-table.
 353         (reg_table): Include reg_table evex-entries from
 354         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 355         (prefix_table): Add entries for new instructions.
 356         (vex_table): Ditto.
 357         (vex_len_table): Ditto.
 358         (vex_w_table): Ditto.
 359         (mod_table): Ditto.
 360         (get_valid_dis386): Properly handle new instructions.
 361         (print_insn): Handle zmm and mask registers, print mask operand.
 362         (intel_operand_size): Support EVEX, new modes and sizes.
 363         (OP_E_register): Handle new modes.
 364         (OP_E_memory): Ditto.
 365         (OP_G): Ditto.
 366         (OP_XMM): Ditto.
 367         (OP_EX): Ditto.
 368         (OP_VEX): Ditto.
 369         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 370         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 371         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 372         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 373         CpuAVX512PF and CpuVREX.
 374         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 375         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 376         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 377         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 378         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 379         * i386-init.h: Regenerate.
 380         * i386-opc.h (CpuAVX512F): New.
 381         (CpuAVX512CD): New.
 382         (CpuAVX512ER): New.
 383         (CpuAVX512PF): New.
 384         (CpuVREX): New.
 385         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 386         cpuavx512pf and cpuvrex fields.
 387         (VecSIB): Add VecSIB512.
 388         (EVex): New.
 389         (Masking): New.
 390         (VecESize): New.
 391         (Broadcast): New.
 392         (StaticRounding): New.
 393         (SAE): New.
 394         (Disp8MemShift): New.
 395         (NoDefMask): New.
 396         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 397         staticrounding, sae, disp8memshift and nodefmask.
 398         (RegZMM): New.
 399         (Zmmword): Ditto.
 400         (Vec_Disp8): Ditto.
 401         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 402         fields.
 403         (RegVRex): New.
 404         * i386-opc.tbl: Add AVX512 instructions.
 405         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 406         registers, mask registers.
 407         * i386-tbl.h: Regenerate.
 408
 409 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 410
 411         PR gas/15220
 412         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 413         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 414
 415 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 416
 417         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 418         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 419         PREFIX_0F3ACC.
 420         (prefix_table): Updated.
 421         (three_byte_table): Likewise.
 422         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 423         (cpu_flags): Add CpuSHA.
 424         (i386_cpu_flags): Add cpusha.
 425         * i386-init.h: Regenerate.
 426         * i386-opc.h (CpuSHA): New.
 427         (CpuUnused): Restored.
 428         (i386_cpu_flags): Add cpusha.
 429         * i386-opc.tbl: Add SHA instructions.
 430         * i386-tbl.h: Regenerate.
 431
 432 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 433             Kirill Yukhin  <kirill.yukhin@intel.com>
 434             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 435
 436         * i386-dis.c (BND_Fixup): New.
 437         (Ebnd): New.
 438         (Ev_bnd): New.
 439         (Gbnd): New.
 440         (BND): New.
 441         (v_bnd_mode): New.
 442         (bnd_mode): New.
 443         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 444         MOD_0F1B_PREFIX_1.
 445         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 446         (dis tables): Replace XX with BND for near branch and call
 447         instructions.
 448         (prefix_table): Add new entries.
 449         (mod_table): Likewise.
 450         (names_bnd): New.
 451         (intel_names_bnd): New.
 452         (att_names_bnd): New.
 453         (BND_PREFIX): New.
 454         (prefix_name): Handle BND_PREFIX.
 455         (print_insn): Initialize names_bnd.
 456         (intel_operand_size): Handle new modes.
 457         (OP_E_register): Likewise.
 458         (OP_E_memory): Likewise.
 459         (OP_G): Likewise.
 460         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 461         (cpu_flags): Add CpuMPX.
 462         (operand_type_init): Add RegBND.
 463         (opcode_modifiers): Add BNDPrefixOk.
 464         (operand_types): Add RegBND.
 465         * i386-init.h: Regenerate.
 466         * i386-opc.h (CpuMPX): New.
 467         (CpuUnused): Comment out.
 468         (i386_cpu_flags): Add cpumpx.
 469         (BNDPrefixOk): New.
 470         (i386_opcode_modifier): Add bndprefixok.
 471         (RegBND): New.
 472         (i386_operand_type): Add regbnd.
 473         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 474         Add MPX instructions and bnd prefix.
 475         * i386-reg.tbl: Add bnd0-bnd3 registers.
 476         * i386-tbl.h: Regenerate.
 477
 478 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 479
 480         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 481         ATTRIBUTE_UNUSED.
 482
 483 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 484
 485         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 486         special rules.
 487         * Makefile.in: Regenerate.
 488         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 489         all fields.  Reformat.
 490
 491 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 492
 493         * mips16-opc.c: Include mips-formats.h.
 494         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 495         static arrays.
 496         (decode_mips16_operand): New function.
 497         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 498         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 499         Abort for OP_SAVE_RESTORE_LIST.
 500         (print_mips16_insn_arg): Change interface.  Use mips_operand
 501         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 502         (print_insn_mips16): ...here.  Call init_print_arg_state.
 503         Update the call to print_mips16_insn_arg.
 504
 505 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 506
 507         * mips-formats.h: New file.
 508         * mips-opc.c: Include mips-formats.h.
 509         (reg_0_map): New static array.
 510         (decode_mips_operand): New function.
 511         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 512         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 513         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 514         (int_c_map): New static arrays.
 515         (decode_micromips_operand): New function.
 516         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 517         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 518         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 519         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 520         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 521         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 522         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 523         (print_reg): New function.
 524         (mips_print_arg_state): New structure.
 525         (init_print_arg_state, print_insn_arg): New functions.
 526         (print_insn_args): Change interface and use mips_operand structures.
 527         Delete GET_OP_S.  Move GET_OP definition to...
 528         (print_insn_mips): ...here.  Update the call to print_insn_args.
 529         (print_insn_micromips): Use print_insn_args.
 530
 531 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 532
 533         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 534         in macros.
 535
 536 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 537
 538         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 539         ADDA.S, MULA.S and SUBA.S.
 540
 541 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 542
 543         PR gas/13572
 544         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 545         * i386-tbl.h: Regenerated.
 546
 547 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 548
 549         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 550         and SD A(B) macros up.
 551         * micromips-opc.c (micromips_opcodes): Likewise.
 552
 553 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 554
 555         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 556         instructions.
 557
 558 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 559
 560         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 561         MDMX-like instructions.
 562         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 563         printing "Q" operands for INSN_5400 instructions.
 564
 565 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 566
 567         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 568         "+S" for "cins".
 569         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 570         Combine cases.
 571
 572 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 573
 574         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 575         "jalx".
 576         * mips16-opc.c (mips16_opcodes): Likewise.
 577         * micromips-opc.c (micromips_opcodes): Likewise.
 578         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 579         (print_insn_mips16): Handle "+i".
 580         (print_insn_micromips): Likewise.  Conditionally preserve the
 581         ISA bit for "a" but not for "+i".
 582
 583 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 584
 585         * micromips-opc.c (WR_mhi): Rename to..
 586         (WR_mh): ...this.
 587         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 588         "mh,mi" with "mh".
 589         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 590         (micromips_to_32_reg_h_map1): ...this.
 591         (micromips_to_32_reg_i_map): Rename to...
 592         (micromips_to_32_reg_h_map2): ...this.
 593         (print_micromips_insn): Remove "mi" case.  Print both registers
 594         in the pair for "mh".
 595
 596 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 597
 598         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 599         * micromips-opc.c (micromips_opcodes): Likewise.
 600         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 601         and "+T" handling.  Check for a "0" suffix when deciding whether to
 602         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 603
 604 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 605
 606         * s390-opc.c (J12_12, J24_24): New macros.
 607         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 608         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 609         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 610
 611 2013-07-04  Alan Modra  <amodra@gmail.com>
 612
 613         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 614
 615 2013-06-26  Nick Clifton  <nickc@redhat.com>
 616
 617         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 618         field when checking for type 2 nop.
 619         * rx-decode.c: Regenerate.
 620
 621 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 622
 623         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 624         and "movep" macros.
 625
 626 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 627
 628         * mips-dis.c (is_mips16_plt_tail): New function.
 629         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 630         word.
 631         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 632
 633 2013-06-21  DJ Delorie  <dj@redhat.com>
 634
 635         * msp430-decode.opc: New.
 636         * msp430-decode.c: New/generated.
 637         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 638         (MAINTAINER_CLEANFILES): Likewise.
 639         Add rule to build msp430-decode.c frommsp430decode.opc
 640         using the opc2c program.
 641         * Makefile.in: Regenerate.
 642         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 643         * configure: Regenerate.
 644
 645 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 646
 647         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 648         (SYMTAB_AVAILABLE): Removed.
 649         (#include "elf/aarch64.h): Ditto.
 650
 651 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 652             Maciej W. Rozycki  <macro@codesourcery.com>
 653             Chao-Ying Fu  <fu@mips.com>
 654
 655         * micromips-opc.c (EVA): Define.
 656         (TLBINV): Define.
 657         (micromips_opcodes): Add EVA opcodes.
 658         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 659         (print_insn_args): Handle EVA offsets.
 660         (print_insn_micromips): Likewise.
 661         * mips-opc.c (EVA): Define.
 662         (TLBINV): Define.
 663         (mips_builtin_opcodes): Add EVA opcodes.
 664
 665 2013-06-17  Alan Modra  <amodra@gmail.com>
 666
 667         * Makefile.am (mips-opc.lo): Add rules to create automatic
 668         dependency files.  Pass archdefs.
 669         (micromips-opc.lo, mips16-opc.lo): Likewise.
 670         * Makefile.in: Regenerate.
 671
 672 2013-06-14  DJ Delorie  <dj@redhat.com>
 673
 674         * rx-decode.opc (rx_decode_opcode): Bit operations on
 675         registers are 32-bit operations, not 8-bit operations.
 676         * rx-decode.c: Regenerate.
 677
 678 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 679
 680         * micromips-opc.c (IVIRT): New define.
 681         (IVIRT64): New define.
 682         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 683         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 684
 685         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 686         dmtgc0 to print cp0 names.
 687
 688 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 689
 690         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 691         argument.
 692
 693 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 694             Richard Sandiford  <rdsandiford@googlemail.com>
 695
 696         * micromips-opc.c (D32, D33, MC): Update definitions.
 697         (micromips_opcodes):  Initialize ase field.
 698         * mips-dis.c (mips_arch_choice): Add ase field.
 699         (mips_arch_choices): Initialize ase field.
 700         (set_default_mips_dis_options): Declare and setup mips_ase.
 701         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 702         MT32, MC): Update definitions.
 703         (mips_builtin_opcodes): Initialize ase field.
 704
 705 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 706
 707         * s390-opc.txt (flogr): Require a register pair destination.
 708
 709 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 710
 711         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 712         instruction format.
 713
 714 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 715
 716         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 717
 718 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 719
 720         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 721         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 722         XLS_MASK, PPCVSX2): New defines.
 723         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 724         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 725         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 726         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 727         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 728         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 729         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 730         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 731         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 732         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 733         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 734         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 735         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 736         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 737         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 738         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 739         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 740         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 741         <lxvx, stxvx>: New extended mnemonics.
 742
 743 2013-05-17  Alan Modra  <amodra@gmail.com>
 744
 745         * ia64-raw.tbl: Replace non-ASCII char.
 746         * ia64-waw.tbl: Likewise.
 747         * ia64-asmtab.c: Regenerate.
 748
 749 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 750
 751         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 752         * i386-init.h: Regenerated.
 753
 754 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 755
 756         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 757         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 758         check from [0, 255] to [-128, 255].
 759
 760 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 761
 762         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 763         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 764         (parse_mips_dis_option): Handle the virt option.
 765         (print_insn_args): Handle "+J".
 766         (print_mips_disassembler_options): Print out message about virt64.
 767         * mips-opc.c (IVIRT): New define.
 768         (IVIRT64): New define.
 769         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 770         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 771         Move rfe to the bottom as it conflicts with tlbgp.
 772
 773 2013-05-09  Alan Modra  <amodra@gmail.com>
 774
 775         * ppc-opc.c (extract_vlesi): Properly sign extend.
 776         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 777
 778 2013-05-02  Nick Clifton  <nickc@redhat.com>
 779
 780         * msp430-dis.c: Add support for MSP430X instructions.
 781
 782 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 783
 784         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 785         to "eccinj".
 786
 787 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 788
 789         PR binutils/15369
 790         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 791         of CGEN_CPU_ENDIAN.
 792         (hash_insns_list): Likewise.
 793
 794 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 795
 796         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 797         warning workaround.
 798
 799 2013-04-08  Jan Beulich <jbeulich@suse.com>
 800
 801         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 802         * i386-tbl.h: Re-generate.
 803
 804 2013-04-06  David S. Miller  <davem@davemloft.net>
 805
 806         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 807         of an opcode, prefer the one with F_PREFERRED set.
 808         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 809         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 810         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 811         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 812         instructions generating condition codes, mark existing mnenomics
 813         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 814         existing mnenomics as aliases.
 815
 816 2013-04-03  Nick Clifton  <nickc@redhat.com>
 817
 818         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 819         destination address by subtracting the operand from the current
 820         address.
 821         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 822         a positive value in the insn.
 823         (extract_u16_loop): Do not negate the returned value.
 824         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 825
 826         (ceilf.sw): Remove duplicate entry.
 827         (cvtf.hs): New entry.
 828         (cvtf.sh): Likewise.
 829         (fmaf.s): Likewise.
 830         (fmsf.s): Likewise.
 831         (fnmaf.s): Likewise.
 832         (fnmsf.s): Likewise.
 833         (maddf.s): Restrict to E3V5 architectures.
 834         (msubf.s): Likewise.
 835         (nmaddf.s): Likewise.
 836         (nmsubf.s): Likewise.
 837
 838 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 841         check address mode.
 842         (print_insn): Pass sizeflag to get_sib.
 843
 844 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 845
 846         PR binutils/15068
 847         * tic6x-dis.c: Add support for displaying 16-bit insns.
 848
 849 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 850
 851         PR gas/15095
 852         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 853         individual msb and lsb halves in src1 & src2 fields.  Discard the
 854         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 855         follow what Ti SDK does in that case as any value in the src1
 856         field yields the same output with SDK disassembler.
 857
 858 2013-03-12  Michael Eager <eager@eagercon.com>
 859
 860         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 861
 862 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 863
 864         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 865
 866 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 867
 868         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 869
 870 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 871
 872         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 873
 874 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 875
 876         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 877         (thumb32_opcodes): Likewise.
 878         (print_insn_thumb32): Handle 'S' control char.
 879
 880 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 881
 882         * lm32-desc.c: Regenerate.
 883
 884 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 885
 886         * i386-reg.tbl (riz): Add RegRex64.
 887         * i386-tbl.h: Regenerated.
 888
 889 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 890
 891         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 892         (aarch64_feature_crc): New static.
 893         (CRC): New macro.
 894         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 895         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 896         * aarch64-asm-2.c: Re-generate.
 897         * aarch64-dis-2.c: Ditto.
 898         * aarch64-opc-2.c: Ditto.
 899
 900 2013-02-27  Alan Modra  <amodra@gmail.com>
 901
 902         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 903         * rl78-decode.c: Regenerate.
 904
 905 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 906
 907         * rl78-decode.opc: Fix encoding of DIVWU insn.
 908         * rl78-decode.c: Regenerate.
 909
 910 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 911
 912         PR gas/15159
 913         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 914
 915         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 916         (cpu_flags): Add CpuSMAP.
 917
 918         * i386-opc.h (CpuSMAP): New.
 919         (i386_cpu_flags): Add cpusmap.
 920
 921         * i386-opc.tbl: Add clac and stac.
 922
 923         * i386-init.h: Regenerated.
 924         * i386-tbl.h: Likewise.
 925
 926 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 927
 928         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 929         which also makes the disassembler output be in little
 930         endian like it should be.
 931
 932 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 933
 934         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 935         fields to NULL.
 936         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 937
 938 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 939
 940         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 941         section disassembled.
 942
 943 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 944
 945         * arm-dis.c: Update strht pattern.
 946
 947 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 948
 949         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 950         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 951         trunc.w.s macro for EE.
 952
 953 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 954             Andrew Jenner <andrew@codesourcery.com>
 955
 956         Based on patches from Altera Corporation.
 957
 958         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 959         nios2-opc.c.
 960         * Makefile.in: Regenerated.
 961         * configure.in: Add case for bfd_nios2_arch.
 962         * configure: Regenerated.
 963         * disassemble.c (ARCH_nios2): Define.
 964         (disassembler): Add case for bfd_arch_nios2.
 965         * nios2-dis.c: New file.
 966         * nios2-opc.c: New file.
 967
 968 2013-02-04  Alan Modra  <amodra@gmail.com>
 969
 970         * po/POTFILES.in: Regenerate.
 971         * rl78-decode.c: Regenerate.
 972         * rx-decode.c: Regenerate.
 973
 974 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 975
 976         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 977         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 978         * aarch64-asm.c (convert_xtl_to_shll): New function.
 979         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 980         calling convert_xtl_to_shll.
 981         * aarch64-dis.c (convert_shll_to_xtl): New function.
 982         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 983         calling convert_shll_to_xtl.
 984         * aarch64-gen.c: Update copyright year.
 985         * aarch64-asm-2.c: Re-generate.
 986         * aarch64-dis-2.c: Re-generate.
 987         * aarch64-opc-2.c: Re-generate.
 988
 989 2013-01-24  Nick Clifton  <nickc@redhat.com>
 990
 991         * v850-dis.c: Add support for e3v5 architecture.
 992         * v850-opc.c: Likewise.
 993
 994 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 995
 996         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 997         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 998         * aarch64-opc.c (operand_general_constraint_met_p): For
 999         AARCH64_MOD_LSL, move the range check on the shift amount before the
1000         alignment check; change to call set_sft_amount_out_of_range_error
1001         instead of set_imm_out_of_range_error.
1002         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1003         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1004         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1005         SIMD_IMM_SFT.
1006
1007 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1008
1009         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1010
1011         * i386-init.h: Regenerated.
1012         * i386-tbl.h: Likewise.
1013
1014 2013-01-15  Nick Clifton  <nickc@redhat.com>
1015
1016         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1017         values.
1018         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1019
1020 2013-01-14  Will Newton <will.newton@imgtec.com>
1021
1022         * metag-dis.c (REG_WIDTH): Increase to 64.
1023
1024 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1025
1026         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1027         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1028         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1029         (SH6): Update.
1030         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1031         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1032         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1033         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1034
1035 2013-01-10  Will Newton <will.newton@imgtec.com>
1036
1037         * Makefile.am: Add Meta.
1038         * configure.in: Add Meta.
1039         * disassemble.c: Add Meta support.
1040         * metag-dis.c: New file.
1041         * Makefile.in: Regenerate.
1042         * configure: Regenerate.
1043
1044 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1045
1046         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1047         (match_opcode): Rename to cr16_match_opcode.
1048
1049 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1050
1051         * mips-dis.c: Add names for CP0 registers of r5900.
1052         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1053         instructions sq and lq.
1054         Add support for MIPS r5900 CPU.
1055         Add support for 128 bit MMI (Multimedia Instructions).
1056         Add support for EE instructions (Emotion Engine).
1057         Disable unsupported floating point instructions (64 bit and
1058         undefined compare operations).
1059         Enable instructions of MIPS ISA IV which are supported by r5900.
1060         Disable 64 bit co processor instructions.
1061         Disable 64 bit multiplication and division instructions.
1062         Disable instructions for co-processor 2 and 3, because these are
1063         not supported (preparation for later VU0 support (Vector Unit)).
1064         Disable cvt.w.s because this behaves like trunc.w.s and the
1065         correct execution can't be ensured on r5900.
1066         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1067         will confuse less developers and compilers.
1068
1069 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1070
1071         * aarch64-opc.c (aarch64_print_operand): Change to print
1072         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1073         in comment.
1074         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1075         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1076         OP_MOV_IMM_WIDE.
1077
1078 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1079
1080         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1081         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1082
1083 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         * i386-gen.c (process_copyright): Update copyright year to 2013.
1086
1087 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1088
1089         * cr16-dis.c (match_opcode,make_instruction): Remove static
1090         declaration.
1091         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1092         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1093
1094 For older changes see ChangeLog-2012
1095 \f
1096 Copyright (C) 2013 Free Software Foundation, Inc.
1097
1098 Copying and distribution of this file, with or without modification,
1099 are permitted in any medium without royalty provided the copyright
1100 notice and this notice are preserved.
1101
1102 Local Variables:
1103 mode: change-log
1104 left-margin: 8
1105 fill-column: 74
1106 version-control: never
1107 End: