opcodes/ChangeLog

   1 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
   4         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
   5         trunc.w.s macro for EE.
   6
   7 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
   8             Andrew Jenner <andrew@codesourcery.com>
   9
  10         Based on patches from Altera Corporation.
  11
  12         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
  13         nios2-opc.c.
  14         * Makefile.in: Regenerated.
  15         * configure.in: Add case for bfd_nios2_arch.
  16         * configure: Regenerated.
  17         * disassemble.c (ARCH_nios2): Define.
  18         (disassembler): Add case for bfd_arch_nios2.
  19         * nios2-dis.c: New file.
  20         * nios2-opc.c: New file.
  21
  22 2013-02-04  Alan Modra  <amodra@gmail.com>
  23
  24         * po/POTFILES.in: Regenerate.
  25         * rl78-decode.c: Regenerate.
  26         * rx-decode.c: Regenerate.
  27
  28 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
  29
  30         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
  31         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
  32         * aarch64-asm.c (convert_xtl_to_shll): New function.
  33         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  34         calling convert_xtl_to_shll.
  35         * aarch64-dis.c (convert_shll_to_xtl): New function.
  36         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  37         calling convert_shll_to_xtl.
  38         * aarch64-gen.c: Update copyright year.
  39         * aarch64-asm-2.c: Re-generate.
  40         * aarch64-dis-2.c: Re-generate.
  41         * aarch64-opc-2.c: Re-generate.
  42
  43 2013-01-24  Nick Clifton  <nickc@redhat.com>
  44
  45         * v850-dis.c: Add support for e3v5 architecture.
  46         * v850-opc.c: Likewise.
  47
  48 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  49
  50         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
  51         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
  52         * aarch64-opc.c (operand_general_constraint_met_p): For
  53         AARCH64_MOD_LSL, move the range check on the shift amount before the
  54         alignment check; change to call set_sft_amount_out_of_range_error
  55         instead of set_imm_out_of_range_error.
  56         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
  57         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
  58         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
  59         SIMD_IMM_SFT.
  60
  61 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
  62
  63         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
  64
  65         * i386-init.h: Regenerated.
  66         * i386-tbl.h: Likewise.
  67
  68 2013-01-15  Nick Clifton  <nickc@redhat.com>
  69
  70         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
  71         values.
  72         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
  73
  74 2013-01-14  Will Newton <will.newton@imgtec.com>
  75
  76         * metag-dis.c (REG_WIDTH): Increase to 64.
  77
  78 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  79
  80         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
  81         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
  82         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
  83         (SH6): Update.
  84         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
  85         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
  86         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
  87         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
  88
  89 2013-01-10  Will Newton <will.newton@imgtec.com>
  90
  91         * Makefile.am: Add Meta.
  92         * configure.in: Add Meta.
  93         * disassemble.c: Add Meta support.
  94         * metag-dis.c: New file.
  95         * Makefile.in: Regenerate.
  96         * configure: Regenerate.
  97
  98 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
  99
 100         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 101         (match_opcode): Rename to cr16_match_opcode.
 102
 103 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 104
 105         * mips-dis.c: Add names for CP0 registers of r5900.
 106         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 107         instructions sq and lq.
 108         Add support for MIPS r5900 CPU.
 109         Add support for 128 bit MMI (Multimedia Instructions).
 110         Add support for EE instructions (Emotion Engine).
 111         Disable unsupported floating point instructions (64 bit and
 112         undefined compare operations).
 113         Enable instructions of MIPS ISA IV which are supported by r5900.
 114         Disable 64 bit co processor instructions.
 115         Disable 64 bit multiplication and division instructions.
 116         Disable instructions for co-processor 2 and 3, because these are
 117         not supported (preparation for later VU0 support (Vector Unit)).
 118         Disable cvt.w.s because this behaves like trunc.w.s and the
 119         correct execution can't be ensured on r5900.
 120         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 121         will confuse less developers and compilers.
 122
 123 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 124
 125         * aarch64-opc.c (aarch64_print_operand): Change to print
 126         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 127         in comment.
 128         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 129         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 130         OP_MOV_IMM_WIDE.
 131
 132 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 133
 134         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 135         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 136
 137 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-gen.c (process_copyright): Update copyright year to 2013.
 140
 141 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 142
 143         * cr16-dis.c (match_opcode,make_instruction): Remove static
 144         declaration.
 145         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 146         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 147
 148 For older changes see ChangeLog-2012
 149 \f
 150 Copyright (C) 2013 Free Software Foundation, Inc.
 151
 152 Copying and distribution of this file, with or without modification,
 153 are permitted in any medium without royalty provided the copyright
 154 notice and this notice are preserved.
 155
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