1 2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (MOVBE_Fixup): New.
5 (PREFIX_0F3880): Likewise.
6 (PREFIX_0F3881): Likewise.
7 (PREFIX_0F38F0): Updated.
8 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
9 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
10 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
12 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
14 (cpu_flags): Add CpuMovbe and CpuEPT.
16 * i386-opc.h (CpuMovbe): New.
19 (i386_cpu_flags): Add cpumovbe and cpuept.
21 * i386-opc.tbl: Add entries for movbe and EPT instructions.
22 * i386-init.h: Regenerated.
23 * i386-tbl.h: Likewise.
25 2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
27 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
28 the two drem and the two dremu macros.
30 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
32 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
33 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
34 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
35 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
37 2008-04-25 David S. Miller <davem@davemloft.net>
39 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
40 instead of %sys_tick_cmpr, as suggested in architecture manuals.
42 2008-04-23 Paolo Bonzini <bonzini@gnu.org>
44 * aclocal.m4: Regenerate.
45 * configure: Regenerate.
47 2008-04-23 David S. Miller <davem@davemloft.net>
49 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
51 (prefetch_table): Add missing values.
53 2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
55 * i386-gen.c (opcode_modifiers): Add NoAVX.
57 * i386-opc.h (NoAVX): New.
59 (i386_opcode_modifier): Add noavx.
61 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
62 instructions which don't have AVX equivalent.
63 * i386-tbl.h: Regenerated.
65 2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
67 * i386-dis.c (OP_VEX_FMA): New.
68 (OP_EX_VexImmW): Likewise.
70 (Vex128FMA): Likewise.
71 (EXVexImmW): Likewise.
72 (get_vex_imm8): Likewise.
73 (OP_EX_VexReg): Likewise.
74 (vex_i4_done): Renamed to ...
76 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
77 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
79 (print_insn): Updated.
80 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
81 (OP_REG_VexI4): Check invalid high registers.
83 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
84 Michael Meissner <michael.meissner@amd.com>
86 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
87 * i386-tbl.h: Regenerate from i386-opc.tbl.
89 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
91 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
92 accept Power E500MC instructions.
93 (print_ppc_disassembler_options): Document -Me500mc.
94 * ppc-opc.c (DUIS, DUI, T): New.
95 (XRT, XRTRA): Likewise.
97 (powerpc_opcodes): Add new Power E500MC instructions.
99 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
101 * s390-dis.c (init_disasm): Evaluate disassembler_options.
102 (print_s390_disassembler_options): New function.
103 * disassemble.c (disassembler_usage): Invoke
104 print_s390_disassembler_options.
106 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
108 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
109 of local variables used for mnemonic parsing: prefix, suffix and
112 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
114 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
115 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
116 (s390_crb_extensions): New extensions table.
117 (insertExpandedMnemonic): Handle '$' tag.
118 * s390-opc.txt: Remove conditional jump variants which can now
119 be expanded automatically.
120 Replace '*' tag with '$' in the compare and branch instructions.
122 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
124 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
125 (PREFIX_VEX_3AXX): Likewis.
127 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
129 * i386-opc.tbl: Remove 4 extra blank lines.
131 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
134 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
135 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
136 * i386-opc.tbl: Likewise.
138 * i386-opc.h (CpuCLMUL): Renamed to ...
141 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
143 * i386-init.h: Regenerated.
145 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
147 * i386-dis.c (OP_E_register): New.
148 (OP_E_memory): Likewise.
150 (OP_EX_Vex): Likewise.
151 (OP_EX_VexW): Likewise.
152 (OP_XMM_Vex): Likewise.
153 (OP_XMM_VexW): Likewise.
154 (OP_REG_VexI4): Likewise.
155 (PCLMUL_Fixup): Likewise.
156 (VEXI4_Fixup): Likewise.
157 (VZERO_Fixup): Likewise.
158 (VCMP_Fixup): Likewise.
159 (VPERMIL2_Fixup): Likewise.
160 (rex_original): Likewise.
161 (rex_ignored): Likewise.
182 (VPERMIL2): Likewise.
183 (xmm_mode): Likewise.
184 (xmmq_mode): Likewise.
185 (ymmq_mode): Likewise.
186 (vex_mode): Likewise.
187 (vex128_mode): Likewise.
188 (vex256_mode): Likewise.
189 (USE_VEX_C4_TABLE): Likewise.
190 (USE_VEX_C5_TABLE): Likewise.
191 (USE_VEX_LEN_TABLE): Likewise.
192 (VEX_C4_TABLE): Likewise.
193 (VEX_C5_TABLE): Likewise.
194 (VEX_LEN_TABLE): Likewise.
195 (REG_VEX_XX): Likewise.
196 (MOD_VEX_XXX): Likewise.
197 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
198 (PREFIX_0F3A44): Likewise.
199 (PREFIX_0F3ADF): Likewise.
200 (PREFIX_VEX_XXX): Likewise.
202 (VEX_OF38): Likewise.
203 (VEX_OF3A): Likewise.
204 (VEX_LEN_XXX): Likewise.
206 (need_vex): Likewise.
207 (need_vex_reg): Likewise.
208 (vex_i4_done): Likewise.
209 (vex_table): Likewise.
210 (vex_len_table): Likewise.
211 (OP_REG_VexI4): Likewise.
212 (vex_cmp_op): Likewise.
213 (pclmul_op): Likewise.
214 (vpermil2_op): Likewise.
217 (PREFIX_0F38F0): Likewise.
218 (PREFIX_0F3A60): Likewise.
219 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
220 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
221 and PREFIX_VEX_XXX entries.
222 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
223 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
225 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
226 Add MOD_VEX_XXX entries.
227 (ckprefix): Initialize rex_original and rex_ignored. Store the
228 REX byte in rex_original.
229 (get_valid_dis386): Handle the implicit prefix in VEX prefix
230 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
231 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
232 calling get_valid_dis386. Use rex_original and rex_ignored when
234 (putop): Handle "XY".
235 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
237 (OP_E_extended): Updated to use OP_E_register and
239 (OP_XMM): Handle VEX.
241 (XMM_Fixup): Likewise.
242 (CMP_Fixup): Use ARRAY_SIZE.
244 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
245 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
246 (operand_type_init): Add OPERAND_TYPE_REGYMM and
247 OPERAND_TYPE_VEX_IMM4.
248 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
249 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
250 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
251 VexImmExt and SSE2AVX.
252 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
254 * i386-opc.h (CpuAVX): New.
256 (CpuCLMUL): Likewise.
267 (Vex3Sources): Likewise.
268 (VexImmExt): Likewise.
272 (Vex_Imm4): Likewise.
273 (Implicit1stXmm0): Likewise.
276 (ByteOkIntel): Likewise.
279 (Unspecified): Likewise.
281 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
282 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
283 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
284 vex3sources, veximmext and sse2avx.
285 (i386_operand_type): Add regymm, ymmword and vex_imm4.
287 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
289 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
291 * i386-init.h: Regenerated.
292 * i386-tbl.h: Likewise.
294 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
296 From Robin Getz <robin.getz@analog.com>
297 * bfin-dis.c (bu32): Typedef.
298 (enum const_forms_t): Add c_uimm32 and c_huimm32.
299 (constant_formats[]): Add uimm32 and huimm16.
304 (luimm16_val): Define.
305 (struct saved_state): Define.
306 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
307 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
308 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
310 (decode_LDIMMhalf_0): Print out the whole register value.
312 From Jie Zhang <jie.zhang@analog.com>
313 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
314 multiply and multiply-accumulate to data register instruction.
316 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
317 c_imm32, c_huimm32e): Define.
318 (constant_formats): Add flags for printing decimal, leading spaces, and
320 (comment, parallel): Add global flags in all disassembly.
321 (fmtconst): Take advantage of new flags, and print default in hex.
322 (fmtconst_val): Likewise.
323 (decode_macfunc): Be consistant with spaces, tabs, comments,
324 capitalization in disassembly, fix minor coding style issues.
325 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
326 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
327 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
328 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
329 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
330 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
331 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
332 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
333 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
334 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
335 _print_insn_bfin, print_insn_bfin): Likewise.
337 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
339 * aclocal.m4: Regenerate.
340 * configure: Likewise.
341 * Makefile.in: Likewise.
343 2008-03-13 Alan Modra <amodra@bigpond.net.au>
345 * Makefile.am: Run "make dep-am".
346 * Makefile.in: Regenerate.
347 * configure: Regenerate.
349 2008-03-07 Alan Modra <amodra@bigpond.net.au>
351 * ppc-opc.c (powerpc_opcodes): Order and format.
353 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
355 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
356 * i386-tbl.h: Regenerated.
358 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
360 * i386-opc.tbl: Disallow 16-bit near indirect branches for
362 * i386-tbl.h: Regenerated.
364 2008-02-21 Jan Beulich <jbeulich@novell.com>
366 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
367 and Fword for far indirect jmp. Allow Reg16 and Word for near
368 indirect jmp on x86-64. Disallow Fword for lcall.
369 * i386-tbl.h: Re-generate.
371 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
373 * cr16-opc.c (cr16_num_optab): Defined
375 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
377 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
378 * i386-init.h: Regenerated.
380 2008-02-14 Nick Clifton <nickc@redhat.com>
383 * configure.in (SHARED_LIBADD): Select the correct host specific
384 file extension for shared libraries.
385 * configure: Regenerate.
387 2008-02-13 Jan Beulich <jbeulich@novell.com>
389 * i386-opc.h (RegFlat): New.
390 * i386-reg.tbl (flat): Add.
391 * i386-tbl.h: Re-generate.
393 2008-02-13 Jan Beulich <jbeulich@novell.com>
395 * i386-dis.c (a_mode): New.
396 (cond_jump_mode): Adjust.
397 (Ma): Change to a_mode.
398 (intel_operand_size): Handle a_mode.
399 * i386-opc.tbl: Allow Dword and Qword for bound.
400 * i386-tbl.h: Re-generate.
402 2008-02-13 Jan Beulich <jbeulich@novell.com>
404 * i386-gen.c (process_i386_registers): Process new fields.
405 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
406 unsigned char. Add dw2_regnum and Dw2Inval.
407 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
409 * i386-tbl.h: Re-generate.
411 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
413 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
414 * i386-init.h: Updated.
416 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
418 * i386-gen.c (cpu_flags): Add CpuXsave.
420 * i386-opc.h (CpuXsave): New.
422 (i386_cpu_flags): Add cpuxsave.
424 * i386-dis.c (MOD_0FAE_REG_4): New.
425 (RM_0F01_REG_2): Likewise.
426 (MOD_0FAE_REG_5): Updated.
427 (RM_0F01_REG_3): Likewise.
428 (reg_table): Use MOD_0FAE_REG_4.
429 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
431 (rm_table): Add RM_0F01_REG_2.
433 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
434 * i386-init.h: Regenerated.
435 * i386-tbl.h: Likewise.
437 2008-02-11 Jan Beulich <jbeulich@novell.com>
439 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
440 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
441 * i386-tbl.h: Re-generate.
443 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
446 * configure: Regenerated.
448 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
450 * mips-dis.c: Update copyright.
451 (mips_arch_choices): Add Octeon.
452 * mips-opc.c: Update copyright.
454 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
456 2008-01-29 Alan Modra <amodra@bigpond.net.au>
458 * ppc-opc.c: Support optional L form mtmsr.
460 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
462 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
464 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
467 * i386-init.h: Regenerated.
469 2008-01-23 Tristan Gingold <gingold@adacore.com>
471 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
472 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
474 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
476 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
477 (cpu_flags): Likewise.
479 * i386-opc.h (CpuMMX2): Removed.
482 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
483 * i386-init.h: Regenerated.
484 * i386-tbl.h: Likewise.
486 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
488 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
490 * i386-init.h: Regenerated.
492 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
494 * i386-opc.tbl: Use Qword on movddup.
495 * i386-tbl.h: Regenerated.
497 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
499 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
500 * i386-tbl.h: Regenerated.
502 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
504 * i386-dis.c (Mx): New.
505 (PREFIX_0FC3): Likewise.
506 (PREFIX_0FC7_REG_6): Updated.
507 (dis386_twobyte): Use PREFIX_0FC3.
508 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
509 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
512 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
514 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
515 (operand_types): Add Mem.
517 * i386-opc.h (IntelSyntax): New.
518 * i386-opc.h (Mem): New.
520 (Opcode_Modifier_Max): Updated.
521 (i386_opcode_modifier): Add intelsyntax.
522 (i386_operand_type): Add mem.
524 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
527 * i386-reg.tbl: Add size for accumulator.
529 * i386-init.h: Regenerated.
530 * i386-tbl.h: Likewise.
532 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
534 * i386-opc.h (Byte): Fix a typo.
536 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-gen.c (operand_type_init): Add Dword to
540 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
541 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
543 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
544 Xmmword, Unspecified and Anysize.
545 (set_bitfield): Make Mmword an alias of Qword. Make Oword
548 * i386-opc.h (CheckSize): Removed.
556 (i386_opcode_modifier): Remove checksize, byte, word, dword,
560 (Unspecified): Likewise.
562 (i386_operand_type): Add byte, word, dword, fword, qword,
563 tbyte xmmword, unspecified and anysize.
565 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
566 Tbyte, Xmmword, Unspecified and Anysize.
568 * i386-reg.tbl: Add size for accumulator.
570 * i386-init.h: Regenerated.
571 * i386-tbl.h: Likewise.
573 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
575 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
577 (reg_table): Updated.
578 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
579 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
581 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
583 * i386-gen.c (set_bitfield): Use fail () on error.
585 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
587 * i386-gen.c (lineno): New.
588 (filename): Likewise.
589 (set_bitfield): Report filename and line numer on error.
590 (process_i386_opcodes): Set filename and update lineno.
591 (process_i386_registers): Likewise.
593 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
595 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
598 * i386-opc.h (IntelMnemonic): Renamed to ..
600 (Opcode_Modifier_Max): Updated.
601 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
604 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
605 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
606 * i386-tbl.h: Regenerated.
608 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
610 * i386-gen.c: Update copyright to 2008.
611 * i386-opc.h: Likewise.
612 * i386-opc.tbl: Likewise.
614 * i386-init.h: Regenerated.
615 * i386-tbl.h: Likewise.
617 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
619 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
620 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
621 * i386-tbl.h: Regenerated.
623 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
625 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
627 (cpu_flags): Likewise.
629 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
630 (CpuSSE4_2_Or_ABM): Likewise.
632 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
634 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
635 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
636 and CpuPadLock, respectively.
637 * i386-init.h: Regenerated.
638 * i386-tbl.h: Likewise.
640 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
642 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
644 * i386-opc.h (No_xSuf): Removed.
645 (CheckSize): Updated.
647 * i386-tbl.h: Regenerated.
649 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
651 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
652 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
654 (cpu_flags): Add CpuSSE4_2_Or_ABM.
656 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
658 (i386_cpu_flags): Add cpusse4_2_or_abm.
660 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
661 CpuABM|CpuSSE4_2 on popcnt.
662 * i386-init.h: Regenerated.
663 * i386-tbl.h: Likewise.
665 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
667 * i386-opc.h: Update comments.
669 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
671 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
672 * i386-opc.h: Likewise.
673 * i386-opc.tbl: Likewise.
675 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
678 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
679 Byte, Word, Dword, QWord and Xmmword.
681 * i386-opc.h (No_xSuf): New.
682 (CheckSize): Likewise.
689 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
690 Dword, QWord and Xmmword.
692 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
694 * i386-tbl.h: Regenerated.
696 2008-01-02 Mark Kettenis <kettenis@gnu.org>
698 * m88k-dis.c (instructions): Fix fcvt.* instructions.
701 For older changes see ChangeLog-2007
707 version-control: never