opcodes/ChangeLog

   1 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
   2             Richard Sandiford  <rdsandiford@googlemail.com>
   3
   4         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
   5         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
   6         (print_vu0_channel): New function.
   7         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
   8         (print_insn_args): Handle '#'.
   9         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
  10         * mips-opc.c (mips_vu0_channel_mask): New constant.
  11         (decode_mips_operand): Handle new VU0 operand types.
  12         (VU0, VU0CH): New macros.
  13         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
  14         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
  15         Use "+6" rather than "G" for QMFC2 and QMTC2.
  16
  17 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
  18
  19         * mips-formats.h (PCREL): Reorder parameters and update the definition
  20         to match new mips_pcrel_operand layout.
  21         (JUMP, JALX, BRANCH): Update accordingly.
  22         * mips16-opc.c (decode_mips16_operand): Likewise.
  23
  24 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  25
  26         * micromips-opc.c (WR_s): Delete.
  27
  28 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  29
  30         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
  31         New macros.
  32         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
  33         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
  34         (mips_builtin_opcodes): Use the new position-based read-write flags
  35         instead of field-based ones.  Use UDI for "udi..." instructions.
  36         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  37         New macros.
  38         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
  39         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
  40         (WR_SP, RD_16): New macros.
  41         (RD_SP): Redefine as an INSN2_* flag.
  42         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
  43         (mips16_opcodes): Use the new position-based read-write flags
  44         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
  45         pinfo2 field.
  46         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
  47         New macros.
  48         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
  49         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
  50         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
  51         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
  52         (micromips_opcodes): Use the new position-based read-write flags
  53         instead of field-based ones.
  54         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
  55         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
  56         of field-based flags.
  57
  58 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  59
  60         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
  61         (WR_SP): Replace with...
  62         (MOD_SP): ...this.
  63         (mips16_opcodes): Update accordingly.
  64         * mips-dis.c (print_insn_mips16): Likewise.
  65
  66 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  67
  68         * mips16-opc.c (mips16_opcodes): Reformat.
  69
  70 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  71
  72         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
  73         for operands that are hard-coded to $0.
  74         * micromips-opc.c (micromips_opcodes): Likewise.
  75
  76 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  77
  78         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
  79         for the single-operand forms of JALR and JALR.HB.
  80         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
  81         and JALRS.HB.
  82
  83 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  84
  85         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
  86         instructions.  Fix them to use WR_MACC instead of WR_CC and
  87         add missing RD_MACCs.
  88
  89 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
  90
  91         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
  92
  93 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
  94
  95         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
  96
  97 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
  98             Alexander Ivchenko  <alexander.ivchenko@intel.com>
  99             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 100             Sergey Lega  <sergey.s.lega@intel.com>
 101             Anna Tikhonova  <anna.tikhonova@intel.com>
 102             Ilya Tocar  <ilya.tocar@intel.com>
 103             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 104             Ilya Verbin  <ilya.verbin@intel.com>
 105             Kirill Yukhin  <kirill.yukhin@intel.com>
 106             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 107
 108         * i386-dis-evex.h: New.
 109         * i386-dis.c (OP_Rounding): New.
 110         (VPCMP_Fixup): New.
 111         (OP_Mask): New.
 112         (Rdq): New.
 113         (XMxmmq): New.
 114         (EXdScalarS): New.
 115         (EXymm): New.
 116         (EXEvexHalfBcstXmmq): New.
 117         (EXxmm_mdq): New.
 118         (EXEvexXGscat): New.
 119         (EXEvexXNoBcst): New.
 120         (VPCMP): New.
 121         (EXxEVexR): New.
 122         (EXxEVexS): New.
 123         (XMask): New.
 124         (MaskG): New.
 125         (MaskE): New.
 126         (MaskR): New.
 127         (MaskVex): New.
 128         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 129         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 130         evex_rounding_mode, evex_sae_mode, mask_mode.
 131         (USE_EVEX_TABLE): New.
 132         (EVEX_TABLE): New.
 133         (EVEX enum): New.
 134         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 135         REG_EVEX_0F38C7.
 136         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 137         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 138         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 139         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 140         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 141         MOD_EVEX_0F38C7_REG_6.
 142         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 143         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 144         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 145         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 146         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 147         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 148         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 149         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 150         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 151         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 152         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 153         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 154         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 155         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 156         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 157         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 158         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 159         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 160         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 161         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 162         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 163         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 164         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 165         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 166         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 167         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 168         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 169         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 170         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 171         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 172         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 173         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 174         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 175         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 176         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 177         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 178         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 179         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 180         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 181         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 182         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 183         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 184         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 185         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 186         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 187         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 188         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 189         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 190         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 191         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 192         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 193         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 194         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 195         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 196         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 197         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 198         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 199         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 200         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 201         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 202         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 203         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 204         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 205         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 206         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 207         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 208         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 209         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 210         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 211         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 212         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 213         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 214         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 215         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 216         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 217         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 218         PREFIX_EVEX_0F3A55.
 219         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 220         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 221         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 222         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 223         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 224         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 225         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 226         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 227         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 228         VEX_W_0F3A32_P_2_LEN_0.
 229         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 230         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 231         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 232         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 233         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 234         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 235         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 236         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 237         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 238         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 239         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 240         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 241         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 242         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 243         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 244         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 245         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 246         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 247         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 248         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 249         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 250         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 251         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 252         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 253         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 254         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 255         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 256         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 257         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 258         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 259         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 260         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 261         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 262         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 263         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 264         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 265         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 266         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 267         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 268         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 269         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 270         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 271         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 272         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 273         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 274         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 275         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 276         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 277         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 278         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 279         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 280         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 281         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 282         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 283         (struct vex): Add fields evex, r, v, mask_register_specifier,
 284         zeroing, ll, b.
 285         (intel_names_xmm): Add upper 16 registers.
 286         (att_names_xmm): Ditto.
 287         (intel_names_ymm): Ditto.
 288         (att_names_ymm): Ditto.
 289         (names_zmm): New.
 290         (intel_names_zmm): Ditto.
 291         (att_names_zmm): Ditto.
 292         (names_mask): Ditto.
 293         (intel_names_mask): Ditto.
 294         (att_names_mask): Ditto.
 295         (names_rounding): Ditto.
 296         (names_broadcast): Ditto.
 297         (x86_64_table): Add escape to evex-table.
 298         (reg_table): Include reg_table evex-entries from
 299         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 300         (prefix_table): Add entries for new instructions.
 301         (vex_table): Ditto.
 302         (vex_len_table): Ditto.
 303         (vex_w_table): Ditto.
 304         (mod_table): Ditto.
 305         (get_valid_dis386): Properly handle new instructions.
 306         (print_insn): Handle zmm and mask registers, print mask operand.
 307         (intel_operand_size): Support EVEX, new modes and sizes.
 308         (OP_E_register): Handle new modes.
 309         (OP_E_memory): Ditto.
 310         (OP_G): Ditto.
 311         (OP_XMM): Ditto.
 312         (OP_EX): Ditto.
 313         (OP_VEX): Ditto.
 314         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 315         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 316         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 317         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 318         CpuAVX512PF and CpuVREX.
 319         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 320         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 321         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 322         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 323         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 324         * i386-init.h: Regenerate.
 325         * i386-opc.h (CpuAVX512F): New.
 326         (CpuAVX512CD): New.
 327         (CpuAVX512ER): New.
 328         (CpuAVX512PF): New.
 329         (CpuVREX): New.
 330         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 331         cpuavx512pf and cpuvrex fields.
 332         (VecSIB): Add VecSIB512.
 333         (EVex): New.
 334         (Masking): New.
 335         (VecESize): New.
 336         (Broadcast): New.
 337         (StaticRounding): New.
 338         (SAE): New.
 339         (Disp8MemShift): New.
 340         (NoDefMask): New.
 341         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 342         staticrounding, sae, disp8memshift and nodefmask.
 343         (RegZMM): New.
 344         (Zmmword): Ditto.
 345         (Vec_Disp8): Ditto.
 346         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 347         fields.
 348         (RegVRex): New.
 349         * i386-opc.tbl: Add AVX512 instructions.
 350         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 351         registers, mask registers.
 352         * i386-tbl.h: Regenerate.
 353
 354 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 355
 356         PR gas/15220
 357         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 358         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 359
 360 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 361
 362         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 363         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 364         PREFIX_0F3ACC.
 365         (prefix_table): Updated.
 366         (three_byte_table): Likewise.
 367         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 368         (cpu_flags): Add CpuSHA.
 369         (i386_cpu_flags): Add cpusha.
 370         * i386-init.h: Regenerate.
 371         * i386-opc.h (CpuSHA): New.
 372         (CpuUnused): Restored.
 373         (i386_cpu_flags): Add cpusha.
 374         * i386-opc.tbl: Add SHA instructions.
 375         * i386-tbl.h: Regenerate.
 376
 377 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 378             Kirill Yukhin  <kirill.yukhin@intel.com>
 379             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 380
 381         * i386-dis.c (BND_Fixup): New.
 382         (Ebnd): New.
 383         (Ev_bnd): New.
 384         (Gbnd): New.
 385         (BND): New.
 386         (v_bnd_mode): New.
 387         (bnd_mode): New.
 388         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 389         MOD_0F1B_PREFIX_1.
 390         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 391         (dis tables): Replace XX with BND for near branch and call
 392         instructions.
 393         (prefix_table): Add new entries.
 394         (mod_table): Likewise.
 395         (names_bnd): New.
 396         (intel_names_bnd): New.
 397         (att_names_bnd): New.
 398         (BND_PREFIX): New.
 399         (prefix_name): Handle BND_PREFIX.
 400         (print_insn): Initialize names_bnd.
 401         (intel_operand_size): Handle new modes.
 402         (OP_E_register): Likewise.
 403         (OP_E_memory): Likewise.
 404         (OP_G): Likewise.
 405         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 406         (cpu_flags): Add CpuMPX.
 407         (operand_type_init): Add RegBND.
 408         (opcode_modifiers): Add BNDPrefixOk.
 409         (operand_types): Add RegBND.
 410         * i386-init.h: Regenerate.
 411         * i386-opc.h (CpuMPX): New.
 412         (CpuUnused): Comment out.
 413         (i386_cpu_flags): Add cpumpx.
 414         (BNDPrefixOk): New.
 415         (i386_opcode_modifier): Add bndprefixok.
 416         (RegBND): New.
 417         (i386_operand_type): Add regbnd.
 418         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 419         Add MPX instructions and bnd prefix.
 420         * i386-reg.tbl: Add bnd0-bnd3 registers.
 421         * i386-tbl.h: Regenerate.
 422
 423 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 424
 425         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 426         ATTRIBUTE_UNUSED.
 427
 428 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 429
 430         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 431         special rules.
 432         * Makefile.in: Regenerate.
 433         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 434         all fields.  Reformat.
 435
 436 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 437
 438         * mips16-opc.c: Include mips-formats.h.
 439         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 440         static arrays.
 441         (decode_mips16_operand): New function.
 442         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 443         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 444         Abort for OP_SAVE_RESTORE_LIST.
 445         (print_mips16_insn_arg): Change interface.  Use mips_operand
 446         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 447         (print_insn_mips16): ...here.  Call init_print_arg_state.
 448         Update the call to print_mips16_insn_arg.
 449
 450 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 451
 452         * mips-formats.h: New file.
 453         * mips-opc.c: Include mips-formats.h.
 454         (reg_0_map): New static array.
 455         (decode_mips_operand): New function.
 456         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 457         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 458         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 459         (int_c_map): New static arrays.
 460         (decode_micromips_operand): New function.
 461         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 462         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 463         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 464         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 465         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 466         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 467         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 468         (print_reg): New function.
 469         (mips_print_arg_state): New structure.
 470         (init_print_arg_state, print_insn_arg): New functions.
 471         (print_insn_args): Change interface and use mips_operand structures.
 472         Delete GET_OP_S.  Move GET_OP definition to...
 473         (print_insn_mips): ...here.  Update the call to print_insn_args.
 474         (print_insn_micromips): Use print_insn_args.
 475
 476 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 477
 478         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 479         in macros.
 480
 481 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 482
 483         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 484         ADDA.S, MULA.S and SUBA.S.
 485
 486 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         PR gas/13572
 489         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 490         * i386-tbl.h: Regenerated.
 491
 492 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 493
 494         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 495         and SD A(B) macros up.
 496         * micromips-opc.c (micromips_opcodes): Likewise.
 497
 498 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 499
 500         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 501         instructions.
 502
 503 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 504
 505         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 506         MDMX-like instructions.
 507         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 508         printing "Q" operands for INSN_5400 instructions.
 509
 510 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 511
 512         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 513         "+S" for "cins".
 514         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 515         Combine cases.
 516
 517 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 518
 519         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 520         "jalx".
 521         * mips16-opc.c (mips16_opcodes): Likewise.
 522         * micromips-opc.c (micromips_opcodes): Likewise.
 523         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 524         (print_insn_mips16): Handle "+i".
 525         (print_insn_micromips): Likewise.  Conditionally preserve the
 526         ISA bit for "a" but not for "+i".
 527
 528 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 529
 530         * micromips-opc.c (WR_mhi): Rename to..
 531         (WR_mh): ...this.
 532         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 533         "mh,mi" with "mh".
 534         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 535         (micromips_to_32_reg_h_map1): ...this.
 536         (micromips_to_32_reg_i_map): Rename to...
 537         (micromips_to_32_reg_h_map2): ...this.
 538         (print_micromips_insn): Remove "mi" case.  Print both registers
 539         in the pair for "mh".
 540
 541 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 542
 543         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 544         * micromips-opc.c (micromips_opcodes): Likewise.
 545         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 546         and "+T" handling.  Check for a "0" suffix when deciding whether to
 547         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 548
 549 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 550
 551         * s390-opc.c (J12_12, J24_24): New macros.
 552         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 553         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 554         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 555
 556 2013-07-04  Alan Modra  <amodra@gmail.com>
 557
 558         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 559
 560 2013-06-26  Nick Clifton  <nickc@redhat.com>
 561
 562         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 563         field when checking for type 2 nop.
 564         * rx-decode.c: Regenerate.
 565
 566 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 567
 568         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 569         and "movep" macros.
 570
 571 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 572
 573         * mips-dis.c (is_mips16_plt_tail): New function.
 574         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 575         word.
 576         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 577
 578 2013-06-21  DJ Delorie  <dj@redhat.com>
 579
 580         * msp430-decode.opc: New.
 581         * msp430-decode.c: New/generated.
 582         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 583         (MAINTAINER_CLEANFILES): Likewise.
 584         Add rule to build msp430-decode.c frommsp430decode.opc
 585         using the opc2c program.
 586         * Makefile.in: Regenerate.
 587         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 588         * configure: Regenerate.
 589
 590 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 591
 592         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 593         (SYMTAB_AVAILABLE): Removed.
 594         (#include "elf/aarch64.h): Ditto.
 595
 596 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 597             Maciej W. Rozycki  <macro@codesourcery.com>
 598             Chao-Ying Fu  <fu@mips.com>
 599
 600         * micromips-opc.c (EVA): Define.
 601         (TLBINV): Define.
 602         (micromips_opcodes): Add EVA opcodes.
 603         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 604         (print_insn_args): Handle EVA offsets.
 605         (print_insn_micromips): Likewise.
 606         * mips-opc.c (EVA): Define.
 607         (TLBINV): Define.
 608         (mips_builtin_opcodes): Add EVA opcodes.
 609
 610 2013-06-17  Alan Modra  <amodra@gmail.com>
 611
 612         * Makefile.am (mips-opc.lo): Add rules to create automatic
 613         dependency files.  Pass archdefs.
 614         (micromips-opc.lo, mips16-opc.lo): Likewise.
 615         * Makefile.in: Regenerate.
 616
 617 2013-06-14  DJ Delorie  <dj@redhat.com>
 618
 619         * rx-decode.opc (rx_decode_opcode): Bit operations on
 620         registers are 32-bit operations, not 8-bit operations.
 621         * rx-decode.c: Regenerate.
 622
 623 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 624
 625         * micromips-opc.c (IVIRT): New define.
 626         (IVIRT64): New define.
 627         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 628         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 629
 630         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 631         dmtgc0 to print cp0 names.
 632
 633 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 634
 635         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 636         argument.
 637
 638 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 639             Richard Sandiford  <rdsandiford@googlemail.com>
 640
 641         * micromips-opc.c (D32, D33, MC): Update definitions.
 642         (micromips_opcodes):  Initialize ase field.
 643         * mips-dis.c (mips_arch_choice): Add ase field.
 644         (mips_arch_choices): Initialize ase field.
 645         (set_default_mips_dis_options): Declare and setup mips_ase.
 646         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 647         MT32, MC): Update definitions.
 648         (mips_builtin_opcodes): Initialize ase field.
 649
 650 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 651
 652         * s390-opc.txt (flogr): Require a register pair destination.
 653
 654 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 655
 656         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 657         instruction format.
 658
 659 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 660
 661         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 662
 663 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 664
 665         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 666         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 667         XLS_MASK, PPCVSX2): New defines.
 668         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 669         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 670         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 671         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 672         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 673         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 674         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 675         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 676         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 677         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 678         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 679         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 680         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 681         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 682         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 683         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 684         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 685         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 686         <lxvx, stxvx>: New extended mnemonics.
 687
 688 2013-05-17  Alan Modra  <amodra@gmail.com>
 689
 690         * ia64-raw.tbl: Replace non-ASCII char.
 691         * ia64-waw.tbl: Likewise.
 692         * ia64-asmtab.c: Regenerate.
 693
 694 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 695
 696         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 697         * i386-init.h: Regenerated.
 698
 699 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 700
 701         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 702         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 703         check from [0, 255] to [-128, 255].
 704
 705 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 706
 707         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 708         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 709         (parse_mips_dis_option): Handle the virt option.
 710         (print_insn_args): Handle "+J".
 711         (print_mips_disassembler_options): Print out message about virt64.
 712         * mips-opc.c (IVIRT): New define.
 713         (IVIRT64): New define.
 714         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 715         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 716         Move rfe to the bottom as it conflicts with tlbgp.
 717
 718 2013-05-09  Alan Modra  <amodra@gmail.com>
 719
 720         * ppc-opc.c (extract_vlesi): Properly sign extend.
 721         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 722
 723 2013-05-02  Nick Clifton  <nickc@redhat.com>
 724
 725         * msp430-dis.c: Add support for MSP430X instructions.
 726
 727 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 728
 729         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 730         to "eccinj".
 731
 732 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 733
 734         PR binutils/15369
 735         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 736         of CGEN_CPU_ENDIAN.
 737         (hash_insns_list): Likewise.
 738
 739 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 740
 741         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 742         warning workaround.
 743
 744 2013-04-08  Jan Beulich <jbeulich@suse.com>
 745
 746         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 747         * i386-tbl.h: Re-generate.
 748
 749 2013-04-06  David S. Miller  <davem@davemloft.net>
 750
 751         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 752         of an opcode, prefer the one with F_PREFERRED set.
 753         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 754         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 755         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 756         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 757         instructions generating condition codes, mark existing mnenomics
 758         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 759         existing mnenomics as aliases.
 760
 761 2013-04-03  Nick Clifton  <nickc@redhat.com>
 762
 763         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 764         destination address by subtracting the operand from the current
 765         address.
 766         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 767         a positive value in the insn.
 768         (extract_u16_loop): Do not negate the returned value.
 769         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 770
 771         (ceilf.sw): Remove duplicate entry.
 772         (cvtf.hs): New entry.
 773         (cvtf.sh): Likewise.
 774         (fmaf.s): Likewise.
 775         (fmsf.s): Likewise.
 776         (fnmaf.s): Likewise.
 777         (fnmsf.s): Likewise.
 778         (maddf.s): Restrict to E3V5 architectures.
 779         (msubf.s): Likewise.
 780         (nmaddf.s): Likewise.
 781         (nmsubf.s): Likewise.
 782
 783 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 784
 785         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 786         check address mode.
 787         (print_insn): Pass sizeflag to get_sib.
 788
 789 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 790
 791         PR binutils/15068
 792         * tic6x-dis.c: Add support for displaying 16-bit insns.
 793
 794 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 795
 796         PR gas/15095
 797         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 798         individual msb and lsb halves in src1 & src2 fields.  Discard the
 799         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 800         follow what Ti SDK does in that case as any value in the src1
 801         field yields the same output with SDK disassembler.
 802
 803 2013-03-12  Michael Eager <eager@eagercon.com>
 804
 805         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 806
 807 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 808
 809         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 810
 811 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 812
 813         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 814
 815 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 816
 817         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 818
 819 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 820
 821         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 822         (thumb32_opcodes): Likewise.
 823         (print_insn_thumb32): Handle 'S' control char.
 824
 825 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 826
 827         * lm32-desc.c: Regenerate.
 828
 829 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 830
 831         * i386-reg.tbl (riz): Add RegRex64.
 832         * i386-tbl.h: Regenerated.
 833
 834 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 835
 836         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 837         (aarch64_feature_crc): New static.
 838         (CRC): New macro.
 839         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 840         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 841         * aarch64-asm-2.c: Re-generate.
 842         * aarch64-dis-2.c: Ditto.
 843         * aarch64-opc-2.c: Ditto.
 844
 845 2013-02-27  Alan Modra  <amodra@gmail.com>
 846
 847         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 848         * rl78-decode.c: Regenerate.
 849
 850 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 851
 852         * rl78-decode.opc: Fix encoding of DIVWU insn.
 853         * rl78-decode.c: Regenerate.
 854
 855 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 856
 857         PR gas/15159
 858         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 859
 860         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 861         (cpu_flags): Add CpuSMAP.
 862
 863         * i386-opc.h (CpuSMAP): New.
 864         (i386_cpu_flags): Add cpusmap.
 865
 866         * i386-opc.tbl: Add clac and stac.
 867
 868         * i386-init.h: Regenerated.
 869         * i386-tbl.h: Likewise.
 870
 871 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 872
 873         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 874         which also makes the disassembler output be in little
 875         endian like it should be.
 876
 877 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 878
 879         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 880         fields to NULL.
 881         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 882
 883 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 884
 885         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 886         section disassembled.
 887
 888 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 889
 890         * arm-dis.c: Update strht pattern.
 891
 892 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 893
 894         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 895         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 896         trunc.w.s macro for EE.
 897
 898 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 899             Andrew Jenner <andrew@codesourcery.com>
 900
 901         Based on patches from Altera Corporation.
 902
 903         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 904         nios2-opc.c.
 905         * Makefile.in: Regenerated.
 906         * configure.in: Add case for bfd_nios2_arch.
 907         * configure: Regenerated.
 908         * disassemble.c (ARCH_nios2): Define.
 909         (disassembler): Add case for bfd_arch_nios2.
 910         * nios2-dis.c: New file.
 911         * nios2-opc.c: New file.
 912
 913 2013-02-04  Alan Modra  <amodra@gmail.com>
 914
 915         * po/POTFILES.in: Regenerate.
 916         * rl78-decode.c: Regenerate.
 917         * rx-decode.c: Regenerate.
 918
 919 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 920
 921         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 922         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 923         * aarch64-asm.c (convert_xtl_to_shll): New function.
 924         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 925         calling convert_xtl_to_shll.
 926         * aarch64-dis.c (convert_shll_to_xtl): New function.
 927         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 928         calling convert_shll_to_xtl.
 929         * aarch64-gen.c: Update copyright year.
 930         * aarch64-asm-2.c: Re-generate.
 931         * aarch64-dis-2.c: Re-generate.
 932         * aarch64-opc-2.c: Re-generate.
 933
 934 2013-01-24  Nick Clifton  <nickc@redhat.com>
 935
 936         * v850-dis.c: Add support for e3v5 architecture.
 937         * v850-opc.c: Likewise.
 938
 939 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 940
 941         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 942         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 943         * aarch64-opc.c (operand_general_constraint_met_p): For
 944         AARCH64_MOD_LSL, move the range check on the shift amount before the
 945         alignment check; change to call set_sft_amount_out_of_range_error
 946         instead of set_imm_out_of_range_error.
 947         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 948         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 949         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 950         SIMD_IMM_SFT.
 951
 952 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 953
 954         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 955
 956         * i386-init.h: Regenerated.
 957         * i386-tbl.h: Likewise.
 958
 959 2013-01-15  Nick Clifton  <nickc@redhat.com>
 960
 961         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 962         values.
 963         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 964
 965 2013-01-14  Will Newton <will.newton@imgtec.com>
 966
 967         * metag-dis.c (REG_WIDTH): Increase to 64.
 968
 969 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 970
 971         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 972         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 973         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 974         (SH6): Update.
 975         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 976         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 977         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 978         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 979
 980 2013-01-10  Will Newton <will.newton@imgtec.com>
 981
 982         * Makefile.am: Add Meta.
 983         * configure.in: Add Meta.
 984         * disassemble.c: Add Meta support.
 985         * metag-dis.c: New file.
 986         * Makefile.in: Regenerate.
 987         * configure: Regenerate.
 988
 989 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 990
 991         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 992         (match_opcode): Rename to cr16_match_opcode.
 993
 994 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 995
 996         * mips-dis.c: Add names for CP0 registers of r5900.
 997         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 998         instructions sq and lq.
 999         Add support for MIPS r5900 CPU.
1000         Add support for 128 bit MMI (Multimedia Instructions).
1001         Add support for EE instructions (Emotion Engine).
1002         Disable unsupported floating point instructions (64 bit and
1003         undefined compare operations).
1004         Enable instructions of MIPS ISA IV which are supported by r5900.
1005         Disable 64 bit co processor instructions.
1006         Disable 64 bit multiplication and division instructions.
1007         Disable instructions for co-processor 2 and 3, because these are
1008         not supported (preparation for later VU0 support (Vector Unit)).
1009         Disable cvt.w.s because this behaves like trunc.w.s and the
1010         correct execution can't be ensured on r5900.
1011         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1012         will confuse less developers and compilers.
1013
1014 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1015
1016         * aarch64-opc.c (aarch64_print_operand): Change to print
1017         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1018         in comment.
1019         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1020         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1021         OP_MOV_IMM_WIDE.
1022
1023 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1024
1025         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1026         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1027
1028 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1029
1030         * i386-gen.c (process_copyright): Update copyright year to 2013.
1031
1032 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1033
1034         * cr16-dis.c (match_opcode,make_instruction): Remove static
1035         declaration.
1036         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1037         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1038
1039 For older changes see ChangeLog-2012
1040 \f
1041 Copyright (C) 2013 Free Software Foundation, Inc.
1042
1043 Copying and distribution of this file, with or without modification,
1044 are permitted in any medium without royalty provided the copyright
1045 notice and this notice are preserved.
1046
1047 Local Variables:
1048 mode: change-log
1049 left-margin: 8
1050 fill-column: 74
1051 version-control: never
1052 End: