1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
4 store templates, adding D.
5 * i386-tbl.h: Re-generate.
7 2018-09-13 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
10 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
11 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
12 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
13 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
14 Fold load and store templates where possible, adding D. Drop
15 IgnoreSize where it was pointlessly present. Drop redundant
17 * i386-tbl.h: Re-generate.
19 2018-09-13 Jan Beulich <jbeulich@suse.com>
21 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
22 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
23 (intel_operand_size): Handle v_bndmk_mode.
24 (OP_E_memory): Likewise. Produce (bad) when also riprel.
26 2018-09-08 John Darrington <john@darrington.wattle.id.au>
28 * disassemble.c (ARCH_s12z): Define if ARCH_all.
30 2018-08-31 Kito Cheng <kito@andestech.com>
32 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
33 compressed floating point instructions.
35 2018-08-30 Kito Cheng <kito@andestech.com>
37 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
38 riscv_opcode.xlen_requirement.
39 * riscv-opc.c (riscv_opcodes): Update for struct change.
41 2018-08-29 Martin Aberg <maberg@gaisler.com>
43 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
44 psr (PWRPSR) instruction.
46 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
48 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
50 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
52 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
54 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
56 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
57 loongson3a as an alias of gs464 for compatibility.
58 * mips-opc.c (mips_opcodes): Change Comments.
60 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
62 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
64 (print_mips_disassembler_options): Document -M loongson-ext.
65 * mips-opc.c (LEXT2): New macro.
66 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
68 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
70 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
72 (parse_mips_ase_option): Handle -M loongson-ext option.
73 (print_mips_disassembler_options): Document -M loongson-ext.
74 * mips-opc.c (IL3A): Delete.
75 * mips-opc.c (LEXT): New macro.
76 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
79 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
81 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
83 (parse_mips_ase_option): Handle -M loongson-cam option.
84 (print_mips_disassembler_options): Document -M loongson-cam.
85 * mips-opc.c (LCAM): New macro.
86 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
89 2018-08-21 Alan Modra <amodra@gmail.com>
91 * ppc-dis.c (operand_value_powerpc): Init "invalid".
92 (skip_optional_operands): Count optional operands, and update
93 ppc_optional_operand_value call.
94 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
95 (extract_vlensi): Likewise.
96 (extract_fxm): Return default value for missing optional operand.
97 (extract_ls, extract_raq, extract_tbr): Likewise.
98 (insert_sxl, extract_sxl): New functions.
99 (insert_esync, extract_esync): Remove Power9 handling and simplify.
100 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
101 flag and extra entry.
102 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
105 2018-08-20 Alan Modra <amodra@gmail.com>
107 * sh-opc.h (MASK): Simplify.
109 2018-08-18 John Darrington <john@darrington.wattle.id.au>
111 * s12z-dis.c (bm_decode): Deal with cases where the mode is
112 BM_RESERVED0 or BM_RESERVED1
113 (bm_rel_decode, bm_n_bytes): Ditto.
115 2018-08-18 John Darrington <john@darrington.wattle.id.au>
119 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
121 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
122 address with the addr32 prefix and without base nor index
125 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
128 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
129 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
130 (cpu_flags): Add CpuCMOV and CpuFXSR.
131 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
132 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
133 * i386-init.h: Regenerated.
134 * i386-tbl.h: Likewise.
136 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
138 * arc-regs.h: Update auxiliary registers.
140 2018-08-06 Jan Beulich <jbeulich@suse.com>
142 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
143 (RegIP, RegIZ): Define.
144 * i386-reg.tbl: Adjust comments.
145 (rip): Use Qword instead of BaseIndex. Use RegIP.
146 (eip): Use Dword instead of BaseIndex. Use RegIP.
147 (riz): Add Qword. Use RegIZ.
148 (eiz): Add Dword. Use RegIZ.
149 * i386-tbl.h: Re-generate.
151 2018-08-03 Jan Beulich <jbeulich@suse.com>
153 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
154 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
155 vpmovzxdq, vpmovzxwd): Remove NoRex64.
156 * i386-tbl.h: Re-generate.
158 2018-08-03 Jan Beulich <jbeulich@suse.com>
160 * i386-gen.c (operand_types): Remove Mem field.
161 * i386-opc.h (union i386_operand_type): Remove mem field.
162 * i386-init.h, i386-tbl.h: Re-generate.
164 2018-08-01 Alan Modra <amodra@gmail.com>
166 * po/POTFILES.in: Regenerate.
168 2018-07-31 Nick Clifton <nickc@redhat.com>
170 * po/sv.po: Updated Swedish translation.
172 2018-07-31 Jan Beulich <jbeulich@suse.com>
174 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
175 * i386-init.h, i386-tbl.h: Re-generate.
177 2018-07-31 Jan Beulich <jbeulich@suse.com>
179 * i386-opc.h (ZEROING_MASKING) Rename to ...
180 (DYNAMIC_MASKING): ... this. Adjust comment.
181 * i386-opc.tbl (MaskingMorZ): Define.
182 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
183 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
184 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
185 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
186 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
187 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
188 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
189 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
190 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
192 2018-07-31 Jan Beulich <jbeulich@suse.com>
194 * i386-opc.tbl: Use element rather than vector size for AVX512*
195 scatter/gather insns.
196 * i386-tbl.h: Re-generate.
198 2018-07-31 Jan Beulich <jbeulich@suse.com>
200 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
201 (cpu_flags): Drop CpuVREX.
202 * i386-opc.h (CpuVREX): Delete.
203 (union i386_cpu_flags): Remove cpuvrex.
204 * i386-init.h, i386-tbl.h: Re-generate.
206 2018-07-30 Jim Wilson <jimw@sifive.com>
208 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
210 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
212 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
214 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
215 * Makefile.in: Regenerated.
216 * configure.ac: Add C-SKY.
217 * configure: Regenerated.
218 * csky-dis.c: New file.
219 * csky-opc.h: New file.
220 * disassemble.c (ARCH_csky): Define.
221 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
222 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
224 2018-07-27 Alan Modra <amodra@gmail.com>
226 * ppc-opc.c (insert_sprbat): Correct function parameter and
228 (extract_sprbat): Likewise, variable too.
230 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
231 Alan Modra <amodra@gmail.com>
233 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
234 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
235 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
236 support disjointed BAT.
237 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
238 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
239 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
241 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
242 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
244 * i386-gen.c (adjust_broadcast_modifier): New function.
245 (process_i386_opcode_modifier): Add an argument for operands.
246 Adjust the Broadcast value based on operands.
247 (output_i386_opcode): Pass operand_types to
248 process_i386_opcode_modifier.
249 (process_i386_opcodes): Pass NULL as operands to
250 process_i386_opcode_modifier.
251 * i386-opc.h (BYTE_BROADCAST): New.
252 (WORD_BROADCAST): Likewise.
253 (DWORD_BROADCAST): Likewise.
254 (QWORD_BROADCAST): Likewise.
255 (i386_opcode_modifier): Expand broadcast to 3 bits.
256 * i386-tbl.h: Regenerated.
258 2018-07-24 Alan Modra <amodra@gmail.com>
261 * or1k-desc.h: Regenerate.
263 2018-07-24 Jan Beulich <jbeulich@suse.com>
265 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
266 vcvtusi2ss, and vcvtusi2sd.
267 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
268 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
269 * i386-tbl.h: Re-generate.
271 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
273 * arc-opc.c (extract_w6): Fix extending the sign.
275 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
277 * arc-tbl.h (vewt): Allow it for ARC EM family.
279 2018-07-23 Alan Modra <amodra@gmail.com>
282 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
283 opcode variants for mtspr/mfspr encodings.
285 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
286 Maciej W. Rozycki <macro@mips.com>
288 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
289 loongson3a descriptors.
290 (parse_mips_ase_option): Handle -M loongson-mmi option.
291 (print_mips_disassembler_options): Document -M loongson-mmi.
292 * mips-opc.c (LMMI): New macro.
293 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
296 2018-07-19 Jan Beulich <jbeulich@suse.com>
298 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
299 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
300 IgnoreSize and [XYZ]MMword where applicable.
301 * i386-tbl.h: Re-generate.
303 2018-07-19 Jan Beulich <jbeulich@suse.com>
305 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
306 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
307 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
308 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
309 * i386-tbl.h: Re-generate.
311 2018-07-19 Jan Beulich <jbeulich@suse.com>
313 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
314 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
315 VPCLMULQDQ templates into their respective AVX512VL counterparts
316 where possible, using Disp8ShiftVL and CheckRegSize instead of
317 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
318 * i386-tbl.h: Re-generate.
320 2018-07-19 Jan Beulich <jbeulich@suse.com>
322 * i386-opc.tbl: Fold AVX512DQ templates into their respective
323 AVX512VL counterparts where possible, using Disp8ShiftVL and
324 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
325 IgnoreSize) as appropriate.
326 * i386-tbl.h: Re-generate.
328 2018-07-19 Jan Beulich <jbeulich@suse.com>
330 * i386-opc.tbl: Fold AVX512BW templates into their respective
331 AVX512VL counterparts where possible, using Disp8ShiftVL and
332 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
333 IgnoreSize) as appropriate.
334 * i386-tbl.h: Re-generate.
336 2018-07-19 Jan Beulich <jbeulich@suse.com>
338 * i386-opc.tbl: Fold AVX512CD templates into their respective
339 AVX512VL counterparts where possible, using Disp8ShiftVL and
340 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
341 IgnoreSize) as appropriate.
342 * i386-tbl.h: Re-generate.
344 2018-07-19 Jan Beulich <jbeulich@suse.com>
346 * i386-opc.h (DISP8_SHIFT_VL): New.
347 * i386-opc.tbl (Disp8ShiftVL): Define.
348 (various): Fold AVX512VL templates into their respective
349 AVX512F counterparts where possible, using Disp8ShiftVL and
350 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
351 IgnoreSize) as appropriate.
352 * i386-tbl.h: Re-generate.
354 2018-07-19 Jan Beulich <jbeulich@suse.com>
356 * Makefile.am: Change dependencies and rule for
357 $(srcdir)/i386-init.h.
358 * Makefile.in: Re-generate.
359 * i386-gen.c (process_i386_opcodes): New local variable
360 "marker". Drop opening of input file. Recognize marker and line
362 * i386-opc.tbl (OPCODE_I386_H): Define.
363 (i386-opc.h): Include it.
366 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
369 * i386-opc.h (Byte): Update comments.
378 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
380 * i386-tbl.h: Regenerated.
382 2018-07-12 Sudakshina Das <sudi.das@arm.com>
384 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
385 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
386 * aarch64-asm-2.c: Regenerate.
387 * aarch64-dis-2.c: Regenerate.
388 * aarch64-opc-2.c: Regenerate.
390 2018-07-12 Tamar Christina <tamar.christina@arm.com>
393 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
394 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
395 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
396 sqdmulh, sqrdmulh): Use Em16.
398 2018-07-11 Sudakshina Das <sudi.das@arm.com>
400 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
401 csdb together with them.
402 (thumb32_opcodes): Likewise.
404 2018-07-11 Jan Beulich <jbeulich@suse.com>
406 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
407 requiring 32-bit registers as operands 2 and 3. Improve
409 (mwait, mwaitx): Fold templates. Improve comments.
410 OPERAND_TYPE_INOUTPORTREG.
411 * i386-tbl.h: Re-generate.
413 2018-07-11 Jan Beulich <jbeulich@suse.com>
415 * i386-gen.c (operand_type_init): Remove
416 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
417 OPERAND_TYPE_INOUTPORTREG.
418 * i386-init.h: Re-generate.
420 2018-07-11 Jan Beulich <jbeulich@suse.com>
422 * i386-opc.tbl (wrssd, wrussd): Add Dword.
423 (wrssq, wrussq): Add Qword.
424 * i386-tbl.h: Re-generate.
426 2018-07-11 Jan Beulich <jbeulich@suse.com>
428 * i386-opc.h: Rename OTMax to OTNum.
429 (OTNumOfUints): Adjust calculation.
430 (OTUnused): Directly alias to OTNum.
432 2018-07-09 Maciej W. Rozycki <macro@mips.com>
434 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
436 (lea_reg_xys): Likewise.
437 (print_insn_loop_primitive): Rename `reg' local variable to
440 2018-07-06 Tamar Christina <tamar.christina@arm.com>
443 * aarch64-tbl.h (ldarh): Fix disassembly mask.
445 2018-07-06 Tamar Christina <tamar.christina@arm.com>
448 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
449 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
451 2018-07-02 Maciej W. Rozycki <macro@mips.com>
454 * mips-dis.c (mips_option_arg_t): New enumeration.
455 (mips_options): New variable.
456 (disassembler_options_mips): New function.
457 (print_mips_disassembler_options): Reimplement in terms of
458 `disassembler_options_mips'.
459 * arm-dis.c (disassembler_options_arm): Adapt to using the
460 `disasm_options_and_args_t' structure.
461 * ppc-dis.c (disassembler_options_powerpc): Likewise.
462 * s390-dis.c (disassembler_options_s390): Likewise.
464 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
466 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
468 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
469 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
470 * testsuite/ld-arm/tls-longplt.d: Likewise.
472 2018-06-29 Tamar Christina <tamar.christina@arm.com>
475 * aarch64-asm-2.c: Regenerate.
476 * aarch64-dis-2.c: Likewise.
477 * aarch64-opc-2.c: Likewise.
478 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
479 * aarch64-opc.c (operand_general_constraint_met_p,
480 aarch64_print_operand): Likewise.
481 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
482 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
484 (AARCH64_OPERANDS): Add Em2.
486 2018-06-26 Nick Clifton <nickc@redhat.com>
488 * po/uk.po: Updated Ukranian translation.
489 * po/de.po: Updated German translation.
490 * po/pt_BR.po: Updated Brazilian Portuguese translation.
492 2018-06-26 Nick Clifton <nickc@redhat.com>
494 * nfp-dis.c: Fix spelling mistake.
496 2018-06-24 Nick Clifton <nickc@redhat.com>
498 * configure: Regenerate.
499 * po/opcodes.pot: Regenerate.
501 2018-06-24 Nick Clifton <nickc@redhat.com>
505 2018-06-19 Tamar Christina <tamar.christina@arm.com>
507 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
508 * aarch64-asm-2.c: Regenerate.
509 * aarch64-dis-2.c: Likewise.
511 2018-06-21 Maciej W. Rozycki <macro@mips.com>
513 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
514 `-M ginv' option description.
516 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
519 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
522 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
524 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
525 * configure.ac: Remove AC_PREREQ.
526 * Makefile.in: Re-generate.
527 * aclocal.m4: Re-generate.
528 * configure: Re-generate.
530 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
532 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
533 mips64r6 descriptors.
534 (parse_mips_ase_option): Handle -Mginv option.
535 (print_mips_disassembler_options): Document -Mginv.
536 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
538 (mips_opcodes): Define ginvi and ginvt.
540 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
541 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
543 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
544 * mips-opc.c (CRC, CRC64): New macros.
545 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
546 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
549 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
552 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
553 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
555 2018-06-06 Alan Modra <amodra@gmail.com>
557 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
558 setjmp. Move init for some other vars later too.
560 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
562 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
563 (dis_private): Add new fields for property section tracking.
564 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
565 (xtensa_instruction_fits): New functions.
566 (fetch_data): Bump minimal fetch size to 4.
567 (print_insn_xtensa): Make struct dis_private static.
568 Load and prepare property table on section change.
569 Don't disassemble literals. Don't disassemble instructions that
570 cross property table boundaries.
572 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
574 * configure: Regenerated.
576 2018-06-01 Jan Beulich <jbeulich@suse.com>
578 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
579 * i386-tbl.h: Re-generate.
581 2018-06-01 Jan Beulich <jbeulich@suse.com>
583 * i386-opc.tbl (sldt, str): Add NoRex64.
584 * i386-tbl.h: Re-generate.
586 2018-06-01 Jan Beulich <jbeulich@suse.com>
588 * i386-opc.tbl (invpcid): Add Oword.
589 * i386-tbl.h: Re-generate.
591 2018-06-01 Alan Modra <amodra@gmail.com>
593 * sysdep.h (_bfd_error_handler): Don't declare.
594 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
595 * rl78-decode.opc: Likewise.
596 * msp430-decode.c: Regenerate.
597 * rl78-decode.c: Regenerate.
599 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
601 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
602 * i386-init.h : Regenerated.
604 2018-05-25 Alan Modra <amodra@gmail.com>
606 * Makefile.in: Regenerate.
607 * po/POTFILES.in: Regenerate.
609 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
611 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
612 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
613 (insert_bab, extract_bab, insert_btab, extract_btab,
614 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
615 (BAT, BBA VBA RBS XB6S): Delete macros.
616 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
617 (BB, BD, RBX, XC6): Update for new macros.
618 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
619 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
620 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
621 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
623 2018-05-18 John Darrington <john@darrington.wattle.id.au>
625 * Makefile.am: Add support for s12z architecture.
626 * configure.ac: Likewise.
627 * disassemble.c: Likewise.
628 * disassemble.h: Likewise.
629 * Makefile.in: Regenerate.
630 * configure: Regenerate.
631 * s12z-dis.c: New file.
634 2018-05-18 Alan Modra <amodra@gmail.com>
636 * nfp-dis.c: Don't #include libbfd.h.
637 (init_nfp3200_priv): Use bfd_get_section_contents.
638 (nit_nfp6000_mecsr_sec): Likewise.
640 2018-05-17 Nick Clifton <nickc@redhat.com>
642 * po/zh_CN.po: Updated simplified Chinese translation.
644 2018-05-16 Tamar Christina <tamar.christina@arm.com>
647 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
648 * aarch64-dis-2.c: Regenerate.
650 2018-05-15 Tamar Christina <tamar.christina@arm.com>
653 * aarch64-asm.c (opintl.h): Include.
654 (aarch64_ins_sysreg): Enforce read/write constraints.
655 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
656 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
657 (F_REG_READ, F_REG_WRITE): New.
658 * aarch64-opc.c (aarch64_print_operand): Generate notes for
660 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
661 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
662 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
663 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
664 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
665 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
666 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
667 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
668 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
669 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
670 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
671 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
672 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
673 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
674 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
675 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
676 msr (F_SYS_WRITE), mrs (F_SYS_READ).
678 2018-05-15 Tamar Christina <tamar.christina@arm.com>
681 * aarch64-dis.c (no_notes: New.
682 (parse_aarch64_dis_option): Support notes.
683 (aarch64_decode_insn, print_operands): Likewise.
684 (print_aarch64_disassembler_options): Document notes.
685 * aarch64-opc.c (aarch64_print_operand): Support notes.
687 2018-05-15 Tamar Christina <tamar.christina@arm.com>
690 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
691 and take error struct.
692 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
693 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
694 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
695 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
696 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
697 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
698 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
699 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
700 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
701 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
702 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
703 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
704 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
705 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
706 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
707 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
708 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
709 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
710 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
711 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
712 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
713 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
714 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
715 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
716 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
717 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
718 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
719 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
720 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
721 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
722 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
723 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
724 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
725 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
726 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
727 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
728 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
729 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
730 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
731 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
732 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
733 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
734 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
735 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
736 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
737 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
738 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
739 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
740 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
741 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
742 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
743 (determine_disassembling_preference, aarch64_decode_insn,
744 print_insn_aarch64_word, print_insn_data): Take errors struct.
745 (print_insn_aarch64): Use errors.
746 * aarch64-asm-2.c: Regenerate.
747 * aarch64-dis-2.c: Regenerate.
748 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
749 boolean in aarch64_insert_operan.
750 (print_operand_extractor): Likewise.
751 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
753 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
755 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
757 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
759 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
761 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
763 * cr16-opc.c (cr16_instruction): Comment typo fix.
764 * hppa-dis.c (print_insn_hppa): Likewise.
766 2018-05-08 Jim Wilson <jimw@sifive.com>
768 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
769 (match_c_slli64, match_srxi_as_c_srxi): New.
770 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
771 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
772 <c.slli, c.srli, c.srai>: Use match_s_slli.
773 <c.slli64, c.srli64, c.srai64>: New.
775 2018-05-08 Alan Modra <amodra@gmail.com>
777 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
778 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
779 partition opcode space for index lookup.
781 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
783 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
784 <insn_length>: ...with this. Update usage.
785 Remove duplicate call to *info->memory_error_func.
787 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
788 H.J. Lu <hongjiu.lu@intel.com>
790 * i386-dis.c (Gva): New.
791 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
792 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
793 (prefix_table): New instructions (see prefix above).
794 (mod_table): New instructions (see prefix above).
795 (OP_G): Handle va_mode.
796 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
798 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
799 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
800 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
801 * i386-opc.tbl: Add movidir{i,64b}.
802 * i386-init.h: Regenerated.
803 * i386-tbl.h: Likewise.
805 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
807 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
809 * i386-opc.h (AddrPrefixOp0): Renamed to ...
810 (AddrPrefixOpReg): This.
811 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
812 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
814 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
816 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
817 (vle_num_opcodes): Likewise.
818 (spe2_num_opcodes): Likewise.
819 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
821 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
822 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
825 2018-05-01 Tamar Christina <tamar.christina@arm.com>
827 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
829 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
831 Makefile.am: Added nfp-dis.c.
832 configure.ac: Added bfd_nfp_arch.
833 disassemble.h: Added print_insn_nfp prototype.
834 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
835 nfp-dis.c: New, for NFP support.
836 po/POTFILES.in: Added nfp-dis.c to the list.
837 Makefile.in: Regenerate.
838 configure: Regenerate.
840 2018-04-26 Jan Beulich <jbeulich@suse.com>
842 * i386-opc.tbl: Fold various non-memory operand AVX512VL
843 templates into their base ones.
844 * i386-tlb.h: Re-generate.
846 2018-04-26 Jan Beulich <jbeulich@suse.com>
848 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
849 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
850 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
851 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
852 * i386-init.h: Re-generate.
854 2018-04-26 Jan Beulich <jbeulich@suse.com>
856 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
857 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
858 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
859 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
861 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
863 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
865 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
866 cpuregzmm, and cpuregmask.
867 * i386-init.h: Re-generate.
868 * i386-tbl.h: Re-generate.
870 2018-04-26 Jan Beulich <jbeulich@suse.com>
872 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
873 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
874 * i386-init.h: Re-generate.
876 2018-04-26 Jan Beulich <jbeulich@suse.com>
878 * i386-gen.c (VexImmExt): Delete.
879 * i386-opc.h (VexImmExt, veximmext): Delete.
880 * i386-opc.tbl: Drop all VexImmExt uses.
881 * i386-tlb.h: Re-generate.
883 2018-04-25 Jan Beulich <jbeulich@suse.com>
885 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
887 * i386-tlb.h: Re-generate.
889 2018-04-25 Tamar Christina <tamar.christina@arm.com>
891 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
893 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
895 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
897 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
898 (cpu_flags): Add CpuCLDEMOTE.
899 * i386-init.h: Regenerate.
900 * i386-opc.h (enum): Add CpuCLDEMOTE,
901 (i386_cpu_flags): Add cpucldemote.
902 * i386-opc.tbl: Add cldemote.
903 * i386-tbl.h: Regenerate.
905 2018-04-16 Alan Modra <amodra@gmail.com>
907 * Makefile.am: Remove sh5 and sh64 support.
908 * configure.ac: Likewise.
909 * disassemble.c: Likewise.
910 * disassemble.h: Likewise.
911 * sh-dis.c: Likewise.
912 * sh64-dis.c: Delete.
913 * sh64-opc.c: Delete.
914 * sh64-opc.h: Delete.
915 * Makefile.in: Regenerate.
916 * configure: Regenerate.
917 * po/POTFILES.in: Regenerate.
919 2018-04-16 Alan Modra <amodra@gmail.com>
921 * Makefile.am: Remove w65 support.
922 * configure.ac: Likewise.
923 * disassemble.c: Likewise.
924 * disassemble.h: Likewise.
927 * Makefile.in: Regenerate.
928 * configure: Regenerate.
929 * po/POTFILES.in: Regenerate.
931 2018-04-16 Alan Modra <amodra@gmail.com>
933 * configure.ac: Remove we32k support.
934 * configure: Regenerate.
936 2018-04-16 Alan Modra <amodra@gmail.com>
938 * Makefile.am: Remove m88k support.
939 * configure.ac: Likewise.
940 * disassemble.c: Likewise.
941 * disassemble.h: Likewise.
942 * m88k-dis.c: Delete.
943 * Makefile.in: Regenerate.
944 * configure: Regenerate.
945 * po/POTFILES.in: Regenerate.
947 2018-04-16 Alan Modra <amodra@gmail.com>
949 * Makefile.am: Remove i370 support.
950 * configure.ac: Likewise.
951 * disassemble.c: Likewise.
952 * disassemble.h: Likewise.
953 * i370-dis.c: Delete.
954 * i370-opc.c: Delete.
955 * Makefile.in: Regenerate.
956 * configure: Regenerate.
957 * po/POTFILES.in: Regenerate.
959 2018-04-16 Alan Modra <amodra@gmail.com>
961 * Makefile.am: Remove h8500 support.
962 * configure.ac: Likewise.
963 * disassemble.c: Likewise.
964 * disassemble.h: Likewise.
965 * h8500-dis.c: Delete.
966 * h8500-opc.h: Delete.
967 * Makefile.in: Regenerate.
968 * configure: Regenerate.
969 * po/POTFILES.in: Regenerate.
971 2018-04-16 Alan Modra <amodra@gmail.com>
973 * configure.ac: Remove tahoe support.
974 * configure: Regenerate.
976 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
978 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
980 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
982 * i386-tbl.h: Regenerated.
984 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
986 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
987 PREFIX_MOD_1_0FAE_REG_6.
989 (OP_E_register): Use va_mode.
990 * i386-dis-evex.h (prefix_table):
991 New instructions (see prefixes above).
992 * i386-gen.c (cpu_flag_init): Add WAITPKG.
993 (cpu_flags): Likewise.
994 * i386-opc.h (enum): Likewise.
995 (i386_cpu_flags): Likewise.
996 * i386-opc.tbl: Add umonitor, umwait, tpause.
997 * i386-init.h: Regenerate.
998 * i386-tbl.h: Likewise.
1000 2018-04-11 Alan Modra <amodra@gmail.com>
1002 * opcodes/i860-dis.c: Delete.
1003 * opcodes/i960-dis.c: Delete.
1004 * Makefile.am: Remove i860 and i960 support.
1005 * configure.ac: Likewise.
1006 * disassemble.c: Likewise.
1007 * disassemble.h: Likewise.
1008 * Makefile.in: Regenerate.
1009 * configure: Regenerate.
1010 * po/POTFILES.in: Regenerate.
1012 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1015 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1017 (print_insn): Clear vex instead of vex.evex.
1019 2018-04-04 Nick Clifton <nickc@redhat.com>
1021 * po/es.po: Updated Spanish translation.
1023 2018-03-28 Jan Beulich <jbeulich@suse.com>
1025 * i386-gen.c (opcode_modifiers): Delete VecESize.
1026 * i386-opc.h (VecESize): Delete.
1027 (struct i386_opcode_modifier): Delete vecesize.
1028 * i386-opc.tbl: Drop VecESize.
1029 * i386-tlb.h: Re-generate.
1031 2018-03-28 Jan Beulich <jbeulich@suse.com>
1033 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1034 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1035 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1036 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1037 * i386-tlb.h: Re-generate.
1039 2018-03-28 Jan Beulich <jbeulich@suse.com>
1041 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1043 * i386-tlb.h: Re-generate.
1045 2018-03-28 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1048 (vex_len_table): Drop Y for vcvt*2si.
1049 (putop): Replace plain 'Y' handling by abort().
1051 2018-03-28 Nick Clifton <nickc@redhat.com>
1054 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1055 instructions with only a base address register.
1056 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1057 handle AARHC64_OPND_SVE_ADDR_R.
1058 (aarch64_print_operand): Likewise.
1059 * aarch64-asm-2.c: Regenerate.
1060 * aarch64_dis-2.c: Regenerate.
1061 * aarch64-opc-2.c: Regenerate.
1063 2018-03-22 Jan Beulich <jbeulich@suse.com>
1065 * i386-opc.tbl: Drop VecESize from register only insn forms and
1066 memory forms not allowing broadcast.
1067 * i386-tlb.h: Re-generate.
1069 2018-03-22 Jan Beulich <jbeulich@suse.com>
1071 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1072 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1073 sha256*): Drop Disp<N>.
1075 2018-03-22 Jan Beulich <jbeulich@suse.com>
1077 * i386-dis.c (EbndS, bnd_swap_mode): New.
1078 (prefix_table): Use EbndS.
1079 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1080 * i386-opc.tbl (bndmov): Move misplaced Load.
1081 * i386-tlb.h: Re-generate.
1083 2018-03-22 Jan Beulich <jbeulich@suse.com>
1085 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1086 templates allowing memory operands and folded ones for register
1088 * i386-tlb.h: Re-generate.
1090 2018-03-22 Jan Beulich <jbeulich@suse.com>
1092 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1093 256-bit templates. Drop redundant leftover Disp<N>.
1094 * i386-tlb.h: Re-generate.
1096 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1098 * riscv-opc.c (riscv_insn_types): New.
1100 2018-03-13 Nick Clifton <nickc@redhat.com>
1102 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1104 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1106 * i386-opc.tbl: Add Optimize to clr.
1107 * i386-tbl.h: Regenerated.
1109 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1111 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1112 * i386-opc.h (OldGcc): Removed.
1113 (i386_opcode_modifier): Remove oldgcc.
1114 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1115 instructions for old (<= 2.8.1) versions of gcc.
1116 * i386-tbl.h: Regenerated.
1118 2018-03-08 Jan Beulich <jbeulich@suse.com>
1120 * i386-opc.h (EVEXDYN): New.
1121 * i386-opc.tbl: Fold various AVX512VL templates.
1122 * i386-tlb.h: Re-generate.
1124 2018-03-08 Jan Beulich <jbeulich@suse.com>
1126 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1127 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1128 vpexpandd, vpexpandq): Fold AFX512VF templates.
1129 * i386-tlb.h: Re-generate.
1131 2018-03-08 Jan Beulich <jbeulich@suse.com>
1133 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1134 Fold 128- and 256-bit VEX-encoded templates.
1135 * i386-tlb.h: Re-generate.
1137 2018-03-08 Jan Beulich <jbeulich@suse.com>
1139 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1140 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1141 vpexpandd, vpexpandq): Fold AVX512F templates.
1142 * i386-tlb.h: Re-generate.
1144 2018-03-08 Jan Beulich <jbeulich@suse.com>
1146 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1147 64-bit templates. Drop Disp<N>.
1148 * i386-tlb.h: Re-generate.
1150 2018-03-08 Jan Beulich <jbeulich@suse.com>
1152 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1153 and 256-bit templates.
1154 * i386-tlb.h: Re-generate.
1156 2018-03-08 Jan Beulich <jbeulich@suse.com>
1158 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1159 * i386-tlb.h: Re-generate.
1161 2018-03-08 Jan Beulich <jbeulich@suse.com>
1163 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1165 * i386-tlb.h: Re-generate.
1167 2018-03-08 Jan Beulich <jbeulich@suse.com>
1169 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1170 * i386-tlb.h: Re-generate.
1172 2018-03-08 Jan Beulich <jbeulich@suse.com>
1174 * i386-gen.c (opcode_modifiers): Delete FloatD.
1175 * i386-opc.h (FloatD): Delete.
1176 (struct i386_opcode_modifier): Delete floatd.
1177 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1179 * i386-tlb.h: Re-generate.
1181 2018-03-08 Jan Beulich <jbeulich@suse.com>
1183 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1185 2018-03-08 Jan Beulich <jbeulich@suse.com>
1187 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1188 * i386-tlb.h: Re-generate.
1190 2018-03-08 Jan Beulich <jbeulich@suse.com>
1192 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1194 * i386-tlb.h: Re-generate.
1196 2018-03-07 Alan Modra <amodra@gmail.com>
1198 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1200 * disassemble.h (print_insn_rs6000): Delete.
1201 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1202 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1203 (print_insn_rs6000): Delete.
1205 2018-03-03 Alan Modra <amodra@gmail.com>
1207 * sysdep.h (opcodes_error_handler): Define.
1208 (_bfd_error_handler): Declare.
1209 * Makefile.am: Remove stray #.
1210 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1212 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1213 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1214 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1215 opcodes_error_handler to print errors. Standardize error messages.
1216 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1217 and include opintl.h.
1218 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1219 * i386-gen.c: Standardize error messages.
1220 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1221 * Makefile.in: Regenerate.
1222 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1223 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1224 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1225 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1226 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1227 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1228 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1229 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1230 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1231 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1232 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1233 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1234 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1236 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1238 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1239 vpsub[bwdq] instructions.
1240 * i386-tbl.h: Regenerated.
1242 2018-03-01 Alan Modra <amodra@gmail.com>
1244 * configure.ac (ALL_LINGUAS): Sort.
1245 * configure: Regenerate.
1247 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1249 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1250 macro by assignements.
1252 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1255 * i386-gen.c (opcode_modifiers): Add Optimize.
1256 * i386-opc.h (Optimize): New enum.
1257 (i386_opcode_modifier): Add optimize.
1258 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1259 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1260 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1261 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1262 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1264 * i386-tbl.h: Regenerated.
1266 2018-02-26 Alan Modra <amodra@gmail.com>
1268 * crx-dis.c (getregliststring): Allocate a large enough buffer
1269 to silence false positive gcc8 warning.
1271 2018-02-22 Shea Levy <shea@shealevy.com>
1273 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1275 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1277 * i386-opc.tbl: Add {rex},
1278 * i386-tbl.h: Regenerated.
1280 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1282 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1283 (mips16_opcodes): Replace `M' with `m' for "restore".
1285 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1287 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1289 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1291 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1292 variable to `function_index'.
1294 2018-02-13 Nick Clifton <nickc@redhat.com>
1297 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1298 about truncation of printing.
1300 2018-02-12 Henry Wong <henry@stuffedcow.net>
1302 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1304 2018-02-05 Nick Clifton <nickc@redhat.com>
1306 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1308 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1310 * i386-dis.c (enum): Add pconfig.
1311 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1312 (cpu_flags): Add CpuPCONFIG.
1313 * i386-opc.h (enum): Add CpuPCONFIG.
1314 (i386_cpu_flags): Add cpupconfig.
1315 * i386-opc.tbl: Add PCONFIG instruction.
1316 * i386-init.h: Regenerate.
1317 * i386-tbl.h: Likewise.
1319 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1321 * i386-dis.c (enum): Add PREFIX_0F09.
1322 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1323 (cpu_flags): Add CpuWBNOINVD.
1324 * i386-opc.h (enum): Add CpuWBNOINVD.
1325 (i386_cpu_flags): Add cpuwbnoinvd.
1326 * i386-opc.tbl: Add WBNOINVD instruction.
1327 * i386-init.h: Regenerate.
1328 * i386-tbl.h: Likewise.
1330 2018-01-17 Jim Wilson <jimw@sifive.com>
1332 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1334 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1336 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1337 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1338 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1339 (cpu_flags): Add CpuIBT, CpuSHSTK.
1340 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1341 (i386_cpu_flags): Add cpuibt, cpushstk.
1342 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1343 * i386-init.h: Regenerate.
1344 * i386-tbl.h: Likewise.
1346 2018-01-16 Nick Clifton <nickc@redhat.com>
1348 * po/pt_BR.po: Updated Brazilian Portugese translation.
1349 * po/de.po: Updated German translation.
1351 2018-01-15 Jim Wilson <jimw@sifive.com>
1353 * riscv-opc.c (match_c_nop): New.
1354 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1356 2018-01-15 Nick Clifton <nickc@redhat.com>
1358 * po/uk.po: Updated Ukranian translation.
1360 2018-01-13 Nick Clifton <nickc@redhat.com>
1362 * po/opcodes.pot: Regenerated.
1364 2018-01-13 Nick Clifton <nickc@redhat.com>
1366 * configure: Regenerate.
1368 2018-01-13 Nick Clifton <nickc@redhat.com>
1370 2.30 branch created.
1372 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1374 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1375 * i386-tbl.h: Regenerate.
1377 2018-01-10 Jan Beulich <jbeulich@suse.com>
1379 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1380 * i386-tbl.h: Re-generate.
1382 2018-01-10 Jan Beulich <jbeulich@suse.com>
1384 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1385 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1386 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1387 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1388 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1389 Disp8MemShift of AVX512VL forms.
1390 * i386-tbl.h: Re-generate.
1392 2018-01-09 Jim Wilson <jimw@sifive.com>
1394 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1395 then the hi_addr value is zero.
1397 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1399 * arm-dis.c (arm_opcodes): Add csdb.
1400 (thumb32_opcodes): Add csdb.
1402 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1404 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1405 * aarch64-asm-2.c: Regenerate.
1406 * aarch64-dis-2.c: Regenerate.
1407 * aarch64-opc-2.c: Regenerate.
1409 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1412 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1413 Remove AVX512 vmovd with 64-bit operands.
1414 * i386-tbl.h: Regenerated.
1416 2018-01-05 Jim Wilson <jimw@sifive.com>
1418 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1421 2018-01-03 Alan Modra <amodra@gmail.com>
1423 Update year range in copyright notice of all files.
1425 2018-01-02 Jan Beulich <jbeulich@suse.com>
1427 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1428 and OPERAND_TYPE_REGZMM entries.
1430 For older changes see ChangeLog-2017
1432 Copyright (C) 2018 Free Software Foundation, Inc.
1434 Copying and distribution of this file, with or without modification,
1435 are permitted in any medium without royalty provided the copyright
1436 notice and this notice are preserved.
1442 version-control: never