1 2019-12-20 Alan Modra <amodra@gmail.com>
4 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
5 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
6 printed. Print .word in more cases.
8 2019-12-20 Alan Modra <amodra@gmail.com>
10 * or1k-ibld.c: Regenerate.
12 2019-12-20 Alan Modra <amodra@gmail.com>
14 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
17 2019-12-20 Alan Modra <amodra@gmail.com>
19 * m68hc11-dis.c (read_memory): Delete forward decls.
20 (print_indexed_operand, print_insn): Likewise.
21 (print_indexed_operand): Formatting. Don't rely on short being
22 exactly 16 bits, make sign extension explicit.
23 (print_insn): Likewise. Avoid signed overflow.
25 2019-12-19 Alan Modra <amodra@gmail.com>
27 * vax-dis.c (print_insn_mode): Stop index mode recursion.
29 2019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
32 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
34 * microblaze-opc.h (opcodes): Adjust to suit.
36 2019-12-18 Alan Modra <amodra@gmail.com>
38 * alpha-opc.c (OP): Avoid signed overflow.
39 * arm-dis.c (print_insn): Likewise.
40 * mcore-dis.c (print_insn_mcore): Likewise.
41 * pj-dis.c (get_int): Likewise.
42 * ppc-opc.c (EBD15, EBD15BI): Likewise.
43 * score7-dis.c (s7_print_insn): Likewise.
44 * tic30-dis.c (print_insn_tic30): Likewise.
45 * v850-opc.c (insert_SELID): Likewise.
46 * vax-dis.c (print_insn_vax): Likewise.
47 * arc-ext.c (create_map): Likewise.
48 (struct ExtAuxRegister): Make "address" field unsigned int.
49 (arcExtMap_auxRegName): Pass unsigned address.
50 (dump_ARC_extmap): Adjust.
51 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
53 2019-12-17 Alan Modra <amodra@gmail.com>
55 * visium-dis.c (print_insn_visium): Avoid signed overflow.
57 2019-12-17 Alan Modra <amodra@gmail.com>
59 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
60 (value_fit_unsigned_field_p): Likewise.
61 (aarch64_wide_constant_p): Likewise.
62 (operand_general_constraint_met_p): Likewise.
63 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
65 2019-12-17 Alan Modra <amodra@gmail.com>
67 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
68 (print_insn_nds32): Use uint64_t for "given" and "given1".
70 2019-12-17 Alan Modra <amodra@gmail.com>
72 * tic80-dis.c: Delete file.
73 * tic80-opc.c: Delete file.
74 * disassemble.c: Remove tic80 support.
75 * disassemble.h: Likewise.
76 * Makefile.am: Likewise.
77 * configure.ac: Likewise.
78 * Makefile.in: Regenerate.
79 * configure: Regenerate.
80 * po/POTFILES.in: Regenerate.
82 2019-12-17 Alan Modra <amodra@gmail.com>
84 * bpf-ibld.c: Regenerate.
86 2019-12-16 Alan Modra <amodra@gmail.com>
88 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
90 (aarch64_ext_imm): Avoid signed overflow.
92 2019-12-16 Alan Modra <amodra@gmail.com>
94 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
96 2019-12-16 Alan Modra <amodra@gmail.com>
98 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
100 2019-12-16 Alan Modra <amodra@gmail.com>
102 * xstormy16-ibld.c: Regenerate.
104 2019-12-16 Alan Modra <amodra@gmail.com>
106 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
107 value adjustment so that it doesn't affect reg field too.
109 2019-12-16 Alan Modra <amodra@gmail.com>
111 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
112 (get_number_of_operands, getargtype, getbits, getregname),
113 (getcopregname, getprocregname, gettrapstring, getcinvstring),
114 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
115 (powerof2, match_opcode, make_instruction, print_arguments),
116 (print_arg): Delete forward declarations, moving static to..
117 (getregname, getcopregname, getregliststring): ..these definitions.
118 (build_mask): Return unsigned int mask.
119 (match_opcode): Use unsigned int vars.
121 2019-12-16 Alan Modra <amodra@gmail.com>
123 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
125 2019-12-16 Alan Modra <amodra@gmail.com>
127 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
128 (struct objdump_disasm_info): Delete.
129 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
130 N32_IMMS to unsigned before shifting left.
132 2019-12-16 Alan Modra <amodra@gmail.com>
134 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
135 (print_insn_moxie): Remove unnecessary cast.
137 2019-12-12 Alan Modra <amodra@gmail.com>
139 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
142 2019-12-11 Alan Modra <amodra@gmail.com>
144 * arc-dis.c (BITS): Don't truncate high bits with shifts.
145 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
146 * tic54x-dis.c (print_instruction): Likewise.
147 * tilegx-opc.c (parse_insn_tilegx): Likewise.
148 * tilepro-opc.c (parse_insn_tilepro): Likewise.
149 * visium-dis.c (disassem_class0): Likewise.
150 * pdp11-dis.c (sign_extend): Likewise.
152 * epiphany-ibld.c: Regenerate.
153 * lm32-ibld.c: Regenerate.
154 * m32c-ibld.c: Regenerate.
156 2019-12-11 Alan Modra <amodra@gmail.com>
158 * ns32k-dis.c (sign_extend): Correct last patch.
160 2019-12-11 Alan Modra <amodra@gmail.com>
162 * vax-dis.c (NEXTLONG): Avoid signed overflow.
164 2019-12-11 Alan Modra <amodra@gmail.com>
166 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
167 sign extend using shifts.
169 2019-12-11 Alan Modra <amodra@gmail.com>
171 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
173 2019-12-11 Alan Modra <amodra@gmail.com>
175 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
176 on NULL registertable entry.
177 (tic4x_hash_opcode): Use unsigned arithmetic.
179 2019-12-11 Alan Modra <amodra@gmail.com>
181 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
183 2019-12-11 Alan Modra <amodra@gmail.com>
185 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
186 (bit_extract_simple, sign_extend): Likewise.
188 2019-12-11 Alan Modra <amodra@gmail.com>
190 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
192 2019-12-11 Alan Modra <amodra@gmail.com>
194 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
196 2019-12-11 Alan Modra <amodra@gmail.com>
198 * m68k-dis.c (COERCE32): Cast value first.
199 (NEXTLONG, NEXTULONG): Avoid signed overflow.
201 2019-12-11 Alan Modra <amodra@gmail.com>
203 * h8300-dis.c (extract_immediate): Avoid signed overflow.
204 (bfd_h8_disassemble): Likewise.
206 2019-12-11 Alan Modra <amodra@gmail.com>
208 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
209 past end of operands array.
211 2019-12-11 Alan Modra <amodra@gmail.com>
213 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
214 overflow when collecting bytes of a number.
216 2019-12-11 Alan Modra <amodra@gmail.com>
218 * cris-dis.c (print_with_operands): Avoid signed integer
219 overflow when collecting bytes of a 32-bit integer.
221 2019-12-11 Alan Modra <amodra@gmail.com>
223 * cr16-dis.c (EXTRACT, SBM): Rewrite.
224 (cr16_match_opcode): Delete duplicate bcond test.
226 2019-12-11 Alan Modra <amodra@gmail.com>
228 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
230 (MASKBITS, SIGNEXTEND): Rewrite.
231 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
232 unsigned arithmetic, instead assign result of SIGNEXTEND back
234 (fmtconst_val): Use 1u in shift expression.
236 2019-12-11 Alan Modra <amodra@gmail.com>
238 * arc-dis.c (find_format_from_table): Use ull constant when
239 shifting by up to 32.
241 2019-12-11 Alan Modra <amodra@gmail.com>
244 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
245 false when field is zero for sve_size_tsz_bhs.
247 2019-12-11 Alan Modra <amodra@gmail.com>
249 * epiphany-ibld.c: Regenerate.
251 2019-12-10 Alan Modra <amodra@gmail.com>
254 * disassemble.c (disassemble_free_target): New function.
256 2019-12-10 Alan Modra <amodra@gmail.com>
258 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
259 * disassemble.c (disassemble_init_for_target): Likewise.
260 * bpf-dis.c: Regenerate.
261 * epiphany-dis.c: Regenerate.
262 * fr30-dis.c: Regenerate.
263 * frv-dis.c: Regenerate.
264 * ip2k-dis.c: Regenerate.
265 * iq2000-dis.c: Regenerate.
266 * lm32-dis.c: Regenerate.
267 * m32c-dis.c: Regenerate.
268 * m32r-dis.c: Regenerate.
269 * mep-dis.c: Regenerate.
270 * mt-dis.c: Regenerate.
271 * or1k-dis.c: Regenerate.
272 * xc16x-dis.c: Regenerate.
273 * xstormy16-dis.c: Regenerate.
275 2019-12-10 Alan Modra <amodra@gmail.com>
277 * ppc-dis.c (private): Delete variable.
278 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
279 (powerpc_init_dialect): Don't use global private.
281 2019-12-10 Alan Modra <amodra@gmail.com>
283 * s12z-opc.c: Formatting.
285 2019-12-08 Alan Modra <amodra@gmail.com>
287 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
290 2019-12-05 Jan Beulich <jbeulich@suse.com>
292 * aarch64-tbl.h (aarch64_feature_crypto,
293 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
294 CRYPTO_V8_2_INSN): Delete.
296 2019-12-05 Alan Modra <amodra@gmail.com>
299 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
300 (struct string_buf): New.
301 (strbuf): New function.
302 (get_field): Use strbuf rather than strdup of local temp.
303 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
304 (get_field_rfsl, get_field_imm15): Likewise.
305 (get_field_rd, get_field_r1, get_field_r2): Update macros.
306 (get_field_special): Likewise. Don't strcpy spr. Formatting.
307 (print_insn_microblaze): Formatting. Init and pass string_buf to
310 2019-12-04 Jan Beulich <jbeulich@suse.com>
312 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
313 * i386-tbl.h: Re-generate.
315 2019-12-04 Jan Beulich <jbeulich@suse.com>
317 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
319 2019-12-04 Jan Beulich <jbeulich@suse.com>
321 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
323 (xbegin): Drop DefaultSize.
324 * i386-tbl.h: Re-generate.
326 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
328 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
329 Change the coproc CRC conditions to use the extension
330 feature set, second word, base on ARM_EXT2_CRC.
332 2019-11-14 Jan Beulich <jbeulich@suse.com>
334 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
335 * i386-tbl.h: Re-generate.
337 2019-11-14 Jan Beulich <jbeulich@suse.com>
339 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
340 JumpInterSegment, and JumpAbsolute entries.
341 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
342 JUMP_ABSOLUTE): Define.
343 (struct i386_opcode_modifier): Extend jump field to 3 bits.
344 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
346 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
347 JumpInterSegment): Define.
348 * i386-tbl.h: Re-generate.
350 2019-11-14 Jan Beulich <jbeulich@suse.com>
352 * i386-gen.c (operand_type_init): Remove
353 OPERAND_TYPE_JUMPABSOLUTE entry.
354 (opcode_modifiers): Add JumpAbsolute entry.
355 (operand_types): Remove JumpAbsolute entry.
356 * i386-opc.h (JumpAbsolute): Move between enums.
357 (struct i386_opcode_modifier): Add jumpabsolute field.
358 (union i386_operand_type): Remove jumpabsolute field.
359 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
360 * i386-init.h, i386-tbl.h: Re-generate.
362 2019-11-14 Jan Beulich <jbeulich@suse.com>
364 * i386-gen.c (opcode_modifiers): Add AnySize entry.
365 (operand_types): Remove AnySize entry.
366 * i386-opc.h (AnySize): Move between enums.
367 (struct i386_opcode_modifier): Add anysize field.
368 (OTUnused): Un-comment.
369 (union i386_operand_type): Remove anysize field.
370 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
371 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
372 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
374 * i386-tbl.h: Re-generate.
376 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
378 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
379 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
380 use the floating point register (FPR).
382 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
384 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
386 (is_mve_encoding_conflict): Update cmode conflict checks for
389 2019-11-12 Jan Beulich <jbeulich@suse.com>
391 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
393 (operand_types): Remove EsSeg entry.
394 (main): Replace stale use of OTMax.
395 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
396 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
398 (OTUnused): Comment out.
399 (union i386_operand_type): Remove esseg field.
400 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
401 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
402 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
403 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
404 * i386-init.h, i386-tbl.h: Re-generate.
406 2019-11-12 Jan Beulich <jbeulich@suse.com>
408 * i386-gen.c (operand_instances): Add RegB entry.
409 * i386-opc.h (enum operand_instance): Add RegB.
410 * i386-opc.tbl (RegC, RegD, RegB): Define.
411 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
412 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
413 monitorx, mwaitx): Drop ImmExt and convert encodings
415 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
416 (edx, rdx): Add Instance=RegD.
417 (ebx, rbx): Add Instance=RegB.
418 * i386-tbl.h: Re-generate.
420 2019-11-12 Jan Beulich <jbeulich@suse.com>
422 * i386-gen.c (operand_type_init): Adjust
423 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
424 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
425 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
426 (operand_instances): New.
427 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
428 (output_operand_type): New parameter "instance". Process it.
429 (process_i386_operand_type): New local variable "instance".
430 (main): Adjust static assertions.
431 * i386-opc.h (INSTANCE_WIDTH): Define.
432 (enum operand_instance): New.
433 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
434 (union i386_operand_type): Replace acc, inoutportreg, and
435 shiftcount by instance.
436 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
437 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
439 * i386-init.h, i386-tbl.h: Re-generate.
441 2019-11-11 Jan Beulich <jbeulich@suse.com>
443 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
444 smaxp/sminp entries' "tied_operand" field to 2.
446 2019-11-11 Jan Beulich <jbeulich@suse.com>
448 * aarch64-opc.c (operand_general_constraint_met_p): Replace
449 "index" local variable by that of the already existing "num".
451 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
454 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
455 * i386-tbl.h: Regenerated.
457 2019-11-08 Jan Beulich <jbeulich@suse.com>
459 * i386-gen.c (operand_type_init): Add Class= to
460 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
461 OPERAND_TYPE_REGBND entry.
462 (operand_classes): Add RegMask and RegBND entries.
463 (operand_types): Drop RegMask and RegBND entry.
464 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
465 (RegMask, RegBND): Delete.
466 (union i386_operand_type): Remove regmask and regbnd fields.
467 * i386-opc.tbl (RegMask, RegBND): Define.
468 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
470 * i386-init.h, i386-tbl.h: Re-generate.
472 2019-11-08 Jan Beulich <jbeulich@suse.com>
474 * i386-gen.c (operand_type_init): Add Class= to
475 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
476 OPERAND_TYPE_REGZMM entries.
477 (operand_classes): Add RegMMX and RegSIMD entries.
478 (operand_types): Drop RegMMX and RegSIMD entries.
479 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
480 (RegMMX, RegSIMD): Delete.
481 (union i386_operand_type): Remove regmmx and regsimd fields.
482 * i386-opc.tbl (RegMMX): Define.
483 (RegXMM, RegYMM, RegZMM): Add Class=.
484 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
486 * i386-init.h, i386-tbl.h: Re-generate.
488 2019-11-08 Jan Beulich <jbeulich@suse.com>
490 * i386-gen.c (operand_type_init): Add Class= to
491 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
493 (operand_classes): Add RegCR, RegDR, and RegTR entries.
494 (operand_types): Drop Control, Debug, and Test entries.
495 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
496 (Control, Debug, Test): Delete.
497 (union i386_operand_type): Remove control, debug, and test
499 * i386-opc.tbl (Control, Debug, Test): Define.
500 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
501 Class=RegDR, and Test by Class=RegTR.
502 * i386-init.h, i386-tbl.h: Re-generate.
504 2019-11-08 Jan Beulich <jbeulich@suse.com>
506 * i386-gen.c (operand_type_init): Add Class= to
507 OPERAND_TYPE_SREG entry.
508 (operand_classes): Add SReg entry.
509 (operand_types): Drop SReg entry.
510 * i386-opc.h (enum operand_class): Add SReg.
512 (union i386_operand_type): Remove sreg field.
513 * i386-opc.tbl (SReg): Define.
514 * i386-reg.tbl: Replace SReg by Class=SReg.
515 * i386-init.h, i386-tbl.h: Re-generate.
517 2019-11-08 Jan Beulich <jbeulich@suse.com>
519 * i386-gen.c (operand_type_init): Add Class=. New
520 OPERAND_TYPE_ANYIMM entry.
521 (operand_classes): New.
522 (operand_types): Drop Reg entry.
523 (output_operand_type): New parameter "class". Process it.
524 (process_i386_operand_type): New local variable "class".
525 (main): Adjust static assertions.
526 * i386-opc.h (CLASS_WIDTH): Define.
527 (enum operand_class): New.
528 (Reg): Replace by Class. Adjust comment.
529 (union i386_operand_type): Replace reg by class.
530 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
532 * i386-reg.tbl: Replace Reg by Class=Reg.
533 * i386-init.h: Re-generate.
535 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
537 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
538 (aarch64_opcode_table): Add data gathering hint mnemonic.
539 * opcodes/aarch64-dis-2.c: Account for new instruction.
541 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
543 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
546 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
548 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
549 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
550 aarch64_feature_f64mm): New feature sets.
551 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
552 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
554 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
556 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
557 (OP_SVE_QQQ): New qualifier.
558 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
559 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
560 the movprfx constraint.
561 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
562 (aarch64_opcode_table): Define new instructions smmla,
563 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
565 * aarch64-opc.c (operand_general_constraint_met_p): Handle
566 AARCH64_OPND_SVE_ADDR_RI_S4x32.
567 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
568 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
569 Account for new instructions.
570 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
572 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
574 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
575 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
577 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
579 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
580 (neon_opcodes): Add bfloat SIMD instructions.
581 (print_insn_coprocessor): Add new control character %b to print
582 condition code without checking cp_num.
583 (print_insn_neon): Account for BFloat16 instructions that have no
584 special top-byte handling.
586 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
587 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
589 * arm-dis.c (print_insn_coprocessor,
590 print_insn_generic_coprocessor): Create wrapper functions around
591 the implementation of the print_insn_coprocessor control codes.
592 (print_insn_coprocessor_1): Original print_insn_coprocessor
593 function that now takes which array to look at as an argument.
594 (print_insn_arm): Use both print_insn_coprocessor and
595 print_insn_generic_coprocessor.
596 (print_insn_thumb32): As above.
598 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
599 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
601 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
602 in reglane special case.
603 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
604 aarch64_find_next_opcode): Account for new instructions.
605 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
606 in reglane special case.
607 * aarch64-opc.c (struct operand_qualifier_data): Add data for
608 new AARCH64_OPND_QLF_S_2H qualifier.
609 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
610 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
611 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
613 (BFLOAT_SVE, BFLOAT): New feature set macros.
614 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
616 (aarch64_opcode_table): Define new instructions bfdot,
617 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
620 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
621 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
623 * aarch64-tbl.h (ARMV8_6): New macro.
625 2019-11-07 Jan Beulich <jbeulich@suse.com>
627 * i386-dis.c (prefix_table): Add mcommit.
628 (rm_table): Add rdpru.
629 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
630 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
631 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
632 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
633 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
634 * i386-opc.tbl (mcommit, rdpru): New.
635 * i386-init.h, i386-tbl.h: Re-generate.
637 2019-11-07 Jan Beulich <jbeulich@suse.com>
639 * i386-dis.c (OP_Mwait): Drop local variable "names", use
641 (OP_Monitor): Drop local variable "op1_names", re-purpose
642 "names" for it instead, and replace former "names" uses by
645 2019-11-07 Jan Beulich <jbeulich@suse.com>
648 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
650 * opcodes/i386-tbl.h: Re-generate.
652 2019-11-05 Jan Beulich <jbeulich@suse.com>
654 * i386-dis.c (OP_Mwaitx): Delete.
655 (prefix_table): Use OP_Mwait for mwaitx entry.
656 (OP_Mwait): Also handle mwaitx.
658 2019-11-05 Jan Beulich <jbeulich@suse.com>
660 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
661 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
662 (prefix_table): Add respective entries.
663 (rm_table): Link to those entries.
665 2019-11-05 Jan Beulich <jbeulich@suse.com>
667 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
668 (REG_0F1C_P_0_MOD_0): ... this.
669 (REG_0F1E_MOD_3): Rename to ...
670 (REG_0F1E_P_1_MOD_3): ... this.
671 (RM_0F01_REG_5): Rename to ...
672 (RM_0F01_REG_5_MOD_3): ... this.
673 (RM_0F01_REG_7): Rename to ...
674 (RM_0F01_REG_7_MOD_3): ... this.
675 (RM_0F1E_MOD_3_REG_7): Rename to ...
676 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
677 (RM_0FAE_REG_6): Rename to ...
678 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
679 (RM_0FAE_REG_7): Rename to ...
680 (RM_0FAE_REG_7_MOD_3): ... this.
681 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
682 (PREFIX_0F01_REG_5_MOD_0): ... this.
683 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
684 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
685 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
686 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
687 (PREFIX_0FAE_REG_0): Rename to ...
688 (PREFIX_0FAE_REG_0_MOD_3): ... this.
689 (PREFIX_0FAE_REG_1): Rename to ...
690 (PREFIX_0FAE_REG_1_MOD_3): ... this.
691 (PREFIX_0FAE_REG_2): Rename to ...
692 (PREFIX_0FAE_REG_2_MOD_3): ... this.
693 (PREFIX_0FAE_REG_3): Rename to ...
694 (PREFIX_0FAE_REG_3_MOD_3): ... this.
695 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
696 (PREFIX_0FAE_REG_4_MOD_0): ... this.
697 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
698 (PREFIX_0FAE_REG_4_MOD_3): ... this.
699 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
700 (PREFIX_0FAE_REG_5_MOD_0): ... this.
701 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
702 (PREFIX_0FAE_REG_5_MOD_3): ... this.
703 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
704 (PREFIX_0FAE_REG_6_MOD_0): ... this.
705 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
706 (PREFIX_0FAE_REG_6_MOD_3): ... this.
707 (PREFIX_0FAE_REG_7): Rename to ...
708 (PREFIX_0FAE_REG_7_MOD_0): ... this.
709 (PREFIX_MOD_0_0FC3): Rename to ...
710 (PREFIX_0FC3_MOD_0): ... this.
711 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
712 (PREFIX_0FC7_REG_6_MOD_0): ... this.
713 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
714 (PREFIX_0FC7_REG_6_MOD_3): ... this.
715 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
716 (PREFIX_0FC7_REG_7_MOD_3): ... this.
717 (reg_table, prefix_table, mod_table, rm_table): Adjust
720 2019-11-04 Nick Clifton <nickc@redhat.com>
722 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
723 of a v850 system register. Move the v850_sreg_names array into
725 (get_v850_reg_name): Likewise for ordinary register names.
726 (get_v850_vreg_name): Likewise for vector register names.
727 (get_v850_cc_name): Likewise for condition codes.
728 * get_v850_float_cc_name): Likewise for floating point condition
730 (get_v850_cacheop_name): Likewise for cache-ops.
731 (get_v850_prefop_name): Likewise for pref-ops.
732 (disassemble): Use the new accessor functions.
734 2019-10-30 Delia Burduv <delia.burduv@arm.com>
736 * aarch64-opc.c (print_immediate_offset_address): Don't print the
737 immediate for the writeback form of ldraa/ldrab if it is 0.
738 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
739 * aarch64-opc-2.c: Regenerated.
741 2019-10-30 Jan Beulich <jbeulich@suse.com>
743 * i386-gen.c (operand_type_shorthands): Delete.
744 (operand_type_init): Expand previous shorthands.
745 (set_bitfield_from_shorthand): Rename back to ...
746 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
747 of operand_type_init[].
748 (set_bitfield): Adjust call to the above function.
749 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
750 RegXMM, RegYMM, RegZMM): Define.
751 * i386-reg.tbl: Expand prior shorthands.
753 2019-10-30 Jan Beulich <jbeulich@suse.com>
755 * i386-gen.c (output_i386_opcode): Change order of fields
757 * i386-opc.h (struct insn_template): Move operands field.
758 Convert extension_opcode field to unsigned short.
759 * i386-tbl.h: Re-generate.
761 2019-10-30 Jan Beulich <jbeulich@suse.com>
763 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
765 * i386-opc.h (W): Extend comment.
766 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
767 general purpose variants not allowing for byte operands.
768 * i386-tbl.h: Re-generate.
770 2019-10-29 Nick Clifton <nickc@redhat.com>
772 * tic30-dis.c (print_branch): Correct size of operand array.
774 2019-10-29 Nick Clifton <nickc@redhat.com>
776 * d30v-dis.c (print_insn): Check that operand index is valid
777 before attempting to access the operands array.
779 2019-10-29 Nick Clifton <nickc@redhat.com>
781 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
782 locating the bit to be tested.
784 2019-10-29 Nick Clifton <nickc@redhat.com>
786 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
788 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
789 (print_insn_s12z): Check for illegal size values.
791 2019-10-28 Nick Clifton <nickc@redhat.com>
793 * csky-dis.c (csky_chars_to_number): Check for a negative
794 count. Use an unsigned integer to construct the return value.
796 2019-10-28 Nick Clifton <nickc@redhat.com>
798 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
799 operand buffer. Set value to 15 not 13.
800 (get_register_operand): Use OPERAND_BUFFER_LEN.
801 (get_indirect_operand): Likewise.
802 (print_two_operand): Likewise.
803 (print_three_operand): Likewise.
804 (print_oar_insn): Likewise.
806 2019-10-28 Nick Clifton <nickc@redhat.com>
808 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
809 (bit_extract_simple): Likewise.
810 (bit_copy): Likewise.
811 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
812 index_offset array are not accessed.
814 2019-10-28 Nick Clifton <nickc@redhat.com>
816 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
819 2019-10-25 Nick Clifton <nickc@redhat.com>
821 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
822 access to opcodes.op array element.
824 2019-10-23 Nick Clifton <nickc@redhat.com>
826 * rx-dis.c (get_register_name): Fix spelling typo in error
828 (get_condition_name, get_flag_name, get_double_register_name)
829 (get_double_register_high_name, get_double_register_low_name)
830 (get_double_control_register_name, get_double_condition_name)
831 (get_opsize_name, get_size_name): Likewise.
833 2019-10-22 Nick Clifton <nickc@redhat.com>
835 * rx-dis.c (get_size_name): New function. Provides safe
836 access to name array.
837 (get_opsize_name): Likewise.
838 (print_insn_rx): Use the accessor functions.
840 2019-10-16 Nick Clifton <nickc@redhat.com>
842 * rx-dis.c (get_register_name): New function. Provides safe
843 access to name array.
844 (get_condition_name, get_flag_name, get_double_register_name)
845 (get_double_register_high_name, get_double_register_low_name)
846 (get_double_control_register_name, get_double_condition_name):
848 (print_insn_rx): Use the accessor functions.
850 2019-10-09 Nick Clifton <nickc@redhat.com>
853 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
856 2019-10-07 Jan Beulich <jbeulich@suse.com>
858 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
859 (cmpsd): Likewise. Move EsSeg to other operand.
860 * opcodes/i386-tbl.h: Re-generate.
862 2019-09-23 Alan Modra <amodra@gmail.com>
864 * m68k-dis.c: Include cpu-m68k.h
866 2019-09-23 Alan Modra <amodra@gmail.com>
868 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
869 "elf/mips.h" earlier.
871 2018-09-20 Jan Beulich <jbeulich@suse.com>
874 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
876 * i386-tbl.h: Re-generate.
878 2019-09-18 Alan Modra <amodra@gmail.com>
880 * arc-ext.c: Update throughout for bfd section macro changes.
882 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
884 * Makefile.in: Re-generate.
885 * configure: Re-generate.
887 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
889 * riscv-opc.c (riscv_opcodes): Change subset field
890 to insn_class field for all instructions.
891 (riscv_insn_types): Likewise.
893 2019-09-16 Phil Blundell <pb@pbcl.net>
895 * configure: Regenerated.
897 2019-09-10 Miod Vallat <miod@online.fr>
900 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
902 2019-09-09 Phil Blundell <pb@pbcl.net>
904 binutils 2.33 branch created.
906 2019-09-03 Nick Clifton <nickc@redhat.com>
909 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
910 greater than zero before indexing via (bufcnt -1).
912 2019-09-03 Nick Clifton <nickc@redhat.com>
915 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
916 (MAX_SPEC_REG_NAME_LEN): Define.
917 (struct mmix_dis_info): Use defined constants for array lengths.
918 (get_reg_name): New function.
919 (get_sprec_reg_name): New function.
920 (print_insn_mmix): Use new functions.
922 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
924 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
925 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
926 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
928 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
930 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
931 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
932 (aarch64_sys_reg_supported_p): Update checks for the above.
934 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
936 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
937 cases MVE_SQRSHRL and MVE_UQRSHLL.
938 (print_insn_mve): Add case for specifier 'k' to check
939 specific bit of the instruction.
941 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
944 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
945 encountering an unknown machine type.
946 (print_insn_arc): Handle arc_insn_length returning 0. In error
947 cases return -1 rather than calling abort.
949 2019-08-07 Jan Beulich <jbeulich@suse.com>
951 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
952 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
954 * i386-tbl.h: Re-generate.
956 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
958 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
961 2019-07-30 Mel Chen <mel.chen@sifive.com>
963 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
964 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
966 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
969 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
971 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
972 and MPY class instructions.
973 (parse_option): Add nps400 option.
974 (print_arc_disassembler_options): Add nps400 info.
976 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
978 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
981 * arc-opc.c (RAD_CHK): Add.
982 * arc-tbl.h: Regenerate.
984 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
986 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
987 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
989 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
991 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
992 instructions as UNPREDICTABLE.
994 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
996 * bpf-desc.c: Regenerated.
998 2019-07-17 Jan Beulich <jbeulich@suse.com>
1000 * i386-gen.c (static_assert): Define.
1002 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1003 (Opcode_Modifier_Num): ... this.
1006 2019-07-16 Jan Beulich <jbeulich@suse.com>
1008 * i386-gen.c (operand_types): Move RegMem ...
1009 (opcode_modifiers): ... here.
1010 * i386-opc.h (RegMem): Move to opcode modifer enum.
1011 (union i386_operand_type): Move regmem field ...
1012 (struct i386_opcode_modifier): ... here.
1013 * i386-opc.tbl (RegMem): Define.
1014 (mov, movq): Move RegMem on segment, control, debug, and test
1016 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1017 to non-SSE2AVX flavor.
1018 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1019 Move RegMem on register only flavors. Drop IgnoreSize from
1020 legacy encoding flavors.
1021 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1023 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1024 register only flavors.
1025 (vmovd): Move RegMem and drop IgnoreSize on register only
1026 flavor. Change opcode and operand order to store form.
1027 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1029 2019-07-16 Jan Beulich <jbeulich@suse.com>
1031 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1033 * i386-opc.h (SReg2, SReg3): Replace by ...
1035 (union i386_operand_type): Replace sreg fields.
1036 * i386-opc.tbl (mov, ): Use SReg.
1037 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1039 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1040 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1042 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1044 * bpf-desc.c: Regenerate.
1045 * bpf-opc.c: Likewise.
1046 * bpf-opc.h: Likewise.
1048 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1050 * bpf-desc.c: Regenerate.
1051 * bpf-opc.c: Likewise.
1053 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1055 * arm-dis.c (print_insn_coprocessor): Rename index to
1058 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
1060 * riscv-opc.c (riscv_insn_types): Add r4 type.
1062 * riscv-opc.c (riscv_insn_types): Add b and j type.
1064 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1065 format for sb type and correct s type.
1067 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1069 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1070 SVE FMOV alias of FCPY.
1072 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1074 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1075 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1077 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1079 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1080 registers in an instruction prefixed by MOVPRFX.
1082 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1084 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1085 sve_size_13 icode to account for variant behaviour of
1087 * aarch64-dis-2.c: Regenerate.
1088 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1089 sve_size_13 icode to account for variant behaviour of
1091 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1092 (OP_SVE_VVV_Q_D): Add new qualifier.
1093 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1094 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1097 2019-07-01 Jan Beulich <jbeulich@suse.com>
1099 * opcodes/i386-gen.c (operand_type_init): Remove
1100 OPERAND_TYPE_VEC_IMM4 entry.
1101 (operand_types): Remove Vec_Imm4.
1102 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1103 (union i386_operand_type): Remove vec_imm4.
1104 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1105 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1107 2019-07-01 Jan Beulich <jbeulich@suse.com>
1109 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1110 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1111 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1112 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1113 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1114 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1115 * i386-tbl.h: Re-generate.
1117 2019-07-01 Jan Beulich <jbeulich@suse.com>
1119 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1121 * i386-tbl.h: Re-generate.
1123 2019-07-01 Jan Beulich <jbeulich@suse.com>
1125 * i386-opc.tbl (C): New.
1126 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1127 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1128 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1129 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1130 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1131 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1132 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1133 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1134 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1135 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1136 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1137 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1138 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1139 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1140 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1141 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1142 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1143 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1144 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1145 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1146 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1147 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1148 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1149 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1150 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1151 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1153 * i386-tbl.h: Re-generate.
1155 2019-07-01 Jan Beulich <jbeulich@suse.com>
1157 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1159 * i386-tbl.h: Re-generate.
1161 2019-07-01 Jan Beulich <jbeulich@suse.com>
1163 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1164 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1165 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1166 * i386-tbl.h: Re-generate.
1168 2019-07-01 Jan Beulich <jbeulich@suse.com>
1170 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1171 Disp8MemShift from register only templates.
1172 * i386-tbl.h: Re-generate.
1174 2019-07-01 Jan Beulich <jbeulich@suse.com>
1176 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1177 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1178 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1179 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1180 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1181 EVEX_W_0F11_P_3_M_1): Delete.
1182 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1183 EVEX_W_0F11_P_3): New.
1184 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1185 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1186 MOD_EVEX_0F11_PREFIX_3 table entries.
1187 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1188 PREFIX_EVEX_0F11 table entries.
1189 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1190 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1191 EVEX_W_0F11_P_3_M_{0,1} table entries.
1193 2019-07-01 Jan Beulich <jbeulich@suse.com>
1195 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1198 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1201 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1202 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1203 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1204 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1205 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1206 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1207 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1208 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1209 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1210 PREFIX_EVEX_0F38C6_REG_6 entries.
1211 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1212 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1213 EVEX_W_0F38C7_R_6_P_2 entries.
1214 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1215 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1216 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1217 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1218 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1219 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1220 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1222 2019-06-27 Jan Beulich <jbeulich@suse.com>
1224 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1225 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1226 VEX_LEN_0F2D_P_3): Delete.
1227 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1228 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1229 (prefix_table): ... here.
1231 2019-06-27 Jan Beulich <jbeulich@suse.com>
1233 * i386-dis.c (Iq): Delete.
1235 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1237 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1238 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1239 (OP_E_memory): Also honor needindex when deciding whether an
1240 address size prefix needs printing.
1241 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1243 2019-06-26 Jim Wilson <jimw@sifive.com>
1246 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1247 Set info->display_endian to info->endian_code.
1249 2019-06-25 Jan Beulich <jbeulich@suse.com>
1251 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1252 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1253 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1254 OPERAND_TYPE_ACC64 entries.
1255 * i386-init.h: Re-generate.
1257 2019-06-25 Jan Beulich <jbeulich@suse.com>
1259 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1261 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1263 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1265 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1266 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1268 2019-06-25 Jan Beulich <jbeulich@suse.com>
1270 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1273 2019-06-25 Jan Beulich <jbeulich@suse.com>
1275 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1276 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1278 * i386-opc.tbl (movnti): Add IgnoreSize.
1279 * i386-tbl.h: Re-generate.
1281 2019-06-25 Jan Beulich <jbeulich@suse.com>
1283 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1284 * i386-tbl.h: Re-generate.
1286 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1288 * i386-dis-evex.h: Break into ...
1289 * i386-dis-evex-len.h: New file.
1290 * i386-dis-evex-mod.h: Likewise.
1291 * i386-dis-evex-prefix.h: Likewise.
1292 * i386-dis-evex-reg.h: Likewise.
1293 * i386-dis-evex-w.h: Likewise.
1294 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1295 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1296 i386-dis-evex-mod.h.
1298 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1301 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1302 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1304 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1305 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1306 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1307 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1308 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1309 EVEX_LEN_0F385B_P_2_W_1.
1310 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1311 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1312 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1313 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1314 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1315 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1316 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1317 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1318 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1319 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1321 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1324 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1325 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1326 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1327 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1328 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1329 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1330 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1331 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1332 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1333 EVEX_LEN_0F3A43_P_2_W_1.
1334 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1335 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1336 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1337 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1338 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1339 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1340 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1341 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1342 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1343 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1344 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1345 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1347 2019-06-14 Nick Clifton <nickc@redhat.com>
1349 * po/fr.po; Updated French translation.
1351 2019-06-13 Stafford Horne <shorne@gmail.com>
1353 * or1k-asm.c: Regenerated.
1354 * or1k-desc.c: Regenerated.
1355 * or1k-desc.h: Regenerated.
1356 * or1k-dis.c: Regenerated.
1357 * or1k-ibld.c: Regenerated.
1358 * or1k-opc.c: Regenerated.
1359 * or1k-opc.h: Regenerated.
1360 * or1k-opinst.c: Regenerated.
1362 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1364 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1366 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1369 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1370 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1371 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1372 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1373 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1374 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1375 EVEX_LEN_0F3A1B_P_2_W_1.
1376 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1377 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1378 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1379 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1380 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1381 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1382 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1383 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1385 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1388 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1389 EVEX.vvvv when disassembling VEX and EVEX instructions.
1390 (OP_VEX): Set vex.register_specifier to 0 after readding
1391 vex.register_specifier.
1392 (OP_Vex_2src_1): Likewise.
1393 (OP_Vex_2src_2): Likewise.
1394 (OP_LWP_E): Likewise.
1395 (OP_EX_Vex): Don't check vex.register_specifier.
1396 (OP_XMM_Vex): Likewise.
1398 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1399 Lili Cui <lili.cui@intel.com>
1401 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1402 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1404 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1405 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1406 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1407 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1408 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1409 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1410 * i386-init.h: Regenerated.
1411 * i386-tbl.h: Likewise.
1413 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1414 Lili Cui <lili.cui@intel.com>
1416 * doc/c-i386.texi: Document enqcmd.
1417 * testsuite/gas/i386/enqcmd-intel.d: New file.
1418 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1419 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1420 * testsuite/gas/i386/enqcmd.d: Likewise.
1421 * testsuite/gas/i386/enqcmd.s: Likewise.
1422 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1423 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1424 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1425 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1426 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1427 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1428 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1431 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1433 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1435 2019-06-03 Alan Modra <amodra@gmail.com>
1437 * ppc-dis.c (prefix_opcd_indices): Correct size.
1439 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1442 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1444 * i386-tbl.h: Regenerated.
1446 2019-05-24 Alan Modra <amodra@gmail.com>
1448 * po/POTFILES.in: Regenerate.
1450 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1451 Alan Modra <amodra@gmail.com>
1453 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1454 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1455 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1456 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1457 XTOP>): Define and add entries.
1458 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1459 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1460 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1461 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1463 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1464 Alan Modra <amodra@gmail.com>
1466 * ppc-dis.c (ppc_opts): Add "future" entry.
1467 (PREFIX_OPCD_SEGS): Define.
1468 (prefix_opcd_indices): New array.
1469 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1470 (lookup_prefix): New function.
1471 (print_insn_powerpc): Handle 64-bit prefix instructions.
1472 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1473 (PMRR, POWERXX): Define.
1474 (prefix_opcodes): New instruction table.
1475 (prefix_num_opcodes): New constant.
1477 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1479 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1480 * configure: Regenerated.
1481 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1483 (HFILES): Add bpf-desc.h and bpf-opc.h.
1484 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1485 bpf-ibld.c and bpf-opc.c.
1487 * Makefile.in: Regenerated.
1488 * disassemble.c (ARCH_bpf): Define.
1489 (disassembler): Add case for bfd_arch_bpf.
1490 (disassemble_init_for_target): Likewise.
1491 (enum epbf_isa_attr): Define.
1492 * disassemble.h: extern print_insn_bpf.
1493 * bpf-asm.c: Generated.
1494 * bpf-opc.h: Likewise.
1495 * bpf-opc.c: Likewise.
1496 * bpf-ibld.c: Likewise.
1497 * bpf-dis.c: Likewise.
1498 * bpf-desc.h: Likewise.
1499 * bpf-desc.c: Likewise.
1501 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1503 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1504 and VMSR with the new operands.
1506 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1508 * arm-dis.c (enum mve_instructions): New enum
1509 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1511 (mve_opcodes): New instructions as above.
1512 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1514 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1516 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1518 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1519 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1520 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1521 uqshl, urshrl and urshr.
1522 (is_mve_okay_in_it): Add new instructions to TRUE list.
1523 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1524 (print_insn_mve): Updated to accept new %j,
1525 %<bitfield>m and %<bitfield>n patterns.
1527 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1529 * mips-opc.c (mips_builtin_opcodes): Change source register
1530 constraint for DAUI.
1532 2019-05-20 Nick Clifton <nickc@redhat.com>
1534 * po/fr.po: Updated French translation.
1536 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1537 Michael Collison <michael.collison@arm.com>
1539 * arm-dis.c (thumb32_opcodes): Add new instructions.
1540 (enum mve_instructions): Likewise.
1541 (enum mve_undefined): Add new reasons.
1542 (is_mve_encoding_conflict): Handle new instructions.
1543 (is_mve_undefined): Likewise.
1544 (is_mve_unpredictable): Likewise.
1545 (print_mve_undefined): Likewise.
1546 (print_mve_size): Likewise.
1548 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1549 Michael Collison <michael.collison@arm.com>
1551 * arm-dis.c (thumb32_opcodes): Add new instructions.
1552 (enum mve_instructions): Likewise.
1553 (is_mve_encoding_conflict): Handle new instructions.
1554 (is_mve_undefined): Likewise.
1555 (is_mve_unpredictable): Likewise.
1556 (print_mve_size): Likewise.
1558 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1559 Michael Collison <michael.collison@arm.com>
1561 * arm-dis.c (thumb32_opcodes): Add new instructions.
1562 (enum mve_instructions): Likewise.
1563 (is_mve_encoding_conflict): Likewise.
1564 (is_mve_unpredictable): Likewise.
1565 (print_mve_size): Likewise.
1567 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1568 Michael Collison <michael.collison@arm.com>
1570 * arm-dis.c (thumb32_opcodes): Add new instructions.
1571 (enum mve_instructions): Likewise.
1572 (is_mve_encoding_conflict): Handle new instructions.
1573 (is_mve_undefined): Likewise.
1574 (is_mve_unpredictable): Likewise.
1575 (print_mve_size): Likewise.
1577 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1578 Michael Collison <michael.collison@arm.com>
1580 * arm-dis.c (thumb32_opcodes): Add new instructions.
1581 (enum mve_instructions): Likewise.
1582 (is_mve_encoding_conflict): Handle new instructions.
1583 (is_mve_undefined): Likewise.
1584 (is_mve_unpredictable): Likewise.
1585 (print_mve_size): Likewise.
1586 (print_insn_mve): Likewise.
1588 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1589 Michael Collison <michael.collison@arm.com>
1591 * arm-dis.c (thumb32_opcodes): Add new instructions.
1592 (print_insn_thumb32): Handle new instructions.
1594 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1595 Michael Collison <michael.collison@arm.com>
1597 * arm-dis.c (enum mve_instructions): Add new instructions.
1598 (enum mve_undefined): Add new reasons.
1599 (is_mve_encoding_conflict): Handle new instructions.
1600 (is_mve_undefined): Likewise.
1601 (is_mve_unpredictable): Likewise.
1602 (print_mve_undefined): Likewise.
1603 (print_mve_size): Likewise.
1604 (print_mve_shift_n): Likewise.
1605 (print_insn_mve): Likewise.
1607 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1608 Michael Collison <michael.collison@arm.com>
1610 * arm-dis.c (enum mve_instructions): Add new instructions.
1611 (is_mve_encoding_conflict): Handle new instructions.
1612 (is_mve_unpredictable): Likewise.
1613 (print_mve_rotate): Likewise.
1614 (print_mve_size): Likewise.
1615 (print_insn_mve): Likewise.
1617 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1618 Michael Collison <michael.collison@arm.com>
1620 * arm-dis.c (enum mve_instructions): Add new instructions.
1621 (is_mve_encoding_conflict): Handle new instructions.
1622 (is_mve_unpredictable): Likewise.
1623 (print_mve_size): Likewise.
1624 (print_insn_mve): Likewise.
1626 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1627 Michael Collison <michael.collison@arm.com>
1629 * arm-dis.c (enum mve_instructions): Add new instructions.
1630 (enum mve_undefined): Add new reasons.
1631 (is_mve_encoding_conflict): Handle new instructions.
1632 (is_mve_undefined): Likewise.
1633 (is_mve_unpredictable): Likewise.
1634 (print_mve_undefined): Likewise.
1635 (print_mve_size): Likewise.
1636 (print_insn_mve): Likewise.
1638 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1639 Michael Collison <michael.collison@arm.com>
1641 * arm-dis.c (enum mve_instructions): Add new instructions.
1642 (is_mve_encoding_conflict): Handle new instructions.
1643 (is_mve_undefined): Likewise.
1644 (is_mve_unpredictable): Likewise.
1645 (print_mve_size): Likewise.
1646 (print_insn_mve): Likewise.
1648 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1649 Michael Collison <michael.collison@arm.com>
1651 * arm-dis.c (enum mve_instructions): Add new instructions.
1652 (enum mve_unpredictable): Add new reasons.
1653 (enum mve_undefined): Likewise.
1654 (is_mve_okay_in_it): Handle new isntructions.
1655 (is_mve_encoding_conflict): Likewise.
1656 (is_mve_undefined): Likewise.
1657 (is_mve_unpredictable): Likewise.
1658 (print_mve_vmov_index): Likewise.
1659 (print_simd_imm8): Likewise.
1660 (print_mve_undefined): Likewise.
1661 (print_mve_unpredictable): Likewise.
1662 (print_mve_size): Likewise.
1663 (print_insn_mve): Likewise.
1665 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1666 Michael Collison <michael.collison@arm.com>
1668 * arm-dis.c (enum mve_instructions): Add new instructions.
1669 (enum mve_unpredictable): Add new reasons.
1670 (enum mve_undefined): Likewise.
1671 (is_mve_encoding_conflict): Handle new instructions.
1672 (is_mve_undefined): Likewise.
1673 (is_mve_unpredictable): Likewise.
1674 (print_mve_undefined): Likewise.
1675 (print_mve_unpredictable): Likewise.
1676 (print_mve_rounding_mode): Likewise.
1677 (print_mve_vcvt_size): Likewise.
1678 (print_mve_size): Likewise.
1679 (print_insn_mve): Likewise.
1681 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1682 Michael Collison <michael.collison@arm.com>
1684 * arm-dis.c (enum mve_instructions): Add new instructions.
1685 (enum mve_unpredictable): Add new reasons.
1686 (enum mve_undefined): Likewise.
1687 (is_mve_undefined): Handle new instructions.
1688 (is_mve_unpredictable): Likewise.
1689 (print_mve_undefined): Likewise.
1690 (print_mve_unpredictable): Likewise.
1691 (print_mve_size): Likewise.
1692 (print_insn_mve): Likewise.
1694 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1695 Michael Collison <michael.collison@arm.com>
1697 * arm-dis.c (enum mve_instructions): Add new instructions.
1698 (enum mve_undefined): Add new reasons.
1699 (insns): Add new instructions.
1700 (is_mve_encoding_conflict):
1701 (print_mve_vld_str_addr): New print function.
1702 (is_mve_undefined): Handle new instructions.
1703 (is_mve_unpredictable): Likewise.
1704 (print_mve_undefined): Likewise.
1705 (print_mve_size): Likewise.
1706 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1707 (print_insn_mve): Handle new operands.
1709 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1710 Michael Collison <michael.collison@arm.com>
1712 * arm-dis.c (enum mve_instructions): Add new instructions.
1713 (enum mve_unpredictable): Add new reasons.
1714 (is_mve_encoding_conflict): Handle new instructions.
1715 (is_mve_unpredictable): Likewise.
1716 (mve_opcodes): Add new instructions.
1717 (print_mve_unpredictable): Handle new reasons.
1718 (print_mve_register_blocks): New print function.
1719 (print_mve_size): Handle new instructions.
1720 (print_insn_mve): Likewise.
1722 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1723 Michael Collison <michael.collison@arm.com>
1725 * arm-dis.c (enum mve_instructions): Add new instructions.
1726 (enum mve_unpredictable): Add new reasons.
1727 (enum mve_undefined): Likewise.
1728 (is_mve_encoding_conflict): Handle new instructions.
1729 (is_mve_undefined): Likewise.
1730 (is_mve_unpredictable): Likewise.
1731 (coprocessor_opcodes): Move NEON VDUP from here...
1732 (neon_opcodes): ... to here.
1733 (mve_opcodes): Add new instructions.
1734 (print_mve_undefined): Handle new reasons.
1735 (print_mve_unpredictable): Likewise.
1736 (print_mve_size): Handle new instructions.
1737 (print_insn_neon): Handle vdup.
1738 (print_insn_mve): Handle new operands.
1740 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1741 Michael Collison <michael.collison@arm.com>
1743 * arm-dis.c (enum mve_instructions): Add new instructions.
1744 (enum mve_unpredictable): Add new values.
1745 (mve_opcodes): Add new instructions.
1746 (vec_condnames): New array with vector conditions.
1747 (mve_predicatenames): New array with predicate suffixes.
1748 (mve_vec_sizename): New array with vector sizes.
1749 (enum vpt_pred_state): New enum with vector predication states.
1750 (struct vpt_block): New struct type for vpt blocks.
1751 (vpt_block_state): Global struct to keep track of state.
1752 (mve_extract_pred_mask): New helper function.
1753 (num_instructions_vpt_block): Likewise.
1754 (mark_outside_vpt_block): Likewise.
1755 (mark_inside_vpt_block): Likewise.
1756 (invert_next_predicate_state): Likewise.
1757 (update_next_predicate_state): Likewise.
1758 (update_vpt_block_state): Likewise.
1759 (is_vpt_instruction): Likewise.
1760 (is_mve_encoding_conflict): Add entries for new instructions.
1761 (is_mve_unpredictable): Likewise.
1762 (print_mve_unpredictable): Handle new cases.
1763 (print_instruction_predicate): Likewise.
1764 (print_mve_size): New function.
1765 (print_vec_condition): New function.
1766 (print_insn_mve): Handle vpt blocks and new print operands.
1768 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1770 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1771 8, 14 and 15 for Armv8.1-M Mainline.
1773 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1774 Michael Collison <michael.collison@arm.com>
1776 * arm-dis.c (enum mve_instructions): New enum.
1777 (enum mve_unpredictable): Likewise.
1778 (enum mve_undefined): Likewise.
1779 (struct mopcode32): New struct.
1780 (is_mve_okay_in_it): New function.
1781 (is_mve_architecture): Likewise.
1782 (arm_decode_field): Likewise.
1783 (arm_decode_field_multiple): Likewise.
1784 (is_mve_encoding_conflict): Likewise.
1785 (is_mve_undefined): Likewise.
1786 (is_mve_unpredictable): Likewise.
1787 (print_mve_undefined): Likewise.
1788 (print_mve_unpredictable): Likewise.
1789 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1790 (print_insn_mve): New function.
1791 (print_insn_thumb32): Handle MVE architecture.
1792 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1794 2019-05-10 Nick Clifton <nickc@redhat.com>
1797 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1798 end of the table prematurely.
1800 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1802 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1805 2019-05-11 Alan Modra <amodra@gmail.com>
1807 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1808 when -Mraw is in effect.
1810 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1812 * aarch64-dis-2.c: Regenerate.
1813 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1814 (OP_SVE_BBB): New variant set.
1815 (OP_SVE_DDDD): New variant set.
1816 (OP_SVE_HHH): New variant set.
1817 (OP_SVE_HHHU): New variant set.
1818 (OP_SVE_SSS): New variant set.
1819 (OP_SVE_SSSU): New variant set.
1820 (OP_SVE_SHH): New variant set.
1821 (OP_SVE_SBBU): New variant set.
1822 (OP_SVE_DSS): New variant set.
1823 (OP_SVE_DHHU): New variant set.
1824 (OP_SVE_VMV_HSD_BHS): New variant set.
1825 (OP_SVE_VVU_HSD_BHS): New variant set.
1826 (OP_SVE_VVVU_SD_BH): New variant set.
1827 (OP_SVE_VVVU_BHSD): New variant set.
1828 (OP_SVE_VVV_QHD_DBS): New variant set.
1829 (OP_SVE_VVV_HSD_BHS): New variant set.
1830 (OP_SVE_VVV_HSD_BHS2): New variant set.
1831 (OP_SVE_VVV_BHS_HSD): New variant set.
1832 (OP_SVE_VV_BHS_HSD): New variant set.
1833 (OP_SVE_VVV_SD): New variant set.
1834 (OP_SVE_VVU_BHS_HSD): New variant set.
1835 (OP_SVE_VZVV_SD): New variant set.
1836 (OP_SVE_VZVV_BH): New variant set.
1837 (OP_SVE_VZV_SD): New variant set.
1838 (aarch64_opcode_table): Add sve2 instructions.
1840 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1842 * aarch64-asm-2.c: Regenerated.
1843 * aarch64-dis-2.c: Regenerated.
1844 * aarch64-opc-2.c: Regenerated.
1845 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1846 for SVE_SHLIMM_UNPRED_22.
1847 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1848 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1851 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1853 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1854 sve_size_tsz_bhs iclass encode.
1855 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1856 sve_size_tsz_bhs iclass decode.
1858 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1860 * aarch64-asm-2.c: Regenerated.
1861 * aarch64-dis-2.c: Regenerated.
1862 * aarch64-opc-2.c: Regenerated.
1863 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1864 for SVE_Zm4_11_INDEX.
1865 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1866 (fields): Handle SVE_i2h field.
1867 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1868 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1870 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1872 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1873 sve_shift_tsz_bhsd iclass encode.
1874 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1875 sve_shift_tsz_bhsd iclass decode.
1877 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1879 * aarch64-asm-2.c: Regenerated.
1880 * aarch64-dis-2.c: Regenerated.
1881 * aarch64-opc-2.c: Regenerated.
1882 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1883 (aarch64_encode_variant_using_iclass): Handle
1884 sve_shift_tsz_hsd iclass encode.
1885 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1886 sve_shift_tsz_hsd iclass decode.
1887 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1888 for SVE_SHRIMM_UNPRED_22.
1889 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1890 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1893 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1895 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1896 sve_size_013 iclass encode.
1897 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1898 sve_size_013 iclass decode.
1900 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1902 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1903 sve_size_bh iclass encode.
1904 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1905 sve_size_bh iclass decode.
1907 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1909 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1910 sve_size_sd2 iclass encode.
1911 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1912 sve_size_sd2 iclass decode.
1913 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1914 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1916 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1918 * aarch64-asm-2.c: Regenerated.
1919 * aarch64-dis-2.c: Regenerated.
1920 * aarch64-opc-2.c: Regenerated.
1921 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1923 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1924 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1926 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1928 * aarch64-asm-2.c: Regenerated.
1929 * aarch64-dis-2.c: Regenerated.
1930 * aarch64-opc-2.c: Regenerated.
1931 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1932 for SVE_Zm3_11_INDEX.
1933 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1934 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1935 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1937 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1939 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1941 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1942 sve_size_hsd2 iclass encode.
1943 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1944 sve_size_hsd2 iclass decode.
1945 * aarch64-opc.c (fields): Handle SVE_size field.
1946 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1948 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1950 * aarch64-asm-2.c: Regenerated.
1951 * aarch64-dis-2.c: Regenerated.
1952 * aarch64-opc-2.c: Regenerated.
1953 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1955 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1956 (fields): Handle SVE_rot3 field.
1957 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1958 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1960 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1962 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1965 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1968 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1969 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1970 aarch64_feature_sve2bitperm): New feature sets.
1971 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1972 for feature set addresses.
1973 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1974 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1976 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1977 Faraz Shahbazker <fshahbazker@wavecomp.com>
1979 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1980 argument and set ASE_EVA_R6 appropriately.
1981 (set_default_mips_dis_options): Pass ISA to above.
1982 (parse_mips_dis_option): Likewise.
1983 * mips-opc.c (EVAR6): New macro.
1984 (mips_builtin_opcodes): Add llwpe, scwpe.
1986 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1988 * aarch64-asm-2.c: Regenerated.
1989 * aarch64-dis-2.c: Regenerated.
1990 * aarch64-opc-2.c: Regenerated.
1991 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1992 AARCH64_OPND_TME_UIMM16.
1993 (aarch64_print_operand): Likewise.
1994 * aarch64-tbl.h (QL_IMM_NIL): New.
1997 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1999 2019-04-29 John Darrington <john@darrington.wattle.id.au>
2001 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2003 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2004 Faraz Shahbazker <fshahbazker@wavecomp.com>
2006 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2008 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2010 * s12z-opc.h: Add extern "C" bracketing to help
2011 users who wish to use this interface in c++ code.
2013 2019-04-24 John Darrington <john@darrington.wattle.id.au>
2015 * s12z-opc.c (bm_decode): Handle bit map operations with the
2018 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2020 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2021 specifier. Add entries for VLDR and VSTR of system registers.
2022 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2023 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2024 of %J and %K format specifier.
2026 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2028 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2029 Add new entries for VSCCLRM instruction.
2030 (print_insn_coprocessor): Handle new %C format control code.
2032 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2034 * arm-dis.c (enum isa): New enum.
2035 (struct sopcode32): New structure.
2036 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2037 set isa field of all current entries to ANY.
2038 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2039 Only match an entry if its isa field allows the current mode.
2041 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2043 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2045 (print_insn_thumb32): Add logic to print %n CLRM register list.
2047 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2049 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2052 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2054 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2055 (print_insn_thumb32): Edit the switch case for %Z.
2057 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2059 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2061 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2063 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2065 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2067 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2069 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2071 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2072 Arm register with r13 and r15 unpredictable.
2073 (thumb32_opcodes): New instructions for bfx and bflx.
2075 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2077 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2079 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2081 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2083 2019-04-15 Sudakshina Das <sudi.das@arm.com>
2085 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2087 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2089 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2091 2019-04-12 John Darrington <john@darrington.wattle.id.au>
2093 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2094 "optr". ("operator" is a reserved word in c++).
2096 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2098 * aarch64-opc.c (aarch64_print_operand): Add case for
2100 (verify_constraints): Likewise.
2101 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2102 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2103 to accept Rt|SP as first operand.
2104 (AARCH64_OPERANDS): Add new Rt_SP.
2105 * aarch64-asm-2.c: Regenerated.
2106 * aarch64-dis-2.c: Regenerated.
2107 * aarch64-opc-2.c: Regenerated.
2109 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2111 * aarch64-asm-2.c: Regenerated.
2112 * aarch64-dis-2.c: Likewise.
2113 * aarch64-opc-2.c: Likewise.
2114 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2116 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2118 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2120 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2122 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2123 * i386-init.h: Regenerated.
2125 2019-04-07 Alan Modra <amodra@gmail.com>
2127 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2128 op_separator to control printing of spaces, comma and parens
2129 rather than need_comma, need_paren and spaces vars.
2131 2019-04-07 Alan Modra <amodra@gmail.com>
2134 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2135 (print_insn_neon, print_insn_arm): Likewise.
2137 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2139 * i386-dis-evex.h (evex_table): Updated to support BF16
2141 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2142 and EVEX_W_0F3872_P_3.
2143 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2144 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2145 * i386-opc.h (enum): Add CpuAVX512_BF16.
2146 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2147 * i386-opc.tbl: Add AVX512 BF16 instructions.
2148 * i386-init.h: Regenerated.
2149 * i386-tbl.h: Likewise.
2151 2019-04-05 Alan Modra <amodra@gmail.com>
2153 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2154 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2155 to favour printing of "-" branch hint when using the "y" bit.
2156 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2158 2019-04-05 Alan Modra <amodra@gmail.com>
2160 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2161 opcode until first operand is output.
2163 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2166 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2167 (valid_bo_post_v2): Add support for 'at' branch hints.
2168 (insert_bo): Only error on branch on ctr.
2169 (get_bo_hint_mask): New function.
2170 (insert_boe): Add new 'branch_taken' formal argument. Add support
2171 for inserting 'at' branch hints.
2172 (extract_boe): Add new 'branch_taken' formal argument. Add support
2173 for extracting 'at' branch hints.
2174 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2175 (BOE): Delete operand.
2176 (BOM, BOP): New operands.
2178 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2179 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2180 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2181 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2182 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2183 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2184 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2185 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2186 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2187 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2188 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2189 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2190 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2191 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2192 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2193 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2194 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2195 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2196 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2197 bttarl+>: New extended mnemonics.
2199 2019-03-28 Alan Modra <amodra@gmail.com>
2202 * ppc-opc.c (BTF): Define.
2203 (powerpc_opcodes): Use for mtfsb*.
2204 * ppc-dis.c (print_insn_powerpc): Print fields with both
2205 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2207 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2209 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2210 (mapping_symbol_for_insn): Implement new algorithm.
2211 (print_insn): Remove duplicate code.
2213 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2215 * aarch64-dis.c (print_insn_aarch64):
2218 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2220 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2223 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2225 * aarch64-dis.c (last_stop_offset): New.
2226 (print_insn_aarch64): Use stop_offset.
2228 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2231 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2233 * i386-init.h: Regenerated.
2235 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2238 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2239 vmovdqu16, vmovdqu32 and vmovdqu64.
2240 * i386-tbl.h: Regenerated.
2242 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2244 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2245 from vstrszb, vstrszh, and vstrszf.
2247 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2249 * s390-opc.txt: Add instruction descriptions.
2251 2019-02-08 Jim Wilson <jimw@sifive.com>
2253 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2256 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2258 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2260 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2263 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2264 * aarch64-opc.c (verify_elem_sd): New.
2265 (fields): Add FLD_sz entr.
2266 * aarch64-tbl.h (_SIMD_INSN): New.
2267 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2268 fmulx scalar and vector by element isns.
2270 2019-02-07 Nick Clifton <nickc@redhat.com>
2272 * po/sv.po: Updated Swedish translation.
2274 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2276 * s390-mkopc.c (main): Accept arch13 as cpu string.
2277 * s390-opc.c: Add new instruction formats and instruction opcode
2279 * s390-opc.txt: Add new arch13 instructions.
2281 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2283 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2284 (aarch64_opcode): Change encoding for stg, stzg
2286 * aarch64-asm-2.c: Regenerated.
2287 * aarch64-dis-2.c: Regenerated.
2288 * aarch64-opc-2.c: Regenerated.
2290 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2292 * aarch64-asm-2.c: Regenerated.
2293 * aarch64-dis-2.c: Likewise.
2294 * aarch64-opc-2.c: Likewise.
2295 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2297 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2298 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2300 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2301 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2302 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2303 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2304 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2305 case for ldstgv_indexed.
2306 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2307 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2308 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2309 * aarch64-asm-2.c: Regenerated.
2310 * aarch64-dis-2.c: Regenerated.
2311 * aarch64-opc-2.c: Regenerated.
2313 2019-01-23 Nick Clifton <nickc@redhat.com>
2315 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2317 2019-01-21 Nick Clifton <nickc@redhat.com>
2319 * po/de.po: Updated German translation.
2320 * po/uk.po: Updated Ukranian translation.
2322 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2323 * mips-dis.c (mips_arch_choices): Fix typo in
2324 gs464, gs464e and gs264e descriptors.
2326 2019-01-19 Nick Clifton <nickc@redhat.com>
2328 * configure: Regenerate.
2329 * po/opcodes.pot: Regenerate.
2331 2018-06-24 Nick Clifton <nickc@redhat.com>
2333 2.32 branch created.
2335 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2337 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2339 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2342 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2344 * configure: Regenerate.
2346 2019-01-07 Alan Modra <amodra@gmail.com>
2348 * configure: Regenerate.
2349 * po/POTFILES.in: Regenerate.
2351 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2353 * s12z-opc.c: New file.
2354 * s12z-opc.h: New file.
2355 * s12z-dis.c: Removed all code not directly related to display
2356 of instructions. Used the interface provided by the new files
2358 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2359 * Makefile.in: Regenerate.
2360 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2361 * configure: Regenerate.
2363 2019-01-01 Alan Modra <amodra@gmail.com>
2365 Update year range in copyright notice of all files.
2367 For older changes see ChangeLog-2018
2369 Copyright (C) 2019 Free Software Foundation, Inc.
2371 Copying and distribution of this file, with or without modification,
2372 are permitted in any medium without royalty provided the copyright
2373 notice and this notice are preserved.
2379 version-control: never