opcodes/ChangeLog

   1 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
   4
   5 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
   6
   7         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
   8
   9 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
  10
  11         * ppc-opc.c: Add comment accidentally removed by old commit.
  12         (MTMSRD_L): Delete.
  13
  14 2015-06-04  Nick Clifton  <nickc@redhat.com>
  15
  16         PR 18474
  17         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
  18
  19 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  20
  21         * arm-dis.c (arm_opcodes): Add "setpan".
  22         (thumb_opcodes): Add "setpan".
  23
  24 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  25
  26         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
  27         macros.
  28
  29 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  30
  31         * aarch64-tbl.h (aarch64_feature_rdma): New.
  32         (RDMA): New.
  33         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  34         * aarch64-asm-2.c: Regenerate.
  35         * aarch64-dis-2.c: Regenerate.
  36         * aarch64-opc-2.c: Regenerate.
  37
  38 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
  39
  40         * aarch64-tbl.h (aarch64_feature_lor): New.
  41         (LOR): New.
  42         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  43         "stllrb", "stllrh".
  44         * aarch64-asm-2.c: Regenerate.
  45         * aarch64-dis-2.c: Regenerate.
  46         * aarch64-opc-2.c: Regenerate.
  47
  48 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
  49
  50         * aarch64-opc.c (F_ARCHEXT): New.
  51         (aarch64_sys_regs): Add "pan".
  52         (aarch64_sys_reg_supported_p): New.
  53         (aarch64_pstatefields): Add "pan".
  54         (aarch64_pstatefield_supported_p): New.
  55
  56 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-tbl.h: Regenerate.
  59
  60 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-dis.c (print_insn): Swap rounding mode specifier and
  63         general purpose register in Intel mode.
  64
  65 2015-06-01  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
  68         * i386-tbl.h: Regenerate.
  69
  70 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
  73         * i386-init.h: Regenerated.
  74
  75 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         PR binutis/18386
  78         * i386-dis.c: Add comments for '@'.
  79         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
  80         (enum x86_64_isa): New.
  81         (isa64): Likewise.
  82         (print_i386_disassembler_options): Add amd64 and intel64.
  83         (print_insn): Handle amd64 and intel64.
  84         (putop): Handle '@'.
  85         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
  86         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
  87         * i386-opc.h (AMD64): New.
  88         (CpuIntel64): Likewise.
  89         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
  90         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
  91         Mark direct call/jmp without Disp16|Disp32 as Intel64.
  92         * i386-init.h: Regenerated.
  93         * i386-tbl.h: Likewise.
  94
  95 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
  96
  97         * ppc-opc.c (IH) New define.
  98         (powerpc_opcodes) <wait>: Do not enable for POWER7.
  99         <tlbie>: Add RS operand for POWER7.
 100         <slbia>: Add IH operand for POWER6.
 101
 102 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 103
 104         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 105         direct branch.
 106         (jmp): Likewise.
 107         * i386-tbl.h: Regenerated.
 108
 109 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 110
 111         * configure.ac: Support bfd_iamcu_arch.
 112         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 113         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 114         CPU_IAMCU_COMPAT_FLAGS.
 115         (cpu_flags): Add CpuIAMCU.
 116         * i386-opc.h (CpuIAMCU): New.
 117         (i386_cpu_flags): Add cpuiamcu.
 118         * configure: Regenerated.
 119         * i386-init.h: Likewise.
 120         * i386-tbl.h: Likewise.
 121
 122 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 123
 124         PR binutis/18386
 125         * i386-dis.c (X86_64_E8): New.
 126         (X86_64_E9): Likewise.
 127         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 128         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 129         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 130         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 131         (putop): Handle '^'.
 132         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 133         REX_W.
 134
 135 2015-04-30  DJ Delorie  <dj@redhat.com>
 136
 137         * disassemble.c (disassembler): Choose suitable disassembler based
 138         on E_ABI.
 139         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 140         it to decode mul/div insns.
 141         * rl78-decode.c: Regenerate.
 142         * rl78-dis.c (print_insn_rl78): Rename to...
 143         (print_insn_rl78_common): ...this, take ISA parameter.
 144         (print_insn_rl78): New.
 145         (print_insn_rl78_g10): New.
 146         (print_insn_rl78_g13): New.
 147         (print_insn_rl78_g14): New.
 148         (rl78_get_disassembler): New.
 149
 150 2015-04-29  Nick Clifton  <nickc@redhat.com>
 151
 152         * po/fr.po: Updated French translation.
 153
 154 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 155
 156         * ppc-opc.c (DCBT_EO): New define.
 157         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 158         <lharx>: Likewise.
 159         <stbcx.>: Likewise.
 160         <sthcx.>: Likewise.
 161         <waitrsv>: Do not enable for POWER7 and later.
 162         <waitimpl>: Likewise.
 163         <dcbt>: Default to the two operand form of the instruction for all
 164         "old" cpus.  For "new" cpus, use the operand ordering that matches
 165         whether the cpu is server or embedded.
 166         <dcbtst>: Likewise.
 167
 168 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 169
 170         * s390-opc.c: New instruction type VV0UU2.
 171         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 172         and WFC.
 173
 174 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 177         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 178         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 179         (vfpclasspd, vfpclassps): Add %XZ.
 180
 181 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 182
 183         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 184         (PREFIX_UD_REPZ): Likewise.
 185         (PREFIX_UD_REPNZ): Likewise.
 186         (PREFIX_UD_DATA): Likewise.
 187         (PREFIX_UD_ADDR): Likewise.
 188         (PREFIX_UD_LOCK): Likewise.
 189
 190 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 191
 192         * i386-dis.c (prefix_requirement): Removed.
 193         (print_insn): Don't set prefix_requirement.  Check
 194         dp->prefix_requirement instead of prefix_requirement.
 195
 196 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 197
 198         PR binutils/17898
 199         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 200         (PREFIX_MOD_0_0FC7_REG_6): This.
 201         (PREFIX_MOD_3_0FC7_REG_6): New.
 202         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 203         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 204         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 205         PREFIX_MOD_3_0FC7_REG_7.
 206         (mod_table): Replace PREFIX_0FC7_REG_6 with
 207         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 208         PREFIX_MOD_3_0FC7_REG_7.
 209
 210 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 213         (PREFIX_MANDATORY_REPNZ): Likewise.
 214         (PREFIX_MANDATORY_DATA): Likewise.
 215         (PREFIX_MANDATORY_ADDR): Likewise.
 216         (PREFIX_MANDATORY_LOCK): Likewise.
 217         (PREFIX_MANDATORY): Likewise.
 218         (PREFIX_UD_SHIFT): Set to 8
 219         (PREFIX_UD_REPZ): Updated.
 220         (PREFIX_UD_REPNZ): Likewise.
 221         (PREFIX_UD_DATA): Likewise.
 222         (PREFIX_UD_ADDR): Likewise.
 223         (PREFIX_UD_LOCK): Likewise.
 224         (PREFIX_IGNORED_SHIFT): New.
 225         (PREFIX_IGNORED_REPZ): Likewise.
 226         (PREFIX_IGNORED_REPNZ): Likewise.
 227         (PREFIX_IGNORED_DATA): Likewise.
 228         (PREFIX_IGNORED_ADDR): Likewise.
 229         (PREFIX_IGNORED_LOCK): Likewise.
 230         (PREFIX_OPCODE): Likewise.
 231         (PREFIX_IGNORED): Likewise.
 232         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 233         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 234         (three_byte_table): Likewise.
 235         (mod_table): Likewise.
 236         (mandatory_prefix): Renamed to ...
 237         (prefix_requirement): This.
 238         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 239         Update PREFIX_90 entry.
 240         (get_valid_dis386): Check prefix_requirement to see if a prefix
 241         should be ignored.
 242         (print_insn): Replace mandatory_prefix with prefix_requirement.
 243
 244 2015-04-15  Renlin Li  <renlin.li@arm.com>
 245
 246         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 247         use it for ssat and ssat16.
 248         (print_insn_thumb32): Add handle case for 'D' control code.
 249
 250 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 251             H.J. Lu  <hongjiu.lu@intel.com>
 252
 253         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 254         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 255         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 256         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 257         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 258         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 259         Fill prefix_requirement field.
 260         (struct dis386): Add prefix_requirement field.
 261         (dis386): Fill prefix_requirement field.
 262         (dis386_twobyte): Ditto.
 263         (twobyte_has_mandatory_prefix_: Remove.
 264         (reg_table): Fill prefix_requirement field.
 265         (prefix_table): Ditto.
 266         (x86_64_table): Ditto.
 267         (three_byte_table): Ditto.
 268         (xop_table): Ditto.
 269         (vex_table): Ditto.
 270         (vex_len_table): Ditto.
 271         (vex_w_table): Ditto.
 272         (mod_table): Ditto.
 273         (bad_opcode): Ditto.
 274         (print_insn): Use prefix_requirement.
 275         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 276         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 277         (float_reg): Ditto.
 278
 279 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 280
 281         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 282
 283 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         * Makefile.in: Regenerated.
 286
 287 2015-03-25  Anton Blanchard  <anton@samba.org>
 288
 289         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 290         powerpc_opcd_indices and vle_opcd_indices once.
 291
 292 2015-03-25  Anton Blanchard  <anton@samba.org>
 293
 294         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 295
 296 2015-03-24  Terry Guo  <terry.guo@arm.com>
 297
 298         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 299         (opcode16): Likewise.
 300         (coprocessor_opcodes): Replace bit with feature struct.
 301         (neon_opcodes): Likewise.
 302         (arm_opcodes): Likewise.
 303         (thumb_opcodes): Likewise.
 304         (thumb32_opcodes): Likewise.
 305         (print_insn_coprocessor): Likewise.
 306         (print_insn_arm): Likewise.
 307         (select_arm_features): Follow new feature struct.
 308
 309 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 310
 311         * i386-dis.c (rm_table): Add clzero.
 312         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 313         Add CPU_CLZERO_FLAGS.
 314         (cpu_flags): Add CpuCLZERO.
 315         * i386-opc.h: Add CpuCLZERO.
 316         * i386-opc.tbl: Add clzero.
 317         * i386-init.h: Re-generated.
 318         * i386-tbl.h: Re-generated.
 319
 320 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 321
 322         * mips-opc.c (decode_mips_operand): Fix constraint issues
 323         with u and y operands.
 324
 325 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 326
 327         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 328
 329 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 330
 331         * s390-opc.c: Add new IBM z13 instructions.
 332         * s390-opc.txt: Likewise.
 333
 334 2015-03-10  Renlin Li  <renlin.li@arm.com>
 335
 336         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 337         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 338         related alias.
 339         * aarch64-asm-2.c: Regenerate.
 340         * aarch64-dis-2.c: Likewise.
 341         * aarch64-opc-2.c: Likewise.
 342
 343 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 344
 345         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 346
 347 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 348
 349         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 350         arch_sh_up.
 351         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 352         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 353
 354 2015-02-23  Vinay  <Vinay.G@kpit.com>
 355
 356         * rl78-decode.opc (MOV): Added space between two operands for
 357         'mov' instruction in index addressing mode.
 358         * rl78-decode.c: Regenerate.
 359
 360 2015-02-19  Pedro Alves  <palves@redhat.com>
 361
 362         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 363
 364 2015-02-10  Pedro Alves  <palves@redhat.com>
 365             Tom Tromey  <tromey@redhat.com>
 366
 367         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 368         microblaze_and, microblaze_xor.
 369         * microblaze-opc.h (opcodes): Adjust.
 370
 371 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 372
 373         * Makefile.am: Add FT32 files.
 374         * configure.ac: Handle FT32.
 375         * disassemble.c (disassembler): Call print_insn_ft32.
 376         * ft32-dis.c: New file.
 377         * ft32-opc.c: New file.
 378         * Makefile.in: Regenerate.
 379         * configure: Regenerate.
 380         * po/POTFILES.in: Regenerate.
 381
 382 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 383
 384         * nds32-asm.c (keyword_sr): Add new system registers.
 385
 386 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 387
 388         * s390-dis.c (s390_extract_operand): Support vector register
 389         operands.
 390         (s390_print_insn_with_opcode): Support new operands types and add
 391         new handling of optional operands.
 392         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 393         and include opcode/s390.h instead.
 394         (struct op_struct): New field `flags'.
 395         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 396         (dumpTable): Dump flags.
 397         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 398         string.
 399         * s390-opc.c: Add new operands types, instruction formats, and
 400         instruction masks.
 401         (s390_opformats): Add new formats for .insn.
 402         * s390-opc.txt: Add new instructions.
 403
 404 2015-01-01  Alan Modra  <amodra@gmail.com>
 405
 406         Update year range in copyright notice of all files.
 407
 408 For older changes see ChangeLog-2014
 409 \f
 410 Copyright (C) 2015 Free Software Foundation, Inc.
 411
 412 Copying and distribution of this file, with or without modification,
 413 are permitted in any medium without royalty provided the copyright
 414 notice and this notice are preserved.
 415
 416 Local Variables:
 417 mode: change-log
 418 left-margin: 8
 419 fill-column: 74
 420 version-control: never
 421 End: