opcodes/ChangeLog

   1 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/20701
   4         * i386-dis.c (THREE_BYTE_0F7A): Removed.
   5         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
   6         (three_byte_table): Remove THREE_BYTE_0F7A.
   7
   8 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         PR binutils/20775
  11         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
  12         (FGRPd9_4): Replace 1 with 2.
  13         (FGRPd9_5): Replace 2 with 3.
  14         (FGRPd9_6): Replace 3 with 4.
  15         (FGRPd9_7): Replace 4 with 5.
  16         (FGRPda_5): Replace 5 with 6.
  17         (FGRPdb_4): Replace 6 with 7.
  18         (FGRPde_3): Replace 7 with 8.
  19         (FGRPdf_4): Replace 8 with 9.
  20         (fgrps): Add an entry for Bad_Opcode.
  21
  22 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
  23
  24         * arc-opc.c (arc_flag_operands): Add F_DI14.
  25         (arc_flag_classes): Add C_DI14.
  26         * arc-nps400-tbl.h: Add new exc instructions.
  27
  28 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  29
  30         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
  31         major opcode 0xa.
  32         * arc-nps-400-tbl.h: Add dcmac instruction.
  33         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
  34         (insert_nps_rbdouble_64): Added.
  35         (extract_nps_rbdouble_64): Added.
  36         (insert_nps_proto_size): Added.
  37         (extract_nps_proto_size): Added.
  38
  39 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  40
  41         * arc-dis.c (struct arc_operand_iterator): Remove all fields
  42         relating to long instruction processing, add new limm field.
  43         (OPCODE): Rename to...
  44         (OPCODE_32BIT_INSN): ...this.
  45         (OPCODE_AC): Delete.
  46         (skip_this_opcode): Handle different instruction lengths, update
  47         macro name.
  48         (special_flag_p): Update parameter type.
  49         (find_format_from_table): Update for more instruction lengths.
  50         (find_format_long_instructions): Delete.
  51         (find_format): Update for more instruction lengths.
  52         (arc_insn_length): Likewise.
  53         (extract_operand_value): Update for more instruction lengths.
  54         (operand_iterator_next): Remove code relating to long
  55         instructions.
  56         (arc_opcode_to_insn_type): New function.
  57         (print_insn_arc):Update for more instructions lengths.
  58         * arc-ext.c (extInstruction_t): Change argument type.
  59         * arc-ext.h (extInstruction_t): Change argument type.
  60         * arc-fxi.h: Change type unsigned to unsigned long long
  61         extensively throughout.
  62         * arc-nps400-tbl.h: Add long instructions taken from
  63         arc_long_opcodes table in arc-opc.c.
  64         * arc-opc.c: Update parameter types on insert/extract handlers.
  65         (arc_long_opcodes): Delete.
  66         (arc_num_long_opcodes): Delete.
  67         (arc_opcode_len): Update for more instruction lengths.
  68
  69 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  70
  71         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
  72
  73 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  74
  75         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
  76         with arc_opcode_len.
  77         (find_format_long_instructions): Likewise.
  78         * arc-opc.c (arc_opcode_len): New function.
  79
  80 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  81
  82         * arc-nps400-tbl.h: Fix some instruction masks.
  83
  84 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
  85
  86         * i386-dis.c (REG_82): Removed.
  87         (X86_64_82_REG_0): Likewise.
  88         (X86_64_82_REG_1): Likewise.
  89         (X86_64_82_REG_2): Likewise.
  90         (X86_64_82_REG_3): Likewise.
  91         (X86_64_82_REG_4): Likewise.
  92         (X86_64_82_REG_5): Likewise.
  93         (X86_64_82_REG_6): Likewise.
  94         (X86_64_82_REG_7): Likewise.
  95         (X86_64_82): New.
  96         (dis386): Use X86_64_82 instead of REG_82.
  97         (reg_table): Remove REG_82.
  98         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
  99         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 100         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 101         X86_64_82_REG_7.
 102
 103 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         PR binutils/20754
 106         * i386-dis.c (REG_82): New.
 107         (X86_64_82_REG_0): Likewise.
 108         (X86_64_82_REG_1): Likewise.
 109         (X86_64_82_REG_2): Likewise.
 110         (X86_64_82_REG_3): Likewise.
 111         (X86_64_82_REG_4): Likewise.
 112         (X86_64_82_REG_5): Likewise.
 113         (X86_64_82_REG_6): Likewise.
 114         (X86_64_82_REG_7): Likewise.
 115         (dis386): Use REG_82.
 116         (reg_table): Add REG_82.
 117         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 118         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 119         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 120
 121 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 122
 123         * i386-dis.c (REG_82): Renamed to ...
 124         (REG_83): This.
 125         (dis386): Updated.
 126         (reg_table): Likewise.
 127
 128 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 129
 130         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 131         * i386-dis-evex.h (evex_table): Updated.
 132         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 133         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 134         (cpu_flags): Add CpuAVX512_4VNNIW.
 135         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 136         (i386_cpu_flags): Add cpuavx512_4vnniw.
 137         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 138         * i386-init.h: Regenerate.
 139         * i386-tbl.h: Ditto.
 140
 141 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 142
 143         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 144         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 145         * i386-dis-evex.h (evex_table): Updated.
 146         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 147         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 148         (cpu_flags): Add CpuAVX512_4FMAPS.
 149         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 150         * i386-opc.h (AVX512_4FMAP): New.
 151         (i386_cpu_flags): Add cpuavx512_4fmaps.
 152         (ImplicitQuadGroup): New.
 153         (i386_opcode_modifier): Add implicitquadgroup.
 154         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 155         * i386-init.h: Regenerate.
 156         * i386-tbl.h: Ditto.
 157
 158 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 159             Andrew Waterman <andrew@sifive.com>
 160
 161         Add support for RISC-V architecture.
 162         * configure.ac: Add entry for bfd_riscv_arch.
 163         * configure: Regenerate.
 164         * disassemble.c (disassembler): Add support for riscv.
 165         (disassembler_usage): Likewise.
 166         * riscv-dis.c: New file.
 167         * riscv-opc.c: New file.
 168
 169 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 170
 171         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 172         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 173         (rm_table): Update the RM_0FAE_REG_7 entry.
 174         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 175         (cpu_flags): Remove CpuPCOMMIT.
 176         * i386-opc.h (CpuPCOMMIT): Removed.
 177         (i386_cpu_flags): Remove cpupcommit.
 178         * i386-opc.tbl: Remove pcommit.
 179         * i386-init.h: Regenerated.
 180         * i386-tbl.h: Likewise.
 181
 182 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         PR binutis/20705
 185         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 186         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 187         32-bit mode.  Don't check vex.register_specifier in 32-bit
 188         mode.
 189         (OP_VEX): Check for invalid mask registers.
 190
 191 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         PR binutis/20699
 194         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 195         sizeflag.
 196
 197 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         PR binutis/20704
 200         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 201
 202 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 203
 204         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 205         local variable to `index_regno'.
 206
 207 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 208
 209         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 210
 211 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 212
 213         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 214         usage on ISA basis.
 215
 216 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 217
 218         PR target/20666
 219         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 220
 221 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 222
 223         PR target/20667
 224         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 225         available.
 226
 227 2016-10-07  Alan Modra  <amodra@gmail.com>
 228
 229         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 230
 231 2016-10-06  Alan Modra  <amodra@gmail.com>
 232
 233         * aarch64-opc.c: Spell fall through comments consistently.
 234         * i386-dis.c: Likewise.
 235         * aarch64-dis.c: Add missing fall through comments.
 236         * aarch64-opc.c: Likewise.
 237         * arc-dis.c: Likewise.
 238         * arm-dis.c: Likewise.
 239         * i386-dis.c: Likewise.
 240         * m68k-dis.c: Likewise.
 241         * mep-asm.c: Likewise.
 242         * ns32k-dis.c: Likewise.
 243         * sh-dis.c: Likewise.
 244         * tic4x-dis.c: Likewise.
 245         * tic6x-dis.c: Likewise.
 246         * vax-dis.c: Likewise.
 247
 248 2016-10-06  Alan Modra  <amodra@gmail.com>
 249
 250         * arc-ext.c (create_map): Add missing break.
 251         * msp430-decode.opc (encode_as): Likewise.
 252         * msp430-decode.c: Regenerate.
 253
 254 2016-10-06  Alan Modra  <amodra@gmail.com>
 255
 256         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 257         * crx-dis.c (print_insn_crx): Likewise.
 258
 259 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         PR binutils/20657
 262         * i386-dis.c (putop): Don't assign alt twice.
 263
 264 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 265
 266         PR target/20553
 267         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 268
 269 2016-09-29  Alan Modra  <amodra@gmail.com>
 270
 271         * ppc-opc.c (L): Make compulsory.
 272         (LOPT): New, optional form of L.
 273         (HTM_R): Define as LOPT.
 274         (L0, L1): Delete.
 275         (L32OPT): New, optional for 32-bit L.
 276         (L2OPT): New, 2-bit L for dcbf.
 277         (SVC_LEC): Update.
 278         (L2): Define.
 279         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 280         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 281         <dcbf>: Use L2OPT.
 282         <tlbiel, tlbie>: Use LOPT.
 283         <wclr, wclrall>: Use L2.
 284
 285 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 286
 287         * Makefile.in: Regenerate.
 288         * configure: Likewise.
 289
 290 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 291
 292         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 293         (EXTINSN2OP): Use EXTINSN2OPF.
 294         (bspeekm, bspop, modapp): New extension instructions.
 295         * arc-opc.c (F_DNZ_ND): Define.
 296         (F_DNZ_D): Likewise.
 297         (F_SIZEB1): Changed.
 298         (C_DNZ_D): Define.
 299         (C_HARD): Changed.
 300         * arc-tbl.h (dbnz): New instruction.
 301         (prealloc): Allow it for ARC EM.
 302         (xbfu): Likewise.
 303
 304 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 305
 306         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 307         after commas in addresses.
 308         (aarch64_print_operand): Likewise.
 309
 310 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 311
 312         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 313         rather than "should be" or "expected to be" in error messages.
 314
 315 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 316
 317         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 318         (print_mnemonic_name): ...here.
 319         (print_comment): New function.
 320         (print_aarch64_insn): Call it.
 321         * aarch64-opc.c (aarch64_conds): Add SVE names.
 322         (aarch64_print_operand): Print alternative condition names in
 323         a comment.
 324
 325 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 326
 327         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 328         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 329         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 330         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 331         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 332         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 333         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 334         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 335         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 336         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 337         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 338         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 339         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 340         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 341         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 342         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 343         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 344         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 345         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 346         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 347         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 348         (aarch64_feature_sve): New variable.
 349         (SVE): New macro.
 350         (_SVE_INSN): Likewise.
 351         (aarch64_opcode_table): Add SVE instructions.
 352         * aarch64-opc.h (extract_fields): Declare.
 353         * aarch64-opc-2.c: Regenerate.
 354         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 355         * aarch64-asm-2.c: Regenerate.
 356         * aarch64-dis.c (extract_fields): Make global.
 357         (do_misc_decoding): Handle the new SVE aarch64_ops.
 358         * aarch64-dis-2.c: Regenerate.
 359
 360 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 361
 362         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 363         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 364         aarch64_field_kinds.
 365         * aarch64-opc.c (fields): Add corresponding entries.
 366         * aarch64-asm.c (aarch64_get_variant): New function.
 367         (aarch64_encode_variant_using_iclass): Likewise.
 368         (aarch64_opcode_encode): Call it.
 369         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 370         (aarch64_opcode_decode): Call it.
 371
 372 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 373
 374         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 375         and FP register operands.
 376         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 377         (FLD_SVE_Vn): New aarch64_field_kinds.
 378         * aarch64-opc.c (fields): Add corresponding entries.
 379         (aarch64_print_operand): Handle the new SVE core and FP register
 380         operands.
 381         * aarch64-opc-2.c: Regenerate.
 382         * aarch64-asm-2.c: Likewise.
 383         * aarch64-dis-2.c: Likewise.
 384
 385 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 386
 387         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 388         immediate operands.
 389         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 390         * aarch64-opc.c (fields): Add corresponding entry.
 391         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 392         operands.
 393         (aarch64_print_operand): Likewise.
 394         * aarch64-opc-2.c: Regenerate.
 395         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 396         (ins_sve_float_zero_one): New inserters.
 397         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 398         (aarch64_ins_sve_float_half_two): Likewise.
 399         (aarch64_ins_sve_float_zero_one): Likewise.
 400         * aarch64-asm-2.c: Regenerate.
 401         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 402         (ext_sve_float_zero_one): New extractors.
 403         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 404         (aarch64_ext_sve_float_half_two): Likewise.
 405         (aarch64_ext_sve_float_zero_one): Likewise.
 406         * aarch64-dis-2.c: Regenerate.
 407
 408 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 409
 410         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 411         integer immediate operands.
 412         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 413         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 414         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 415         * aarch64-opc.c (fields): Add corresponding entries.
 416         (operand_general_constraint_met_p): Handle the new SVE integer
 417         immediate operands.
 418         (aarch64_print_operand): Likewise.
 419         (aarch64_sve_dupm_mov_immediate_p): New function.
 420         * aarch64-opc-2.c: Regenerate.
 421         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 422         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 423         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 424         (aarch64_ins_limm): ...here.
 425         (aarch64_ins_inv_limm): New function.
 426         (aarch64_ins_sve_aimm): Likewise.
 427         (aarch64_ins_sve_asimm): Likewise.
 428         (aarch64_ins_sve_limm_mov): Likewise.
 429         (aarch64_ins_sve_shlimm): Likewise.
 430         (aarch64_ins_sve_shrimm): Likewise.
 431         * aarch64-asm-2.c: Regenerate.
 432         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 433         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 434         * aarch64-dis.c (decode_limm): New function, split out from...
 435         (aarch64_ext_limm): ...here.
 436         (aarch64_ext_inv_limm): New function.
 437         (decode_sve_aimm): Likewise.
 438         (aarch64_ext_sve_aimm): Likewise.
 439         (aarch64_ext_sve_asimm): Likewise.
 440         (aarch64_ext_sve_limm_mov): Likewise.
 441         (aarch64_top_bit): Likewise.
 442         (aarch64_ext_sve_shlimm): Likewise.
 443         (aarch64_ext_sve_shrimm): Likewise.
 444         * aarch64-dis-2.c: Regenerate.
 445
 446 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 447
 448         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 449         operands.
 450         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 451         the AARCH64_MOD_MUL_VL entry.
 452         (value_aligned_p): Cope with non-power-of-two alignments.
 453         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 454         (print_immediate_offset_address): Likewise.
 455         (aarch64_print_operand): Likewise.
 456         * aarch64-opc-2.c: Regenerate.
 457         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 458         (ins_sve_addr_ri_s9xvl): New inserters.
 459         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 460         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 461         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 462         * aarch64-asm-2.c: Regenerate.
 463         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 464         (ext_sve_addr_ri_s9xvl): New extractors.
 465         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 466         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 467         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 468         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 469         * aarch64-dis-2.c: Regenerate.
 470
 471 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 472
 473         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 474         address operands.
 475         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 476         (FLD_SVE_xs_22): New aarch64_field_kinds.
 477         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 478         (get_operand_specific_data): New function.
 479         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 480         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 481         (operand_general_constraint_met_p): Handle the new SVE address
 482         operands.
 483         (sve_reg): New array.
 484         (get_addr_sve_reg_name): New function.
 485         (aarch64_print_operand): Handle the new SVE address operands.
 486         * aarch64-opc-2.c: Regenerate.
 487         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 488         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 489         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 490         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 491         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 492         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 493         (aarch64_ins_sve_addr_zi_u5): Likewise.
 494         (aarch64_ins_sve_addr_zz): Likewise.
 495         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 496         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 497         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 498         * aarch64-asm-2.c: Regenerate.
 499         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 500         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 501         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 502         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 503         (aarch64_ext_sve_addr_ri_u6): Likewise.
 504         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 505         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 506         (aarch64_ext_sve_addr_zi_u5): Likewise.
 507         (aarch64_ext_sve_addr_zz): Likewise.
 508         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 509         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 510         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 511         * aarch64-dis-2.c: Regenerate.
 512
 513 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 514
 515         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 516         AARCH64_OPND_SVE_PATTERN_SCALED.
 517         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 518         * aarch64-opc.c (fields): Add a corresponding entry.
 519         (set_multiplier_out_of_range_error): New function.
 520         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 521         (operand_general_constraint_met_p): Handle
 522         AARCH64_OPND_SVE_PATTERN_SCALED.
 523         (print_register_offset_address): Use PRIi64 to print the
 524         shift amount.
 525         (aarch64_print_operand): Likewise.  Handle
 526         AARCH64_OPND_SVE_PATTERN_SCALED.
 527         * aarch64-opc-2.c: Regenerate.
 528         * aarch64-asm.h (ins_sve_scale): New inserter.
 529         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 530         * aarch64-asm-2.c: Regenerate.
 531         * aarch64-dis.h (ext_sve_scale): New inserter.
 532         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 533         * aarch64-dis-2.c: Regenerate.
 534
 535 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 536
 537         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 538         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 539         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 540         (FLD_SVE_prfop): Likewise.
 541         * aarch64-opc.c: Include libiberty.h.
 542         (aarch64_sve_pattern_array): New variable.
 543         (aarch64_sve_prfop_array): Likewise.
 544         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 545         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 546         AARCH64_OPND_SVE_PRFOP.
 547         * aarch64-asm-2.c: Regenerate.
 548         * aarch64-dis-2.c: Likewise.
 549         * aarch64-opc-2.c: Likewise.
 550
 551 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 552
 553         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 554         AARCH64_OPND_QLF_P_[ZM].
 555         (aarch64_print_operand): Print /z and /m where appropriate.
 556
 557 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 558
 559         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 560         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 561         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 562         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 563         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 564         * aarch64-opc.c (fields): Add corresponding entries here.
 565         (operand_general_constraint_met_p): Check that SVE register lists
 566         have the correct length.  Check the ranges of SVE index registers.
 567         Check for cases where p8-p15 are used in 3-bit predicate fields.
 568         (aarch64_print_operand): Handle the new SVE operands.
 569         * aarch64-opc-2.c: Regenerate.
 570         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 571         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 572         (aarch64_ins_sve_reglist): Likewise.
 573         * aarch64-asm-2.c: Regenerate.
 574         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 575         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 576         (aarch64_ext_sve_reglist): Likewise.
 577         * aarch64-dis-2.c: Regenerate.
 578
 579 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 580
 581         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 582         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 583         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 584         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 585         tied operands.
 586
 587 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 588
 589         * aarch64-opc.c (get_offset_int_reg_name): New function.
 590         (print_immediate_offset_address): Likewise.
 591         (print_register_offset_address): Take the base and offset
 592         registers as parameters.
 593         (aarch64_print_operand): Update caller accordingly.  Use
 594         print_immediate_offset_address.
 595
 596 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 597
 598         * aarch64-opc.c (BANK): New macro.
 599         (R32, R64): Take a register number as argument
 600         (int_reg): Use BANK.
 601
 602 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 603
 604         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 605         (aarch64_print_operand): Update accordingly.
 606
 607 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 608
 609         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 610         for FPIMM.
 611         * aarch64-asm.h (ins_fpimm): New inserter.
 612         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 613         * aarch64-asm-2.c: Regenerate.
 614         * aarch64-dis.h (ext_fpimm): New extractor.
 615         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 616         (aarch64_ext_fpimm): New function.
 617         * aarch64-dis-2.c: Regenerate.
 618
 619 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 620
 621         * aarch64-asm.c: Include libiberty.h.
 622         (insert_fields): New function.
 623         (aarch64_ins_imm): Use it.
 624         * aarch64-dis.c (extract_fields): New function.
 625         (aarch64_ext_imm): Use it.
 626
 627 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 628
 629         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 630         with an esize parameter.
 631         (operand_general_constraint_met_p): Update accordingly.
 632         Fix misindented code.
 633         * aarch64-asm.c (aarch64_ins_limm): Update call to
 634         aarch64_logical_immediate_p.
 635
 636 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 637
 638         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 639
 640 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 641
 642         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 643
 644 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 645
 646         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 647
 648 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 649
 650         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 651         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 652         xor3>: Delete mnemonics.
 653         <cp_abort>: Rename mnemonic from ...
 654         <cpabort>: ...to this.
 655         <setb>: Change to a X form instruction.
 656         <sync>: Change to 1 operand form.
 657         <copy>: Delete mnemonic.
 658         <copy_first>: Rename mnemonic from ...
 659         <copy>: ...to this.
 660         <paste, paste.>: Delete mnemonics.
 661         <paste_last>: Rename mnemonic from ...
 662         <paste.>: ...to this.
 663
 664 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 665
 666         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 667
 668 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 669
 670         * s390-mkopc.c (main): Support alternate arch strings.
 671
 672 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 673
 674         * s390-opc.txt: Fix kmctr instruction type.
 675
 676 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 677
 678         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 679         * i386-init.h: Regenerated.
 680
 681 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 682
 683         * opcodes/arc-dis.c (print_insn_arc): Changed.
 684
 685 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 686
 687         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 688         camellia_fl.
 689
 690 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 691
 692         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 693         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 694         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 695
 696 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 697
 698         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 699         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 700         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 701         PREFIX_MOD_3_0FAE_REG_4.
 702         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 703         PREFIX_MOD_3_0FAE_REG_4.
 704         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 705         (cpu_flags): Add CpuPTWRITE.
 706         * i386-opc.h (CpuPTWRITE): New.
 707         (i386_cpu_flags): Add cpuptwrite.
 708         * i386-opc.tbl: Add ptwrite instruction.
 709         * i386-init.h: Regenerated.
 710         * i386-tbl.h: Likewise.
 711
 712 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 713
 714         * arc-dis.h: Wrap around in extern "C".
 715
 716 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 717
 718         * aarch64-tbl.h (V8_2_INSN): New macro.
 719         (aarch64_opcode_table): Use it.
 720
 721 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 722
 723         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 724         CORE_INSN, __FP_INSN and SIMD_INSN.
 725
 726 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 727
 728         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 729         (aarch64_opcode_table): Update uses accordingly.
 730
 731 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 732         Kwok Cheung Yeung  <kcy@codesourcery.com>
 733
 734         opcodes/
 735         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 736         'e_cmplwi' to 'e_cmpli' instead.
 737         (OPVUPRT, OPVUPRT_MASK): Define.
 738         (powerpc_opcodes): Add E200Z4 insns.
 739         (vle_opcodes): Add context save/restore insns.
 740
 741 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 742
 743         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 744         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 745         "j".
 746
 747 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 748
 749         * arc-nps400-tbl.h: Change block comments to GNU format.
 750         * arc-dis.c: Add new globals addrtypenames,
 751         addrtypenames_max, and addtypeunknown.
 752         (get_addrtype): New function.
 753         (print_insn_arc): Print colons and address types when
 754         required.
 755         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 756         define insert and extract functions for all address types.
 757         (arc_operands): Add operands for colon and all address
 758         types.
 759         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 760         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 761         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 762         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 763         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 764         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 765
 766 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 767
 768         * configure: Regenerated.
 769
 770 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 771
 772         * arc-dis.c (skipclass): New structure.
 773         (decodelist): New variable.
 774         (is_compatible_p): New function.
 775         (new_element): Likewise.
 776         (skip_class_p): Likewise.
 777         (find_format_from_table): Use skip_class_p function.
 778         (find_format): Decode first the extension instructions.
 779         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 780         e_flags.
 781         (parse_option): New function.
 782         (parse_disassembler_options): Likewise.
 783         (print_arc_disassembler_options): Likewise.
 784         (print_insn_arc): Use parse_disassembler_options function.  Proper
 785         select ARCv2 cpu variant.
 786         * disassemble.c (disassembler_usage): Add ARC disassembler
 787         options.
 788
 789 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 790
 791         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 792         annotation from the "nal" entry and reorder it beyond "bltzal".
 793
 794 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 795
 796         * sparc-opc.c (ldtxa): New macro.
 797         (sparc_opcodes): Use the macro defined above to add entries for
 798         the LDTXA instructions.
 799         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 800         instruction.
 801
 802 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 803
 804         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 805         and "jmpc".
 806
 807 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 810         (movzb): Adjust to cover all permitted suffixes.
 811         (movzw): New.
 812         * i386-tbl.h: Re-generate.
 813
 814 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 817         (lgdt): Remove Tbyte from non-64-bit variant.
 818         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 819         xsaves64, xsavec64): Remove Disp16.
 820         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 821         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 822         64-bit variants.
 823         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 824         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 825         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 826         64-bit variants.
 827         * i386-tbl.h: Re-generate.
 828
 829 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 832         * i386-tbl.h: Re-generate.
 833
 834 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 835
 836         * arm-dis.c (print_insn): Fix typo in comment.
 837
 838 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 839
 840         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 841         range of ldst_elemlist operands.
 842         (print_register_list): Use PRIi64 to print the index.
 843         (aarch64_print_operand): Likewise.
 844
 845 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 846
 847         * mcore-opc.h: Remove sentinal.
 848         * mcore-dis.c (print_insn_mcore): Adjust.
 849
 850 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 851
 852         * arc-opc.c: Correct description of availability of NPS400
 853         features.
 854
 855 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 856
 857         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 858         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 859         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 860         xor3>: New mnemonics.
 861         <setb>: Change to a VX form instruction.
 862         (insert_sh6): Add support for rldixor.
 863         (extract_sh6): Likewise.
 864
 865 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 866
 867         * arc-ext.h: Wrap in extern C.
 868
 869 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 870
 871         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 872         Use same method for determining instruction length on ARC700 and
 873         NPS-400.
 874         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 875         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 876         with the NPS400 subclass.
 877         * arc-opc.c: Likewise.
 878
 879 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 880
 881         * sparc-opc.c (rdasr): New macro.
 882         (wrasr): Likewise.
 883         (rdpr): Likewise.
 884         (wrpr): Likewise.
 885         (rdhpr): Likewise.
 886         (wrhpr): Likewise.
 887         (sparc_opcodes): Use the macros above to fix and expand the
 888         definition of read/write instructions from/to
 889         asr/privileged/hyperprivileged instructions.
 890         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 891         %hva_mask_nz.  Prefer softint_set and softint_clear over
 892         set_softint and clear_softint.
 893         (print_insn_sparc): Support %ver in Rd.
 894
 895 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 896
 897         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 898         architecture according to the hardware capabilities they require.
 899
 900 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 901
 902         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 903         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 904         bfd_mach_sparc_v9{c,d,e,v,m}.
 905         * sparc-opc.c (MASK_V9C): Define.
 906         (MASK_V9D): Likewise.
 907         (MASK_V9E): Likewise.
 908         (MASK_V9V): Likewise.
 909         (MASK_V9M): Likewise.
 910         (v6): Add MASK_V9{C,D,E,V,M}.
 911         (v6notlet): Likewise.
 912         (v7): Likewise.
 913         (v8): Likewise.
 914         (v9): Likewise.
 915         (v9andleon): Likewise.
 916         (v9a): Likewise.
 917         (v9b): Likewise.
 918         (v9c): Define.
 919         (v9d): Likewise.
 920         (v9e): Likewise.
 921         (v9v): Likewise.
 922         (v9m): Likewise.
 923         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 924
 925 2016-06-15  Nick Clifton  <nickc@redhat.com>
 926
 927         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 928         constants to match expected behaviour.
 929         (nds32_parse_opcode): Likewise.  Also for whitespace.
 930
 931 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 932
 933         * arc-opc.c (extract_rhv1): Extract value from insn.
 934
 935 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 936
 937         * arc-nps400-tbl.h: Add ldbit instruction.
 938         * arc-opc.c: Add flag classes required for ldbit.
 939
 940 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 941
 942         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 943         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 944         support the above instructions.
 945
 946 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 947
 948         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 949         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 950         csma, cbba, zncv, and hofs.
 951         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 952         support the above instructions.
 953
 954 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 955
 956         * arc-nps400-tbl.h: Add andab and orab instructions.
 957
 958 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 959
 960         * arc-nps400-tbl.h: Add addl-like instructions.
 961
 962 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 963
 964         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 965
 966 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 967
 968         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 969         instructions.
 970
 971 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 972
 973         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 974         variable.
 975         (init_disasm): Handle new command line option "insnlength".
 976         (print_s390_disassembler_options): Mention new option in help
 977         output.
 978         (print_insn_s390): Use the encoded insn length when dumping
 979         unknown instructions.
 980
 981 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 982
 983         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 984          to the address and set as symbol address for LDS/ STS immediate operands.
 985
 986 2016-06-07  Alan Modra  <amodra@gmail.com>
 987
 988         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 989         cpu for "vle" to e500.
 990         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 991         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 992         (PPCNONE): Delete, substitute throughout.
 993         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 994         except for major opcode 4 and 31.
 995         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 996
 997 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 998
 999         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1000         ARM_EXT_RAS in relevant entries.
1001
1002 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1003
1004         PR binutils/20196
1005         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1006         opcodes for E6500.
1007
1008 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1009
1010         PR binutis/18386
1011         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1012         (indir_v_mode): New.
1013         Add comments for '&'.
1014         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1015         (putop): Handle '&'.
1016         (intel_operand_size): Handle indir_v_mode.
1017         (OP_E_register): Likewise.
1018         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1019         64-bit indirect call/jmp for AMD64.
1020         * i386-tbl.h: Regenerated
1021
1022 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1023
1024         * arc-dis.c (struct arc_operand_iterator): New structure.
1025         (find_format_from_table): All the old content from find_format,
1026         with some minor adjustments, and parameter renaming.
1027         (find_format_long_instructions): New function.
1028         (find_format): Rewritten.
1029         (arc_insn_length): Add LSB parameter.
1030         (extract_operand_value): New function.
1031         (operand_iterator_next): New function.
1032         (print_insn_arc): Use new functions to find opcode, and iterator
1033         over operands.
1034         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1035         (extract_nps_3bit_dst_short): New function.
1036         (insert_nps_3bit_src2_short): New function.
1037         (extract_nps_3bit_src2_short): New function.
1038         (insert_nps_bitop1_size): New function.
1039         (extract_nps_bitop1_size): New function.
1040         (insert_nps_bitop2_size): New function.
1041         (extract_nps_bitop2_size): New function.
1042         (insert_nps_bitop_mod4_msb): New function.
1043         (extract_nps_bitop_mod4_msb): New function.
1044         (insert_nps_bitop_mod4_lsb): New function.
1045         (extract_nps_bitop_mod4_lsb): New function.
1046         (insert_nps_bitop_dst_pos3_pos4): New function.
1047         (extract_nps_bitop_dst_pos3_pos4): New function.
1048         (insert_nps_bitop_ins_ext): New function.
1049         (extract_nps_bitop_ins_ext): New function.
1050         (arc_operands): Add new operands.
1051         (arc_long_opcodes): New global array.
1052         (arc_num_long_opcodes): New global.
1053         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1054
1055 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1056
1057         * nds32-asm.h: Add extern "C".
1058         * sh-opc.h: Likewise.
1059
1060 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1061
1062         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1063         0,b,limm to the rflt instruction.
1064
1065 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1066
1067         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1068         constant.
1069
1070 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1071
1072         PR gas/20145
1073         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1074         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1075         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1076         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1077         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1078         * i386-init.h: Regenerated.
1079
1080 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1081
1082         PR gas/20145
1083         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1084         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1085         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1086         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1087         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1088         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1089         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1090         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1091         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1092         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1093         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1094         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1095         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1096         CpuRegMask for AVX512.
1097         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1098         and CpuRegMask.
1099         (set_bitfield_from_cpu_flag_init): New function.
1100         (set_bitfield): Remove const on f.  Call
1101         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1102         * i386-opc.h (CpuRegMMX): New.
1103         (CpuRegXMM): Likewise.
1104         (CpuRegYMM): Likewise.
1105         (CpuRegZMM): Likewise.
1106         (CpuRegMask): Likewise.
1107         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1108         and cpuregmask.
1109         * i386-init.h: Regenerated.
1110         * i386-tbl.h: Likewise.
1111
1112 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1113
1114         PR gas/20154
1115         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1116         (opcode_modifiers): Add AMD64 and Intel64.
1117         (main): Properly verify CpuMax.
1118         * i386-opc.h (CpuAMD64): Removed.
1119         (CpuIntel64): Likewise.
1120         (CpuMax): Set to CpuNo64.
1121         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1122         (AMD64): New.
1123         (Intel64): Likewise.
1124         (i386_opcode_modifier): Add amd64 and intel64.
1125         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1126         on call and jmp.
1127         * i386-init.h: Regenerated.
1128         * i386-tbl.h: Likewise.
1129
1130 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1131
1132         PR gas/20154
1133         * i386-gen.c (main): Fail if CpuMax is incorrect.
1134         * i386-opc.h (CpuMax): Set to CpuIntel64.
1135         * i386-tbl.h: Regenerated.
1136
1137 2016-05-27  Nick Clifton  <nickc@redhat.com>
1138
1139         PR target/20150
1140         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1141         (msp430dis_opcode_unsigned): New function.
1142         (msp430dis_opcode_signed): New function.
1143         (msp430_singleoperand): Use the new opcode reading functions.
1144         Only disassenmble bytes if they were successfully read.
1145         (msp430_doubleoperand): Likewise.
1146         (msp430_branchinstr): Likewise.
1147         (msp430x_callx_instr): Likewise.
1148         (print_insn_msp430): Check that it is safe to read bytes before
1149         attempting disassembly.  Use the new opcode reading functions.
1150
1151 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1152
1153         * ppc-opc.c (CY): New define.  Document it.
1154         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1155
1156 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1157
1158         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1159         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1160         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1161         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1162         CPU_ANY_AVX_FLAGS.
1163         * i386-init.h: Regenerated.
1164
1165 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1166
1167         PR gas/20141
1168         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1169         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1170         * i386-init.h: Regenerated.
1171
1172 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1173
1174         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1175         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1176         * i386-init.h: Regenerated.
1177
1178 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1179
1180         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1181         information.
1182         (print_insn_arc): Set insn_type information.
1183         * arc-opc.c (C_CC): Add F_CLASS_COND.
1184         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1185         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1186         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1187         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1188         (brne, brne_s, jeq_s, jne_s): Likewise.
1189
1190 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1191
1192         * arc-tbl.h (neg): New instruction variant.
1193
1194 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1195
1196         * arc-dis.c (find_format, find_format, get_auxreg)
1197         (print_insn_arc): Changed.
1198         * arc-ext.h (INSERT_XOP): Likewise.
1199
1200 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1201
1202         * tic54x-dis.c (sprint_mmr): Adjust.
1203         * tic54x-opc.c: Likewise.
1204
1205 2016-05-19  Alan Modra  <amodra@gmail.com>
1206
1207         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1208
1209 2016-05-19  Alan Modra  <amodra@gmail.com>
1210
1211         * ppc-opc.c: Formatting.
1212         (NSISIGNOPT): Define.
1213         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1214
1215 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1216
1217         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1218         replacing references to `micromips_ase' throughout.
1219         (_print_insn_mips): Don't use file-level microMIPS annotation to
1220         determine the disassembly mode with the symbol table.
1221
1222 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1223
1224         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1225
1226 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1227
1228         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1229         mips64r6.
1230         * mips-opc.c (D34): New macro.
1231         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1232
1233 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1234
1235         * i386-dis.c (prefix_table): Add RDPID instruction.
1236         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1237         (cpu_flags): Add RDPID bitfield.
1238         * i386-opc.h (enum): Add RDPID element.
1239         (i386_cpu_flags): Add RDPID field.
1240         * i386-opc.tbl: Add RDPID instruction.
1241         * i386-init.h: Regenerate.
1242         * i386-tbl.h: Regenerate.
1243
1244 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1245
1246         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1247         branch type of a symbol.
1248         (print_insn): Likewise.
1249
1250 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1251
1252         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1253         Mainline Security Extensions instructions.
1254         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1255         Extensions instructions.
1256         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1257         instructions.
1258         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1259         special registers.
1260
1261 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1262
1263         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1264
1265 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1266
1267         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1268         (arcExtMap_genOpcode): Likewise.
1269         * arc-opc.c (arg_32bit_rc): Define new variable.
1270         (arg_32bit_u6): Likewise.
1271         (arg_32bit_limm): Likewise.
1272
1273 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1274
1275         * aarch64-gen.c (VERIFIER): Define.
1276         * aarch64-opc.c (VERIFIER): Define.
1277         (verify_ldpsw): Use static linkage.
1278         * aarch64-opc.h (verify_ldpsw): Remove.
1279         * aarch64-tbl.h: Use VERIFIER for verifiers.
1280
1281 2016-04-28  Nick Clifton  <nickc@redhat.com>
1282
1283         PR target/19722
1284         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1285         * aarch64-opc.c (verify_ldpsw): New function.
1286         * aarch64-opc.h (verify_ldpsw): New prototype.
1287         * aarch64-tbl.h: Add initialiser for verifier field.
1288         (LDPSW): Set verifier to verify_ldpsw.
1289
1290 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1291
1292         PR binutils/19983
1293         PR binutils/19984
1294         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1295         smaller than address size.
1296
1297 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1298
1299         * alpha-dis.c: Regenerate.
1300         * crx-dis.c: Likewise.
1301         * disassemble.c: Likewise.
1302         * epiphany-opc.c: Likewise.
1303         * fr30-opc.c: Likewise.
1304         * frv-opc.c: Likewise.
1305         * ip2k-opc.c: Likewise.
1306         * iq2000-opc.c: Likewise.
1307         * lm32-opc.c: Likewise.
1308         * lm32-opinst.c: Likewise.
1309         * m32c-opc.c: Likewise.
1310         * m32r-opc.c: Likewise.
1311         * m32r-opinst.c: Likewise.
1312         * mep-opc.c: Likewise.
1313         * mt-opc.c: Likewise.
1314         * or1k-opc.c: Likewise.
1315         * or1k-opinst.c: Likewise.
1316         * tic80-opc.c: Likewise.
1317         * xc16x-opc.c: Likewise.
1318         * xstormy16-opc.c: Likewise.
1319
1320 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1321
1322         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1323         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1324         calcsd, and calcxd instructions.
1325         * arc-opc.c (insert_nps_bitop_size): Delete.
1326         (extract_nps_bitop_size): Delete.
1327         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1328         (extract_nps_qcmp_m3): Define.
1329         (extract_nps_qcmp_m2): Define.
1330         (extract_nps_qcmp_m1): Define.
1331         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1332         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1333         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1334         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1335         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1336         NPS_QCMP_M3.
1337
1338 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1339
1340         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1341
1342 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1343
1344         * Makefile.in: Regenerated with automake 1.11.6.
1345         * aclocal.m4: Likewise.
1346
1347 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1348
1349         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1350         instructions.
1351         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1352         (extract_nps_cmem_uimm16): New function.
1353         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1354
1355 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1356
1357         * arc-dis.c (arc_insn_length): New function.
1358         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1359         (find_format): Change insnLen parameter to unsigned.
1360
1361 2016-04-13  Nick Clifton  <nickc@redhat.com>
1362
1363         PR target/19937
1364         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1365         the LD.B and LD.BU instructions.
1366
1367 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1368
1369         * arc-dis.c (find_format): Check for extension flags.
1370         (print_flags): New function.
1371         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1372         .extAuxRegister.
1373         * arc-ext.c (arcExtMap_coreRegName): Use
1374         LAST_EXTENSION_CORE_REGISTER.
1375         (arcExtMap_coreReadWrite): Likewise.
1376         (dump_ARC_extmap): Update printing.
1377         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1378         (arc_aux_regs): Add cpu field.
1379         * arc-regs.h: Add cpu field, lower case name aux registers.
1380
1381 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1382
1383         * arc-tbl.h: Add rtsc, sleep with no arguments.
1384
1385 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1386
1387         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1388         Initialize.
1389         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1390         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1391         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1392         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1393         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1394         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1395         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1396         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1397         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1398         (arc_opcode arc_opcodes): Null terminate the array.
1399         (arc_num_opcodes): Remove.
1400         * arc-ext.h (INSERT_XOP): Define.
1401         (extInstruction_t): Likewise.
1402         (arcExtMap_instName): Delete.
1403         (arcExtMap_insn): New function.
1404         (arcExtMap_genOpcode): Likewise.
1405         * arc-ext.c (ExtInstruction): Remove.
1406         (create_map): Zero initialize instruction fields.
1407         (arcExtMap_instName): Remove.
1408         (arcExtMap_insn): New function.
1409         (dump_ARC_extmap): More info while debuging.
1410         (arcExtMap_genOpcode): New function.
1411         * arc-dis.c (find_format): New function.
1412         (print_insn_arc): Use find_format.
1413         (arc_get_disassembler): Enable dump_ARC_extmap only when
1414         debugging.
1415
1416 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1417
1418         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1419         instruction bits out.
1420
1421 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1422
1423         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1424         * arc-opc.c (arc_flag_operands): Add new flags.
1425         (arc_flag_classes): Add new classes.
1426
1427 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1428
1429         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1430
1431 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1432
1433         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1434         encode1, rflt, crc16, and crc32 instructions.
1435         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1436         (arc_flag_classes): Add C_NPS_R.
1437         (insert_nps_bitop_size_2b): New function.
1438         (extract_nps_bitop_size_2b): Likewise.
1439         (insert_nps_bitop_uimm8): Likewise.
1440         (extract_nps_bitop_uimm8): Likewise.
1441         (arc_operands): Add new operand entries.
1442
1443 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1444
1445         * arc-regs.h: Add a new subclass field.  Add double assist
1446         accumulator register values.
1447         * arc-tbl.h: Use DPA subclass to mark the double assist
1448         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1449         * arc-opc.c (RSP): Define instead of SP.
1450         (arc_aux_regs): Add the subclass field.
1451
1452 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1453
1454         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1455
1456 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1457
1458         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1459         NPS_R_SRC1.
1460
1461 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1462
1463         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1464         issues.  No functional changes.
1465
1466 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1467
1468         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1469         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1470         (RTT): Remove duplicate.
1471         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1472         (PCT_CONFIG*): Remove.
1473         (D1L, D1H, D2H, D2L): Define.
1474
1475 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1476
1477         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1478
1479 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1480
1481         * arc-tbl.h (invld07): Remove.
1482         * arc-ext-tbl.h: New file.
1483         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1484         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1485
1486 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1487
1488         Fix -Wstack-usage warnings.
1489         * aarch64-dis.c (print_operands): Substitute size.
1490         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1491
1492 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1493
1494         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1495         to get a proper diagnostic when an invalid ASR register is used.
1496
1497 2016-03-22  Nick Clifton  <nickc@redhat.com>
1498
1499         * configure: Regenerate.
1500
1501 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1502
1503         * arc-nps400-tbl.h: New file.
1504         * arc-opc.c: Add top level comment.
1505         (insert_nps_3bit_dst): New function.
1506         (extract_nps_3bit_dst): New function.
1507         (insert_nps_3bit_src2): New function.
1508         (extract_nps_3bit_src2): New function.
1509         (insert_nps_bitop_size): New function.
1510         (extract_nps_bitop_size): New function.
1511         (arc_flag_operands): Add nps400 entries.
1512         (arc_flag_classes): Add nps400 entries.
1513         (arc_operands): Add nps400 entries.
1514         (arc_opcodes): Add nps400 include.
1515
1516 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1517
1518         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1519         the new class enum values.
1520
1521 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1522
1523         * arc-dis.c (print_insn_arc): Handle nps400.
1524
1525 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1526
1527         * arc-opc.c (BASE): Delete.
1528
1529 2016-03-18  Nick Clifton  <nickc@redhat.com>
1530
1531         PR target/19721
1532         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1533         of MOV insn that aliases an ORR insn.
1534
1535 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1536
1537         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1538
1539 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1540
1541         * mcore-opc.h: Add const qualifiers.
1542         * microblaze-opc.h (struct op_code_struct): Likewise.
1543         * sh-opc.h: Likewise.
1544         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1545         (tic4x_print_op): Likewise.
1546
1547 2016-03-02  Alan Modra  <amodra@gmail.com>
1548
1549         * or1k-desc.h: Regenerate.
1550         * fr30-ibld.c: Regenerate.
1551         * rl78-decode.c: Regenerate.
1552
1553 2016-03-01  Nick Clifton  <nickc@redhat.com>
1554
1555         PR target/19747
1556         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1557
1558 2016-02-24  Renlin Li  <renlin.li@arm.com>
1559
1560         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1561         (print_insn_coprocessor): Support fp16 instructions.
1562
1563 2016-02-24  Renlin Li  <renlin.li@arm.com>
1564
1565         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1566         vminnm, vrint(mpna).
1567
1568 2016-02-24  Renlin Li  <renlin.li@arm.com>
1569
1570         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1571         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1572
1573 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1574
1575         * i386-dis.c (print_insn): Parenthesize expression to prevent
1576         truncated addresses.
1577         (OP_J): Likewise.
1578
1579 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1580             Janek van Oirschot  <jvanoirs@synopsys.com>
1581
1582         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1583         variable.
1584
1585 2016-02-04  Nick Clifton  <nickc@redhat.com>
1586
1587         PR target/19561
1588         * msp430-dis.c (print_insn_msp430): Add a special case for
1589         decoding an RRC instruction with the ZC bit set in the extension
1590         word.
1591
1592 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1593
1594         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1595         * epiphany-ibld.c: Regenerate.
1596         * fr30-ibld.c: Regenerate.
1597         * frv-ibld.c: Regenerate.
1598         * ip2k-ibld.c: Regenerate.
1599         * iq2000-ibld.c: Regenerate.
1600         * lm32-ibld.c: Regenerate.
1601         * m32c-ibld.c: Regenerate.
1602         * m32r-ibld.c: Regenerate.
1603         * mep-ibld.c: Regenerate.
1604         * mt-ibld.c: Regenerate.
1605         * or1k-ibld.c: Regenerate.
1606         * xc16x-ibld.c: Regenerate.
1607         * xstormy16-ibld.c: Regenerate.
1608
1609 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1610
1611         * epiphany-dis.c: Regenerated from latest cpu files.
1612
1613 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1614
1615         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1616         test bit.
1617
1618 2016-01-25  Renlin Li  <renlin.li@arm.com>
1619
1620         * arm-dis.c (mapping_symbol_for_insn): New function.
1621         (find_ifthen_state): Call mapping_symbol_for_insn().
1622
1623 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1624
1625         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1626         of MSR UAO immediate operand.
1627
1628 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1629
1630         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1631         instruction support.
1632
1633 2016-01-17  Alan Modra  <amodra@gmail.com>
1634
1635         * configure: Regenerate.
1636
1637 2016-01-14  Nick Clifton  <nickc@redhat.com>
1638
1639         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1640         instructions that can support stack pointer operations.
1641         * rl78-decode.c: Regenerate.
1642         * rl78-dis.c: Fix display of stack pointer in MOVW based
1643         instructions.
1644
1645 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1646
1647         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1648         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1649         erxtatus_el1 and erxaddr_el1.
1650
1651 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1652
1653         * arm-dis.c (arm_opcodes): Add "esb".
1654         (thumb_opcodes): Likewise.
1655
1656 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1657
1658         * ppc-opc.c <xscmpnedp>: Delete.
1659         <xvcmpnedp>: Likewise.
1660         <xvcmpnedp.>: Likewise.
1661         <xvcmpnesp>: Likewise.
1662         <xvcmpnesp.>: Likewise.
1663
1664 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1665
1666         PR gas/13050
1667         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1668         addition to ISA_A.
1669
1670 2016-01-01  Alan Modra  <amodra@gmail.com>
1671
1672         Update year range in copyright notice of all files.
1673
1674 For older changes see ChangeLog-2015
1675 \f
1676 Copyright (C) 2016 Free Software Foundation, Inc.
1677
1678 Copying and distribution of this file, with or without modification,
1679 are permitted in any medium without royalty provided the copyright
1680 notice and this notice are preserved.
1681
1682 Local Variables:
1683 mode: change-log
1684 left-margin: 8
1685 fill-column: 74
1686 version-control: never
1687 End: