opcodes/ChangeLog

   1 2020-06-01  Alan Modra  <amodra@gmail.com>
   2
   3         * bpf-desc.c: Regenerate.
   4
   5 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
   6             David Faust <david.faust@oracle.com>
   7
   8         * bpf-desc.c: Regenerate.
   9         * bpf-opc.h: Likewise.
  10         * bpf-opc.c: Likewise.
  11         * bpf-dis.c: Likewise.
  12
  13 2020-05-28  Alan Modra  <amodra@gmail.com>
  14
  15         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
  16         values.
  17
  18 2020-05-28  Alan Modra  <amodra@gmail.com>
  19
  20         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
  21         immediates.
  22         (print_insn_ns32k): Revert last change.
  23
  24 2020-05-28  Nick Clifton  <nickc@redhat.com>
  25
  26         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
  27         static.
  28
  29 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
  30
  31         Fix extraction of signed constants in nios2 disassembler (again).
  32
  33         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
  34         extractions of signed fields.
  35
  36 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
  37
  38         * s390-opc.txt: Relocate vector load/store instructions with
  39         additional alignment parameter and change architecture level
  40         constraint from z14 to z13.
  41
  42 2020-05-21  Alan Modra  <amodra@gmail.com>
  43
  44         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
  45         * sparc-dis.c: Likewise.
  46         * tic4x-dis.c: Likewise.
  47         * xtensa-dis.c: Likewise.
  48         * bpf-desc.c: Regenerate.
  49         * epiphany-desc.c: Regenerate.
  50         * fr30-desc.c: Regenerate.
  51         * frv-desc.c: Regenerate.
  52         * ip2k-desc.c: Regenerate.
  53         * iq2000-desc.c: Regenerate.
  54         * lm32-desc.c: Regenerate.
  55         * m32c-desc.c: Regenerate.
  56         * m32r-desc.c: Regenerate.
  57         * mep-asm.c: Regenerate.
  58         * mep-desc.c: Regenerate.
  59         * mt-desc.c: Regenerate.
  60         * or1k-desc.c: Regenerate.
  61         * xc16x-desc.c: Regenerate.
  62         * xstormy16-desc.c: Regenerate.
  63
  64 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
  65
  66         * riscv-opc.c (riscv_ext_version_table): The table used to store
  67         all information about the supported spec and the corresponding ISA
  68         versions.  Currently, only Zicsr is supported to verify the
  69         correctness of Z sub extension settings.  Others will be supported
  70         in the future patches.
  71         (struct isa_spec_t, isa_specs): List for all supported ISA spec
  72         classes and the corresponding strings.
  73         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
  74         spec class by giving a ISA spec string.
  75         * riscv-opc.c (struct priv_spec_t): New structure.
  76         (struct priv_spec_t priv_specs): List for all supported privilege spec
  77         classes and the corresponding strings.
  78         (riscv_get_priv_spec_class): New function.  Get the corresponding
  79         privilege spec class by giving a spec string.
  80         (riscv_get_priv_spec_name): New function.  Get the corresponding
  81         privilege spec string by giving a CSR version class.
  82         * riscv-dis.c: Updated since DECLARE_CSR is changed.
  83         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
  84         according to the chosen version.  Build a hash table riscv_csr_hash to
  85         store the valid CSR for the chosen pirv verison.  Dump the direct
  86         CSR address rather than it's name if it is invalid.
  87         (parse_riscv_dis_option_without_args): New function.  Parse the options
  88         without arguments.
  89         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
  90         parse the options without arguments first, and then handle the options
  91         with arguments.  Add the new option -Mpriv-spec, which has argument.
  92         * riscv-dis.c (print_riscv_disassembler_options): Add description
  93         about the new OBJDUMP option.
  94
  95 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
  96
  97         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
  98         WC values on POWER10 sync, dcbf  and wait instructions.
  99         (insert_pl, extract_pl): New functions.
 100         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 101         (LS3): New , 3-bit L for sync.
 102         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 103         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 104         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 105         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 106         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 107         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 108         <wait>: Enable PL operand on POWER10.
 109         <dcbf>: Enable L3OPT operand on POWER10.
 110         <sync>: Enable SC2 operand on POWER10.
 111
 112 2020-05-19  Stafford Horne  <shorne@gmail.com>
 113
 114         PR 25184
 115         * or1k-asm.c: Regenerate.
 116         * or1k-desc.c: Regenerate.
 117         * or1k-desc.h: Regenerate.
 118         * or1k-dis.c: Regenerate.
 119         * or1k-ibld.c: Regenerate.
 120         * or1k-opc.c: Regenerate.
 121         * or1k-opc.h: Regenerate.
 122         * or1k-opinst.c: Regenerate.
 123
 124 2020-05-11  Alan Modra  <amodra@gmail.com>
 125
 126         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 127         xsmaxcqp, xsmincqp.
 128
 129 2020-05-11  Alan Modra  <amodra@gmail.com>
 130
 131         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 132         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 133
 134 2020-05-11  Alan Modra  <amodra@gmail.com>
 135
 136         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 137
 138 2020-05-11  Alan Modra  <amodra@gmail.com>
 139
 140         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 141         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 142
 143 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 144
 145         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 146         mnemonics.
 147
 148 2020-05-11  Alan Modra  <amodra@gmail.com>
 149
 150         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 151         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 152         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 153         (prefix_opcodes): Add xxeval.
 154
 155 2020-05-11  Alan Modra  <amodra@gmail.com>
 156
 157         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 158         xxgenpcvwm, xxgenpcvdm.
 159
 160 2020-05-11  Alan Modra  <amodra@gmail.com>
 161
 162         * ppc-opc.c (MP, VXVAM_MASK): Define.
 163         (VXVAPS_MASK): Use VXVA_MASK.
 164         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 165         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 166         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 167         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 168
 169 2020-05-11  Alan Modra  <amodra@gmail.com>
 170             Peter Bergner  <bergner@linux.ibm.com>
 171
 172         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 173         New functions.
 174         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 175         YMSK2, XA6a, XA6ap, XB6a entries.
 176         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 177         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 178         (PPCVSX4): Define.
 179         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 180         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 181         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 182         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 183         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 184         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 185         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 186         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 187         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 188         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 189         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 190         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 191         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 192         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 193
 194 2020-05-11  Alan Modra  <amodra@gmail.com>
 195
 196         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 197         (insert_xts, extract_xts): New functions.
 198         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 199         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 200         (VXRC_MASK, VXSH_MASK): Define.
 201         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 202         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 203         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 204         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 205         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 206         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 207         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 208
 209 2020-05-11  Alan Modra  <amodra@gmail.com>
 210
 211         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 212         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 213         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 214         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 215         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 216
 217 2020-05-11  Alan Modra  <amodra@gmail.com>
 218
 219         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 220         (XTP, DQXP, DQXP_MASK): Define.
 221         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 222         (prefix_opcodes): Add plxvp and pstxvp.
 223
 224 2020-05-11  Alan Modra  <amodra@gmail.com>
 225
 226         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 227         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 228         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 229
 230 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 231
 232         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 233
 234 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 235
 236         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 237         (L1OPT): Define.
 238         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 239
 240 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 241
 242         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 243
 244 2020-05-11  Alan Modra  <amodra@gmail.com>
 245
 246         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 247
 248 2020-05-11  Alan Modra  <amodra@gmail.com>
 249
 250         * ppc-dis.c (ppc_opts): Add "power10" entry.
 251         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 252         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 253
 254 2020-05-11  Nick Clifton  <nickc@redhat.com>
 255
 256         * po/fr.po: Updated French translation.
 257
 258 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 259
 260         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 261         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 262         (operand_general_constraint_met_p): validate
 263         AARCH64_OPND_UNDEFINED.
 264         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 265         for FLD_imm16_2.
 266         * aarch64-asm-2.c: Regenerated.
 267         * aarch64-dis-2.c: Regenerated.
 268         * aarch64-opc-2.c: Regenerated.
 269
 270 2020-04-29  Nick Clifton  <nickc@redhat.com>
 271
 272         PR 22699
 273         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 274         and SETRC insns.
 275
 276 2020-04-29  Nick Clifton  <nickc@redhat.com>
 277
 278         * po/sv.po: Updated Swedish translation.
 279
 280 2020-04-29  Nick Clifton  <nickc@redhat.com>
 281
 282         PR 22699
 283         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 284         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 285         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 286         IMM0_8U case.
 287
 288 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 289
 290         PR 25848
 291         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 292         cmpi only on m68020up and cpu32.
 293
 294 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 295
 296         * aarch64-asm.c (aarch64_ins_none): New.
 297         * aarch64-asm.h (ins_none): New declaration.
 298         * aarch64-dis.c (aarch64_ext_none): New.
 299         * aarch64-dis.h (ext_none): New declaration.
 300         * aarch64-opc.c (aarch64_print_operand): Update case for
 301         AARCH64_OPND_BARRIER_PSB.
 302         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 303         (AARCH64_OPERANDS): Update inserter/extracter for
 304         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 305         * aarch64-asm-2.c: Regenerated.
 306         * aarch64-dis-2.c: Regenerated.
 307         * aarch64-opc-2.c: Regenerated.
 308
 309 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 310
 311         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 312         (aarch64_feature_ras, RAS): Likewise.
 313         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 314         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 315         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 316         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 317         * aarch64-asm-2.c: Regenerated.
 318         * aarch64-dis-2.c: Regenerated.
 319         * aarch64-opc-2.c: Regenerated.
 320
 321 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 322
 323         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 324         (print_insn_neon): Support disassembly of conditional
 325         instructions.
 326
 327 2020-02-16  David Faust  <david.faust@oracle.com>
 328
 329         * bpf-desc.c: Regenerate.
 330         * bpf-desc.h: Likewise.
 331         * bpf-opc.c: Regenerate.
 332         * bpf-opc.h: Likewise.
 333
 334 2020-04-07  Lili Cui  <lili.cui@intel.com>
 335
 336         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 337         (prefix_table): New instructions (see prefixes above).
 338         (rm_table): Likewise
 339         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 340         CPU_ANY_TSXLDTRK_FLAGS.
 341         (cpu_flags): Add CpuTSXLDTRK.
 342         * i386-opc.h (enum): Add CpuTSXLDTRK.
 343         (i386_cpu_flags): Add cputsxldtrk.
 344         * i386-opc.tbl: Add XSUSPLDTRK insns.
 345         * i386-init.h: Regenerate.
 346         * i386-tbl.h: Likewise.
 347
 348 2020-04-02  Lili Cui  <lili.cui@intel.com>
 349
 350         * i386-dis.c (prefix_table): New instructions serialize.
 351         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 352         CPU_ANY_SERIALIZE_FLAGS.
 353         (cpu_flags): Add CpuSERIALIZE.
 354         * i386-opc.h (enum): Add CpuSERIALIZE.
 355         (i386_cpu_flags): Add cpuserialize.
 356         * i386-opc.tbl: Add SERIALIZE insns.
 357         * i386-init.h: Regenerate.
 358         * i386-tbl.h: Likewise.
 359
 360 2020-03-26  Alan Modra  <amodra@gmail.com>
 361
 362         * disassemble.h (opcodes_assert): Declare.
 363         (OPCODES_ASSERT): Define.
 364         * disassemble.c: Don't include assert.h.  Include opintl.h.
 365         (opcodes_assert): New function.
 366         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 367         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 368         calculate maxlen.  Omit insn decoding when insn length exceeds
 369         maxlen.  Exit from nibble loop when looking for E, before
 370         accessing next data byte.  Move processing of E outside loop.
 371         Replace tests of maxlen in loop with assertions.
 372
 373 2020-03-26  Alan Modra  <amodra@gmail.com>
 374
 375         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 376
 377 2020-03-25  Alan Modra  <amodra@gmail.com>
 378
 379         * z80-dis.c (suffix): Init mybuf.
 380
 381 2020-03-22  Alan Modra  <amodra@gmail.com>
 382
 383         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 384         successflly read from section.
 385
 386 2020-03-22  Alan Modra  <amodra@gmail.com>
 387
 388         * arc-dis.c (find_format): Use ISO C string concatenation rather
 389         than line continuation within a string.  Don't access needs_limm
 390         before testing opcode != NULL.
 391
 392 2020-03-22  Alan Modra  <amodra@gmail.com>
 393
 394         * ns32k-dis.c (print_insn_arg): Update comment.
 395         (print_insn_ns32k): Reduce size of index_offset array, and
 396         initialize, passing -1 to print_insn_arg for args that are not
 397         an index.  Don't exit arg loop early.  Abort on bad arg number.
 398
 399 2020-03-22  Alan Modra  <amodra@gmail.com>
 400
 401         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 402         * s12z-opc.c: Formatting.
 403         (operands_f): Return an int.
 404         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 405         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 406         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 407         (exg_sex_discrim): Likewise.
 408         (create_immediate_operand, create_bitfield_operand),
 409         (create_register_operand_with_size, create_register_all_operand),
 410         (create_register_all16_operand, create_simple_memory_operand),
 411         (create_memory_operand, create_memory_auto_operand): Don't
 412         segfault on malloc failure.
 413         (z_ext24_decode): Return an int status, negative on fail, zero
 414         on success.
 415         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 416         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 417         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 418         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 419         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 420         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 421         (loop_primitive_decode, shift_decode, psh_pul_decode),
 422         (bit_field_decode): Similarly.
 423         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 424         to return value, update callers.
 425         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 426         Don't segfault on NULL operand.
 427         (decode_operation): Return OP_INVALID on first fail.
 428         (decode_s12z): Check all reads, returning -1 on fail.
 429
 430 2020-03-20  Alan Modra  <amodra@gmail.com>
 431
 432         * metag-dis.c (print_insn_metag): Don't ignore status from
 433         read_memory_func.
 434
 435 2020-03-20  Alan Modra  <amodra@gmail.com>
 436
 437         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 438         Initialize parts of buffer not written when handling a possible
 439         2-byte insn at end of section.  Don't attempt decoding of such
 440         an insn by the 4-byte machinery.
 441
 442 2020-03-20  Alan Modra  <amodra@gmail.com>
 443
 444         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 445         partially filled buffer.  Prevent lookup of 4-byte insns when
 446         only VLE 2-byte insns are possible due to section size.  Print
 447         ".word" rather than ".long" for 2-byte leftovers.
 448
 449 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 450
 451         PR 25641
 452         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 453
 454 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-dis.c (X86_64_0D): Rename to ...
 457         (X86_64_0E): ... this.
 458
 459 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 462         * Makefile.in: Regenerated.
 463
 464 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 467         3-operand pseudos.
 468         * i386-tbl.h: Re-generate.
 469
 470 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 473         vprot*, vpsha*, and vpshl*.
 474         * i386-tbl.h: Re-generate.
 475
 476 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 479         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 480         * i386-tbl.h: Re-generate.
 481
 482 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 483
 484         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 485         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 486         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 487         * i386-tbl.h: Re-generate.
 488
 489 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-gen.c (struct template_arg, struct template_instance,
 492         struct template_param, struct template, templates,
 493         parse_template, expand_templates): New.
 494         (process_i386_opcodes): Various local variables moved to
 495         expand_templates. Call parse_template and expand_templates.
 496         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 497         * i386-tbl.h: Re-generate.
 498
 499 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 502         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 503         register and memory source templates. Replace VexW= by VexW*
 504         where applicable.
 505         * i386-tbl.h: Re-generate.
 506
 507 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 508
 509         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 510         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 511         * i386-tbl.h: Re-generate.
 512
 513 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 516         * i386-tbl.h: Re-generate.
 517
 518 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 521         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 522         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 523         VexW0 on SSE2AVX variants.
 524         (vmovq): Drop NoRex64 from XMM/XMM variants.
 525         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 526         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 527         applicable use VexW0.
 528         * i386-tbl.h: Re-generate.
 529
 530 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 533         * i386-opc.h (Rex64): Delete.
 534         (struct i386_opcode_modifier): Remove rex64 field.
 535         * i386-opc.tbl (crc32): Drop Rex64.
 536         Replace Rex64 with Size64 everywhere else.
 537         * i386-tbl.h: Re-generate.
 538
 539 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 540
 541         * i386-dis.c (OP_E_memory): Exclude recording of used address
 542         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 543         addressed memory operands for MPX insns.
 544
 545 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 548         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 549         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 550         (ptwrite): Split into non-64-bit and 64-bit forms.
 551         * i386-tbl.h: Re-generate.
 552
 553 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 556         template.
 557         * i386-tbl.h: Re-generate.
 558
 559 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 562         (prefix_table): Move vmmcall here. Add vmgexit.
 563         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 564         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 565         (cpu_flags): Add CpuSEV_ES entry.
 566         * i386-opc.h (CpuSEV_ES): New.
 567         (union i386_cpu_flags): Add cpusev_es field.
 568         * i386-opc.tbl (vmgexit): New.
 569         * i386-init.h, i386-tbl.h: Re-generate.
 570
 571 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 572
 573         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 574         with MnemonicSize.
 575         * i386-opc.h (IGNORESIZE): New.
 576         (DEFAULTSIZE): Likewise.
 577         (IgnoreSize): Removed.
 578         (DefaultSize): Likewise.
 579         (MnemonicSize): New.
 580         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 581         mnemonicsize.
 582         * i386-opc.tbl (IgnoreSize): New.
 583         (DefaultSize): Likewise.
 584         * i386-tbl.h: Regenerated.
 585
 586 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 587
 588         PR 25627
 589         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 590         instructions.
 591
 592 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 593
 594         PR gas/25622
 595         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 596         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 597         * i386-tbl.h: Regenerated.
 598
 599 2020-02-26  Alan Modra  <amodra@gmail.com>
 600
 601         * aarch64-asm.c: Indent labels correctly.
 602         * aarch64-dis.c: Likewise.
 603         * aarch64-gen.c: Likewise.
 604         * aarch64-opc.c: Likewise.
 605         * alpha-dis.c: Likewise.
 606         * i386-dis.c: Likewise.
 607         * nds32-asm.c: Likewise.
 608         * nfp-dis.c: Likewise.
 609         * visium-dis.c: Likewise.
 610
 611 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 612
 613         * arc-regs.h (int_vector_base): Make it available for all ARC
 614         CPUs.
 615
 616 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 617
 618         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 619         changed.
 620
 621 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 622
 623         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 624         c.mv/c.li if rs1 is zero.
 625
 626 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 627
 628         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 629         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 630         CPU_POPCNT_FLAGS.
 631         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 632         * i386-opc.h (CpuABM): Removed.
 633         (CpuPOPCNT): New.
 634         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 635         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 636         popcnt.  Remove CpuABM from lzcnt.
 637         * i386-init.h: Regenerated.
 638         * i386-tbl.h: Likewise.
 639
 640 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 643         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 644         VexW1 instead of open-coding them.
 645         * i386-tbl.h: Re-generate.
 646
 647 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-opc.tbl (AddrPrefixOpReg): Define.
 650         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 651         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 652         templates. Drop NoRex64.
 653         * i386-tbl.h: Re-generate.
 654
 655 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 656
 657         PR gas/6518
 658         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 659         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 660         into Intel syntax instance (with Unpsecified) and AT&T one
 661         (without).
 662         (vcvtneps2bf16): Likewise, along with folding the two so far
 663         separate ones.
 664         * i386-tbl.h: Re-generate.
 665
 666 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 667
 668         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 669         CPU_ANY_SSE4A_FLAGS.
 670
 671 2020-02-17  Alan Modra  <amodra@gmail.com>
 672
 673         * i386-gen.c (cpu_flag_init): Correct last change.
 674
 675 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 676
 677         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 678         CPU_ANY_SSE4_FLAGS.
 679
 680 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 681
 682         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 683         (movzx): Likewise.
 684
 685 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 686
 687         PR gas/25438
 688         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 689         destination for Cpu64-only variant.
 690         (movzx): Fold patterns.
 691         * i386-tbl.h: Re-generate.
 692
 693 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 694
 695         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 696         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 697         CPU_ANY_SSE4_FLAGS entry.
 698         * i386-init.h: Re-generate.
 699
 700 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 703         with Unspecified, making the present one AT&T syntax only.
 704         * i386-tbl.h: Re-generate.
 705
 706 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 709         * i386-tbl.h: Re-generate.
 710
 711 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 712
 713         PR gas/24546
 714         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 715         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 716         Amd64 and Intel64 templates.
 717         (call, jmp): Likewise for far indirect variants. Dro
 718         Unspecified.
 719         * i386-tbl.h: Re-generate.
 720
 721 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 724         * i386-opc.h (ShortForm): Delete.
 725         (struct i386_opcode_modifier): Remove shortform field.
 726         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 727         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 728         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 729         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 730         Drop ShortForm.
 731         * i386-tbl.h: Re-generate.
 732
 733 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 736         fucompi): Drop ShortForm from operand-less templates.
 737         * i386-tbl.h: Re-generate.
 738
 739 2020-02-11  Alan Modra  <amodra@gmail.com>
 740
 741         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 742         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 743         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 744         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 745         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 746
 747 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 748
 749         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 750         (cde_opcodes): Add VCX* instructions.
 751
 752 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 753             Matthew Malcomson  <matthew.malcomson@arm.com>
 754
 755         * arm-dis.c (struct cdeopcode32): New.
 756         (CDE_OPCODE): New macro.
 757         (cde_opcodes): New disassembly table.
 758         (regnames): New option to table.
 759         (cde_coprocs): New global variable.
 760         (print_insn_cde): New
 761         (print_insn_thumb32): Use print_insn_cde.
 762         (parse_arm_disassembler_options): Parse coprocN args.
 763
 764 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 765
 766         PR gas/25516
 767         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 768         with ISA64.
 769         * i386-opc.h (AMD64): Removed.
 770         (Intel64): Likewose.
 771         (AMD64): New.
 772         (INTEL64): Likewise.
 773         (INTEL64ONLY): Likewise.
 774         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 775         * i386-opc.tbl (Amd64): New.
 776         (Intel64): Likewise.
 777         (Intel64Only): Likewise.
 778         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 779         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 780         * i386-tbl.h: Regenerated.
 781
 782 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 783
 784         PR 25469
 785         * z80-dis.c: Add support for GBZ80 opcodes.
 786
 787 2020-02-04  Alan Modra  <amodra@gmail.com>
 788
 789         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 790
 791 2020-02-03  Alan Modra  <amodra@gmail.com>
 792
 793         * m32c-ibld.c: Regenerate.
 794
 795 2020-02-01  Alan Modra  <amodra@gmail.com>
 796
 797         * frv-ibld.c: Regenerate.
 798
 799 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 802         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 803         (OP_E_memory): Replace xmm_mdq_mode case label by
 804         vex_scalar_w_dq_mode one.
 805         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 806
 807 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 810         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 811         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 812         (intel_operand_size): Drop vex_w_dq_mode case label.
 813
 814 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 815
 816         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 817         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 818
 819 2020-01-30  Alan Modra  <amodra@gmail.com>
 820
 821         * m32c-ibld.c: Regenerate.
 822
 823 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 824
 825         * bpf-opc.c: Regenerate.
 826
 827 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 828
 829         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 830         (dis386): Use them to replace C2/C3 table entries.
 831         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 832         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 833         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 834         * i386-tbl.h: Re-generate.
 835
 836 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 839         forms.
 840         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 841         DefaultSize.
 842         * i386-tbl.h: Re-generate.
 843
 844 2020-01-30  Alan Modra  <amodra@gmail.com>
 845
 846         * tic4x-dis.c (tic4x_dp): Make unsigned.
 847
 848 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 849             Jan Beulich  <jbeulich@suse.com>
 850
 851         PR binutils/25445
 852         * i386-dis.c (MOVSXD_Fixup): New function.
 853         (movsxd_mode): New enum.
 854         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 855         (intel_operand_size): Handle movsxd_mode.
 856         (OP_E_register): Likewise.
 857         (OP_G): Likewise.
 858         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 859         register on movsxd.  Add movsxd with 16-bit destination register
 860         for AMD64 and Intel64 ISAs.
 861         * i386-tbl.h: Regenerated.
 862
 863 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 864
 865         PR 25403
 866         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 867         * aarch64-asm-2.c: Regenerate
 868         * aarch64-dis-2.c: Likewise.
 869         * aarch64-opc-2.c: Likewise.
 870
 871 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 872
 873         * i386-opc.tbl (sysret): Drop DefaultSize.
 874         * i386-tbl.h: Re-generate.
 875
 876 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 877
 878         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 879         Dword.
 880         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 881         * i386-tbl.h: Re-generate.
 882
 883 2020-01-20  Nick Clifton  <nickc@redhat.com>
 884
 885         * po/de.po: Updated German translation.
 886         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 887         * po/uk.po: Updated Ukranian translation.
 888
 889 2020-01-20  Alan Modra  <amodra@gmail.com>
 890
 891         * hppa-dis.c (fput_const): Remove useless cast.
 892
 893 2020-01-20  Alan Modra  <amodra@gmail.com>
 894
 895         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 896
 897 2020-01-18  Nick Clifton  <nickc@redhat.com>
 898
 899         * configure: Regenerate.
 900         * po/opcodes.pot: Regenerate.
 901
 902 2020-01-18  Nick Clifton  <nickc@redhat.com>
 903
 904         Binutils 2.34 branch created.
 905
 906 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 907
 908         * opintl.h: Fix spelling error (seperate).
 909
 910 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 911
 912         * i386-opc.tbl: Add {vex} pseudo prefix.
 913         * i386-tbl.h: Regenerated.
 914
 915 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 916
 917         PR 25376
 918         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 919         (neon_opcodes): Likewise.
 920         (select_arm_features): Make sure we enable MVE bits when selecting
 921         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 922         any architecture.
 923
 924 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-opc.tbl: Drop stale comment from XOP section.
 927
 928 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 931         (extractps): Add VexWIG to SSE2AVX forms.
 932         * i386-tbl.h: Re-generate.
 933
 934 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 937         Size64 from and use VexW1 on SSE2AVX forms.
 938         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 939         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 940         * i386-tbl.h: Re-generate.
 941
 942 2020-01-15  Alan Modra  <amodra@gmail.com>
 943
 944         * tic4x-dis.c (tic4x_version): Make unsigned long.
 945         (optab, optab_special, registernames): New file scope vars.
 946         (tic4x_print_register): Set up registernames rather than
 947         malloc'd registertable.
 948         (tic4x_disassemble): Delete optable and optable_special.  Use
 949         optab and optab_special instead.  Throw away old optab,
 950         optab_special and registernames when info->mach changes.
 951
 952 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 953
 954         PR 25377
 955         * z80-dis.c (suffix): Use .db instruction to generate double
 956         prefix.
 957
 958 2020-01-14  Alan Modra  <amodra@gmail.com>
 959
 960         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 961         values to unsigned before shifting.
 962
 963 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 964
 965         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 966         flow instructions.
 967         (print_insn_thumb16, print_insn_thumb32): Likewise.
 968         (print_insn): Initialize the insn info.
 969         * i386-dis.c (print_insn): Initialize the insn info fields, and
 970         detect jumps.
 971
 972 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 973
 974         * arc-opc.c (C_NE): Make it required.
 975
 976 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 977
 978         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 979         reserved register name.
 980
 981 2020-01-13  Alan Modra  <amodra@gmail.com>
 982
 983         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 984         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 985
 986 2020-01-13  Alan Modra  <amodra@gmail.com>
 987
 988         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 989         result of wasm_read_leb128 in a uint64_t and check that bits
 990         are not lost when copying to other locals.  Use uint32_t for
 991         most locals.  Use PRId64 when printing int64_t.
 992
 993 2020-01-13  Alan Modra  <amodra@gmail.com>
 994
 995         * score-dis.c: Formatting.
 996         * score7-dis.c: Formatting.
 997
 998 2020-01-13  Alan Modra  <amodra@gmail.com>
 999
1000         * score-dis.c (print_insn_score48): Use unsigned variables for
1001         unsigned values.  Don't left shift negative values.
1002         (print_insn_score32): Likewise.
1003         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1004
1005 2020-01-13  Alan Modra  <amodra@gmail.com>
1006
1007         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1008
1009 2020-01-13  Alan Modra  <amodra@gmail.com>
1010
1011         * fr30-ibld.c: Regenerate.
1012
1013 2020-01-13  Alan Modra  <amodra@gmail.com>
1014
1015         * xgate-dis.c (print_insn): Don't left shift signed value.
1016         (ripBits): Formatting, use 1u.
1017
1018 2020-01-10  Alan Modra  <amodra@gmail.com>
1019
1020         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1021         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1022
1023 2020-01-10  Alan Modra  <amodra@gmail.com>
1024
1025         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1026         and XRREG value earlier to avoid a shift with negative exponent.
1027         * m10200-dis.c (disassemble): Similarly.
1028
1029 2020-01-09  Nick Clifton  <nickc@redhat.com>
1030
1031         PR 25224
1032         * z80-dis.c (ld_ii_ii): Use correct cast.
1033
1034 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1035
1036         PR 25224
1037         * z80-dis.c (ld_ii_ii): Use character constant when checking
1038         opcode byte value.
1039
1040 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-dis.c (SEP_Fixup): New.
1043         (SEP): Define.
1044         (dis386_twobyte): Use it for sysenter/sysexit.
1045         (enum x86_64_isa): Change amd64 enumerator to value 1.
1046         (OP_J): Compare isa64 against intel64 instead of amd64.
1047         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1048         forms.
1049         * i386-tbl.h: Re-generate.
1050
1051 2020-01-08  Alan Modra  <amodra@gmail.com>
1052
1053         * z8k-dis.c: Include libiberty.h
1054         (instr_data_s): Make max_fetched unsigned.
1055         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1056         Don't exceed byte_info bounds.
1057         (output_instr): Make num_bytes unsigned.
1058         (unpack_instr): Likewise for nibl_count and loop.
1059         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1060         idx unsigned.
1061         * z8k-opc.h: Regenerate.
1062
1063 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1064
1065         * arc-tbl.h (llock): Use 'LLOCK' as class.
1066         (llockd): Likewise.
1067         (scond): Use 'SCOND' as class.
1068         (scondd): Likewise.
1069         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1070         (scondd): Likewise.
1071
1072 2020-01-06  Alan Modra  <amodra@gmail.com>
1073
1074         * m32c-ibld.c: Regenerate.
1075
1076 2020-01-06  Alan Modra  <amodra@gmail.com>
1077
1078         PR 25344
1079         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1080         Peek at next byte to prevent recursion on repeated prefix bytes.
1081         Ensure uninitialised "mybuf" is not accessed.
1082         (print_insn_z80): Don't zero n_fetch and n_used here,..
1083         (print_insn_z80_buf): ..do it here instead.
1084
1085 2020-01-04  Alan Modra  <amodra@gmail.com>
1086
1087         * m32r-ibld.c: Regenerate.
1088
1089 2020-01-04  Alan Modra  <amodra@gmail.com>
1090
1091         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1092
1093 2020-01-04  Alan Modra  <amodra@gmail.com>
1094
1095         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1096
1097 2020-01-04  Alan Modra  <amodra@gmail.com>
1098
1099         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1100
1101 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1102
1103         * aarch64-tbl.h (aarch64_opcode_table): Use
1104         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1105
1106 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1107
1108         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1109         forms of SUDOT and USDOT.
1110
1111 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1112
1113         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1114         uzip{1,2}.
1115         * opcodes/aarch64-dis-2.c: Re-generate.
1116
1117 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1118
1119         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1120         FMMLA encoding.
1121         * opcodes/aarch64-dis-2.c: Re-generate.
1122
1123 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1124
1125         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1126
1127 2020-01-01  Alan Modra  <amodra@gmail.com>
1128
1129         Update year range in copyright notice of all files.
1130
1131 For older changes see ChangeLog-2019
1132 \f
1133 Copyright (C) 2020 Free Software Foundation, Inc.
1134
1135 Copying and distribution of this file, with or without modification,
1136 are permitted in any medium without royalty provided the copyright
1137 notice and this notice are preserved.
1138
1139 Local Variables:
1140 mode: change-log
1141 left-margin: 8
1142 fill-column: 74
1143 version-control: never
1144 End: