opcodes/ChangeLog

   1 2010-10-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-gen.c (opcode_modifiers): Add CheckRegSize.
   4
   5         * i386-opc.h (CheckRegSize): New.
   6         (i386_opcode_modifier): Add checkregsize.
   7
   8         * i386-opc.tbl: Add CheckRegSize to instructions which
   9         require register size check.
  10         * i386-tbl.h: Regenerated.
  11
  12 2010-10-12  Andreas Schwab  <schwab@linux-m68k.org>
  13
  14         * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
  15
  16 2010-10-11  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  17
  18         * s390-opc.c: Make the instruction masks for the load/store on
  19         condition instructions to cover the condition code mask as well.
  20         * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
  21
  22 2010-10-11  Jan Kratochvil  <jan.kratochvil@redhat.com>
  23             Jiang Jilin  <freephp@gmail.com>
  24
  25         * Makefile.am (libopcodes_a_SOURCES): New as empty.
  26         * Makefile.in: Regenerate.
  27
  28 2010-10-09  Matt Rice  <ratmice@gmail.com>
  29
  30         * fr30-desc.h: Regenerate.
  31         * frv-desc.h: Regenerate.
  32         * ip2k-desc.h: Regenerate.
  33         * iq2000-desc.h: Regenerate.
  34         * lm32-desc.h: Regenerate.
  35         * m32c-desc.h: Regenerate.
  36         * m32r-desc.h: Regenerate.
  37         * mep-desc.h: Regenerate.
  38         * mep-opc.c: Regenerate.
  39         * mt-desc.h: Regenerate.
  40         * openrisc-desc.h: Regenerate.
  41         * xc16x-desc.h: Regenerate.
  42         * xstormy16-desc.h: Regenerate.
  43
  44 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
  45
  46         Fix build with -DDEBUG=7
  47         * frv-opc.c: Regenerate.
  48         * or32-dis.c (DEBUG): Don't redefine.
  49         (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
  50         Adapt DEBUG code to some type changes throughout.
  51         * or32-opc.c (or32_extract): Likewise.
  52
  53 2010-10-07  Bernd Schmidt  <bernds@codesourcery.com>
  54
  55         * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
  56         in SPKERNEL instructions.
  57
  58 2010-10-02  H.J. Lu  <hongjiu.lu@intel.com>
  59
  60         PR binutils/12076
  61         * i386-dis.c (RMAL): Remove duplicate.
  62
  63 2010-09-30  Pierre Muller  <muller@ics.u-strasbg.fr>
  64
  65         * s390-mkopc.c (main): Exit with error 1 if sscanf fails
  66         to parse all 6 parameters.
  67
  68 2010-09-28  Pierre Muller  <muller@ics.u-strasbg.fr>
  69
  70         * s390-mkopc.c (main): Change description array size to 80.
  71         Add maximum length of 79 to description parsing.
  72
  73 2010-09-27  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
  74
  75         * configure: Regenerate.
  76
  77 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  78
  79         * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
  80         (main): Recognize the new CPU string.
  81         * s390-opc.c: Add new instruction formats and masks.
  82         * s390-opc.txt: Add new z196 instructions.
  83
  84 2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  85
  86         * s390-dis.c (print_insn_s390): Pick instruction with most
  87         specific mask.
  88         * s390-opc.c: Add unused bits to the insn mask.
  89         * s390-opc.txt: Reorder some instructions to prefer more recent
  90         versions.
  91
  92 2010-09-27  Tejas Belagod  <tejas.belagod@arm.com>
  93
  94         * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
  95         correction to unaligned PCs while printing comment.
  96
  97 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  98
  99         * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
 100         (thumb32_opcodes): Likewise.
 101         (banked_regname): New function.
 102         (print_insn_arm): Add Virtualization Extensions support.
 103         (print_insn_thumb32): Likewise.
 104
 105 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 106
 107         * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
 108         ARM state.
 109
 110 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 111
 112         * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
 113         (thumb32_opcodes): Likewise.
 114
 115 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 116
 117         * arm-dis.c (arm_opcodes): Add support for pldw.
 118         (thumb32_opcodes): Likewise.
 119
 120 2010-09-22  Robin Getz  <robin.getz@analog.com>
 121
 122         * bfin-dis.c (fmtconst): Cast address to 32bits.
 123
 124 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 125
 126         * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
 127
 128 2010-09-22  Robin Getz  <robin.getz@analog.com>
 129
 130         * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
 131         Reject P6/P7 to TESTSET.
 132         (decode_PushPopReg_0): Check for parallel insns.  Reject pushing
 133         SP onto the stack.
 134         (decode_PushPopMultiple_0): Check for parallel insns.  Make sure
 135         P/D fields match all the time.
 136         (decode_CCflag_0): Check for parallel insns.  Verify x/y fields
 137         are 0 for accumulator compares.
 138         (decode_CC2stat_0): Check for parallel insns.  Reject CC<op>CC.
 139         (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
 140         decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
 141         decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 142         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 143         decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
 144         insns.
 145         (decode_dagMODim_0): Verify br field for IREG ops.
 146         (decode_LDST_0): Reject preg load into same preg.
 147         (_print_insn_bfin): Handle returns for ILLEGAL decodes.
 148         (print_insn_bfin): Likewise.
 149
 150 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 151
 152         * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
 153
 154 2010-09-22  Robin Getz  <robin.getz@analog.com>
 155
 156         * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
 157
 158 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 159
 160         * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
 161
 162 2010-09-22  Robin Getz  <robin.getz@analog.com>
 163
 164         * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
 165         register values greater than 8.
 166         (IS_RESERVEDREG, allreg, mostreg): New helpers.
 167         (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
 168         (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
 169         (decode_CC2dreg_0): Check valid CC register number.
 170
 171 2010-09-22  Robin Getz  <robin.getz@analog.com>
 172
 173         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
 174
 175 2010-09-22  Robin Getz  <robin.getz@analog.com>
 176
 177         * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
 178         (reg_names): Likewise.
 179         (decode_statbits): Likewise; while reformatting to make manageable.
 180
 181 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 182
 183         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
 184         (decode_pseudoOChar_0): New function.
 185         (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
 186
 187 2010-09-22  Robin Getz  <robin.getz@analog.com>
 188
 189         * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
 190         LSHIFT instead of SHIFT.
 191
 192 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 193
 194         * bfin-dis.c (constant_formats): Constify the whole structure.
 195         (fmtconst): Add const to return value.
 196         (reg_names): Mark const.
 197         (decode_multfunc): Mark s0/s1 as const.
 198         (decode_macfunc): Mark a/sop as const.
 199
 200 2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>
 201
 202         * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 203
 204 2010-09-14  Maciej W. Rozycki  <macro@codesourcery.com>
 205
 206         * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
 207         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
 208
 209 2010-09-10  Pierre Muller  <muller@ics.u-strasbg.fr>
 210
 211         * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
 212         dlx_insn_type array.
 213
 214 2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         PR binutils/11960
 217         * i386-dis.c (sIv): New.
 218         (dis386): Replace Iq with sIv on "pushT".
 219         (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
 220         (x86_64_table): Replace {T|}/{P|} with P.
 221         (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
 222         (OP_sI): Update v_mode.  Remove w_mode.
 223
 224 2010-08-27  Nathan Froyd  <froydnj@codesourcery.com>
 225
 226         * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
 227         on E500 and E500MC.
 228
 229 2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>
 230
 231         * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
 232         prefetchw.
 233
 234 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 235
 236         * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
 237         to processor flags for PENTIUMPRO processors and later.
 238         * i386-opc.h (enum): Add CpuNop.
 239         (i386_cpu_flags): Add cpunop bit.
 240         * i386-opc.tbl: Change nop cpu_flags.
 241         * i386-init.h: Regenerated.
 242         * i386-tbl.h: Likewise.
 243
 244 2010-08-06  Quentin Neill <quentin.neill@amd.com>
 245
 246         * i386-opc.h (enum): Fix typos in comments.
 247
 248 2010-08-06  Alan Modra  <amodra@gmail.com>
 249
 250         * disassemble.c: Formatting.
 251         (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 252
 253 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
 256         * i386-tbl.h: Regenerated.
 257
 258 2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>
 259
 260         * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
 261
 262         * i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
 263         * i386-tbl.h: Regenerated.
 264
 265 2010-07-29  DJ Delorie  <dj@redhat.com>
 266
 267         * rx-decode.opc (SRR): New.
 268         (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
 269         r0,r0) and NOP3 (max r0,r0) special cases.
 270         * rx-decode.c: Regenerate.
 271
 272 2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
 273
 274         * i386-dis.c: Add 0F to VEX opcode enums.
 275
 276 2010-07-27  DJ Delorie  <dj@redhat.com>
 277
 278         * rx-decode.opc (store_flags): Remove, replace with F_* macros.
 279         (rx_decode_opcode): Likewise.
 280         * rx-decode.c: Regenerate.
 281
 282 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 283             Ina Pandit  <ina.pandit@kpitcummins.com>
 284
 285         * v850-dis.c (v850_sreg_names): Updated structure for system
 286         registers.
 287         (float_cc_names): new structure for condition codes.
 288         (print_value): Update the function that prints value.
 289         (get_operand_value): New function to get the operand value.
 290         (disassemble): Updated to handle the disassembly of instructions.
 291         (print_insn_v850): Updated function to print instruction for different
 292         families.
 293         * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
 294         extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
 295         extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
 296         insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
 297         extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
 298         extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
 299         extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
 300         insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
 301         (insert_d8_7, insert_d5_4, insert_i5div): Remove.
 302         (v850_operands): Update with the relocation name. Also update
 303         the instructions with specific set of processors.
 304
 305 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
 306
 307         * arm-dis.c (print_insn_arm): Add cases for printing more
 308         symbolic operands.
 309         (print_insn_thumb32): Likewise.
 310
 311 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 312
 313         * mips-dis.c (print_insn_mips): Correct branch instruction type
 314         determination.
 315
 316 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 317
 318         * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
 319         type and delay slot determination.
 320         (print_insn_mips16): Extend branch instruction type and delay
 321         slot determination to cover all instructions.
 322         * mips16-opc.c (BR): Remove macro.
 323         (UBR, CBR): New macros.
 324         (mips16_opcodes): Update branch annotation for "b", "beqz",
 325         "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
 326         and "jrc".
 327
 328 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         AVX Programming Reference (June, 2010)
 331         * i386-dis.c (mod_table): Replace rdrnd with rdrand.
 332         * i386-opc.tbl: Likewise.
 333         * i386-tbl.h: Regenerated.
 334
 335 2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 338
 339 2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
 340
 341         * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
 342         ppc_cpu_t before inverting.
 343         (ppc_parse_cpu): Likewise.
 344         (print_insn_powerpc): Likewise.
 345
 346 2010-07-03  Alan Modra  <amodra@gmail.com>
 347
 348         * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
 349         * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
 350         (PPC64, MFDEC2): Update.
 351         (NON32, NO371): Define.
 352         (powerpc_opcode): Update to not use old opcode flags, and avoid
 353         -m601 duplicates.
 354
 355 2010-07-03  DJ Delorie  <dj@delorie.com>
 356
 357         * m32c-ibld.c: Regenerate.
 358
 359 2010-07-03  Alan Modra  <amodra@gmail.com>
 360
 361         * ppc-opc.c (PWR2COM): Define.
 362         (PPCPWR2): Add PPC_OPCODE_COMMON.
 363         (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
 364         "fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
 365         "rac" from -mcom.
 366
 367 2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>
 368
 369         AVX Programming Reference (June, 2010)
 370         * i386-dis.c (PREFIX_0FAE_REG_0): New.
 371         (PREFIX_0FAE_REG_1): Likewise.
 372         (PREFIX_0FAE_REG_2): Likewise.
 373         (PREFIX_0FAE_REG_3): Likewise.
 374         (PREFIX_VEX_3813): Likewise.
 375         (PREFIX_VEX_3A1D): Likewise.
 376         (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 377         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
 378         PREFIX_VEX_3A1D.
 379         (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
 380         (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
 381         PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
 382
 383         * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
 384         CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
 385         (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 386
 387         * i386-opc.h (CpuXsaveopt): New.
 388         (CpuFSGSBase): Likewise.
 389         (CpuRdRnd): Likewise.
 390         (CpuF16C): Likewise.
 391         (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
 392         cpuf16c.
 393
 394         * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
 395         wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 396         * i386-init.h: Regenerated.
 397         * i386-tbl.h: Likewise.
 398
 399 2010-07-01  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 400
 401         * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
 402         and mtocrf on EFS.
 403
 404 2010-06-29  Alan Modra  <amodra@gmail.com>
 405
 406         * maxq-dis.c: Delete file.
 407         * Makefile.am: Remove references to maxq.
 408         * configure.in: Likewise.
 409         * disassemble.c: Likewise.
 410         * Makefile.in: Regenerate.
 411         * configure: Regenerate.
 412         * po/POTFILES.in: Regenerate.
 413
 414 2010-06-29  Alan Modra  <amodra@gmail.com>
 415
 416         * mep-dis.c: Regenerate.
 417
 418 2010-06-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 419
 420         * arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 421
 422 2010-06-27  Alan Modra  <amodra@gmail.com>
 423
 424         * arc-dis.c (arc_sprintf): Delete set but unused variables.
 425         (decodeInstr): Likewise.
 426         * dlx-dis.c (print_insn_dlx): Likewise.
 427         * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
 428         * maxq-dis.c (check_move, print_insn): Likewise.
 429         * mep-dis.c (mep_examine_ivc2_insns): Likewise.
 430         * msp430-dis.c (msp430_branchinstr): Likewise.
 431         * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
 432         * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
 433         * sparc-dis.c (print_insn_sparc): Likewise.
 434         * fr30-asm.c: Regenerate.
 435         * frv-asm.c: Regenerate.
 436         * ip2k-asm.c: Regenerate.
 437         * iq2000-asm.c: Regenerate.
 438         * lm32-asm.c: Regenerate.
 439         * m32c-asm.c: Regenerate.
 440         * m32r-asm.c: Regenerate.
 441         * mep-asm.c: Regenerate.
 442         * mt-asm.c: Regenerate.
 443         * openrisc-asm.c: Regenerate.
 444         * xc16x-asm.c: Regenerate.
 445         * xstormy16-asm.c: Regenerate.
 446
 447 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 448
 449         PR gas/11673
 450         * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
 451
 452 2010-06-16  Vincent Rivière  <vincent.riviere@freesbee.fr>
 453
 454         PR binutils/11676
 455         * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
 456
 457 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 458
 459         * ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
 460         e500x2.  Add PPC_OPCODE_E500 to e500 and e500x2
 461         * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
 462         touch floating point regs and are enabled by COM, PPC or PPCCOM.
 463         Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
 464         Treat lwsync as msync on e500.
 465
 466 2010-06-07  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 467
 468         * arm-dis.c (thumb-opcodes): Add disassembly for movs.
 469
 470 2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 471
 472         * arm-dis.c (print_insn_neon):  Ensure disassembly of Neon
 473         constants is the same on 32-bit and 64-bit hosts.
 474
 475 2010-05-27  Jason Duerstock  <jason.duerstock+binutils@gmail.com>
 476
 477         * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
 478         .short directives so that they can be reassembled.
 479
 480 2010-05-26  Catherine Moore <clm@codesourcery.com>
 481             David Ung  <davidu@mips.com>
 482
 483         * mips-opc.c: Change membership to I1 for instructions ssnop and
 484         ehb.
 485
 486 2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>
 487
 488         * i386-dis.c (sib): New.
 489         (get_sib): Likewise.
 490         (print_insn): Call get_sib.
 491         OP_E_memory): Use sib.
 492
 493 2010-05-26  Catherine Moore  <clm@codesoourcery.com>
 494
 495         * mips-dis.c (mips_arch): Remove INSN_MIPS16.
 496         * mips-opc.c (I16): Remove.
 497         (mips_builtin_op): Reclassify jalx.
 498
 499 2010-05-19  Alan Modra  <amodra@gmail.com>
 500
 501         * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
 502         divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 503
 504 2010-05-13  Alan Modra  <amodra@gmail.com>
 505
 506         * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
 507
 508 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 509
 510         * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
 511         format.
 512         (print_insn_thumb16): Add support for new %W format.
 513
 514 2010-05-07  Tristan Gingold  <gingold@adacore.com>
 515
 516         * Makefile.in: Regenerate with automake 1.11.1.
 517         * aclocal.m4: Ditto.
 518
 519 2010-05-05  Nick Clifton  <nickc@redhat.com>
 520
 521         * po/es.po: Updated Spanish translation.
 522
 523 2010-04-22  Nick Clifton  <nickc@redhat.com>
 524
 525         * po/opcodes.pot: Updated by the Translation project.
 526         * po/vi.po: Updated Vietnamese translation.
 527
 528 2010-04-16  H.J. Lu  <hongjiu.lu@intel.com>
 529
 530         * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
 531         bits in opcode.
 532
 533 2010-04-09  Nick Clifton  <nickc@redhat.com>
 534
 535         * i386-dis.c (print_insn): Remove unused variable op.
 536         (OP_sI): Remove unused variable mask.
 537
 538 2010-04-07  Alan Modra  <amodra@gmail.com>
 539
 540         * configure: Regenerate.
 541
 542 2010-04-06  Peter Bergner  <bergner@vnet.ibm.com>
 543
 544         * ppc-opc.c (RBOPT): New define.
 545         ("dccci"): Enable for PPCA2.  Make operands optional.
 546         ("iccci"): Likewise.  Do not deprecate for PPC476.
 547
 548 2010-04-02  Masaki Muranaka  <monaka@monami-software.com>
 549
 550         * cr16-opc.c (cr16_instruction): Fix typo in comment.
 551
 552 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 553
 554         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
 555         * Makefile.in: Regenerate.
 556         * configure.in (bfd_tic6x_arch): New.
 557         * configure: Regenerate.
 558         * disassemble.c (ARCH_tic6x): Define if ARCH_all.
 559         (disassembler): Handle TI C6X.
 560         * tic6x-dis.c: New.
 561
 562 2010-03-24  Mike Frysinger  <vapier@gentoo.org>
 563
 564         * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
 565
 566 2010-03-23  Joseph Myers  <joseph@codesourcery.com>
 567
 568         * dis-buf.c (buffer_read_memory): Give error for reading just
 569         before the start of memory.
 570
 571 2010-03-22  Sebastian Pop  <sebastian.pop@amd.com>
 572             Quentin Neill <quentin.neill@amd.com>
 573
 574         * i386-dis.c (OP_LWP_I): Removed.
 575         (reg_table): Do not use OP_LWP_I, use Iq.
 576         (OP_LWPCB_E): Remove use of names16.
 577         (OP_LWP_E): Same.
 578         * i386-opc.tbl: Removed 16bit LWP insns.  32bit LWP insns
 579         should not set the Vex.length bit.
 580         * i386-tbl.h: Regenerated.
 581
 582 2010-02-25  Edmar Wienskoski  <edmar@freescale.com>
 583
 584         * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
 585
 586 2010-02-24  Nick Clifton  <nickc@redhat.com>
 587
 588         PR binutils/6773
 589         * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
 590         <prefix>asx.  Replace <prefix>subaddx with <prefix>sax.
 591         (thumb32_opcodes): Likewise.
 592
 593 2010-02-15  Nick Clifton  <nickc@redhat.com>
 594
 595         * po/vi.po: Updated Vietnamese translation.
 596
 597 2010-02-12  Doug Evans  <dje@sebabeach.org>
 598
 599         * lm32-opinst.c: Regenerate.
 600
 601 2010-02-11  Doug Evans  <dje@sebabeach.org>
 602
 603         * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
 604         (print_address): Delete CGEN_PRINT_ADDRESS.
 605         * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
 606         * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
 607         * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
 608         * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
 609
 610         * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
 611         * frv-desc.c, * frv-desc.h, * frv-opc.c,
 612         * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
 613         * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
 614         * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
 615         * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
 616         * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
 617         * mep-desc.c, * mep-desc.h, * mep-opc.c,
 618         * mt-desc.c, * mt-desc.h, * mt-opc.c,
 619         * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
 620         * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
 621         * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
 622
 623 2010-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 624
 625         * i386-dis.c: Update copyright.
 626         * i386-gen.c: Likewise.
 627         * i386-opc.h: Likewise.
 628         * i386-opc.tbl: Likewise.
 629
 630 2010-02-10  Quentin Neill  <quentin.neill@amd.com>
 631             Sebastian Pop  <sebastian.pop@amd.com>
 632
 633         * i386-dis.c (OP_EX_VexImmW): Reintroduced
 634         function to handle 5th imm8 operand.
 635         (PREFIX_VEX_3A48): Added.
 636         (PREFIX_VEX_3A49): Added.
 637         (VEX_W_3A48_P_2): Added.
 638         (VEX_W_3A49_P_2): Added.
 639         (prefix table): Added entries for PREFIX_VEX_3A48
 640         and PREFIX_VEX_3A49.
 641         (vex table): Added entries for VEX_W_3A48_P_2 and
 642         and VEX_W_3A49_P_2.
 643         * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
 644         for Vec_Imm4 operands.
 645         * i386-opc.h (enum): Added Vec_Imm4.
 646         (i386_operand_type): Added vec_imm4.
 647         * i386-opc.tbl: Add entries for vpermilp[ds].
 648         * i386-init.h: Regenerated.
 649         * i386-tbl.h: Regenerated.
 650
 651 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 652
 653         * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
 654         and "pwr7".  Move "a2" into alphabetical order.
 655
 656 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 657
 658         * ppc-dis.c (ppc_opts): Add titan entry.
 659         * ppc-opc.c (TITAN, MULHW): Define.
 660         (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
 661
 662 2010-02-03  Quentin Neill  <quentin.neill@amd.com>
 663
 664         * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
 665         to CPU_BDVER1_FLAGS
 666         * i386-init.h: Regenerated.
 667
 668 2010-02-03  Anthony Green  <green@moxielogic.com>
 669
 670         * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
 671         0x0f, and make 0x00 an illegal instruction.
 672
 673 2010-01-29  Daniel Jacobowitz  <dan@codesourcery.com>
 674
 675         * opcodes/arm-dis.c (struct arm_private_data): New.
 676         (print_insn_coprocessor, print_insn_arm): Update to use struct
 677         arm_private_data.
 678         (is_mapping_symbol, get_map_sym_type): New functions.
 679         (get_sym_code_type): Check the symbol's section.  Do not check
 680         mapping symbols.
 681         (print_insn): Default to disassembling ARM mode code.  Check
 682         for mapping symbols separately from other symbols.  Use
 683         struct arm_private_data.
 684
 685 2010-01-28  H.J. Lu  <hongjiu.lu@intel.com>
 686
 687         * i386-dis.c (EXVexWdqScalar): New.
 688         (vex_scalar_w_dq_mode): Likewise.
 689         (prefix_table): Update entries for PREFIX_VEX_3899,
 690         PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
 691         PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
 692         PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
 693         PREFIX_VEX_38BD and PREFIX_VEX_38BF.
 694         (intel_operand_size): Handle vex_scalar_w_dq_mode.
 695         (OP_EX): Likewise.
 696
 697 2010-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 698
 699         * i386-dis.c (XMScalar): New.
 700         (EXdScalar): Likewise.
 701         (EXqScalar): Likewise.
 702         (EXqScalarS): Likewise.
 703         (VexScalar): Likewise.
 704         (EXdVexScalarS): Likewise.
 705         (EXqVexScalarS): Likewise.
 706         (XMVexScalar): Likewise.
 707         (scalar_mode): Likewise.
 708         (d_scalar_mode): Likewise.
 709         (d_scalar_swap_mode): Likewise.
 710         (q_scalar_mode): Likewise.
 711         (q_scalar_swap_mode): Likewise.
 712         (vex_scalar_mode): Likewise.
 713         (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
 714         VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
 715         VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
 716         VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
 717         VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
 718         VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
 719         VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
 720         VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
 721         VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
 722         VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
 723         (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
 724         VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
 725         VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
 726         VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
 727         VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
 728         VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
 729         VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
 730         VEX_W_7E_P_1, VEX_W_D6_P_2  VEX_W_C2_P_1, VEX_W_C2_P_3,
 731         VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
 732         (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
 733         q_scalar_mode, q_scalar_swap_mode.
 734         (OP_XMM): Handle scalar_mode.
 735         (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
 736         and q_scalar_swap_mode.
 737         (OP_VEX): Handle vex_scalar_mode.
 738
 739 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 740
 741         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 742
 743 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 744
 745         * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
 746
 747 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
 750
 751 2010-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 752
 753         * i386-dis.c (Bad_Opcode): New.
 754         (bad_opcode): Likewise.
 755         (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
 756         (dis386_twobyte): Likewise.
 757         (reg_table): Likewise.
 758         (prefix_table): Likewise.
 759         (x86_64_table): Likewise.
 760         (vex_len_table): Likewise.
 761         (vex_w_table): Likewise.
 762         (mod_table): Likewise.
 763         (rm_table): Likewise.
 764         (float_reg): Likewise.
 765         (reg_table): Remove trailing "(bad)" entries.
 766         (prefix_table): Likewise.
 767         (x86_64_table): Likewise.
 768         (vex_len_table): Likewise.
 769         (vex_w_table): Likewise.
 770         (mod_table): Likewise.
 771         (rm_table): Likewise.
 772         (get_valid_dis386): Handle bytemode 0.
 773
 774 2010-01-23  H.J. Lu  <hongjiu.lu@intel.com>
 775
 776         * i386-opc.h (VEXScalar): New.
 777
 778         * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
 779         instructions.
 780         * i386-tbl.h: Regenerated.
 781
 782 2010-01-21  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
 785
 786         * i386-opc.tbl: Add xsave64 and xrstor64.
 787         * i386-tbl.h: Regenerated.
 788
 789 2010-01-20  Nick Clifton  <nickc@redhat.com>
 790
 791         PR 11170
 792         * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
 793         based post-indexed addressing.
 794
 795 2010-01-15  Sebastian Pop  <sebastian.pop@amd.com>
 796
 797         * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
 798         * i386-tbl.h: Regenerated.
 799
 800 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 801
 802         * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
 803         comments.
 804
 805 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         * i386-dis.c (names_mm): New.
 808         (intel_names_mm): Likewise.
 809         (att_names_mm): Likewise.
 810         (names_xmm): Likewise.
 811         (intel_names_xmm): Likewise.
 812         (att_names_xmm): Likewise.
 813         (names_ymm): Likewise.
 814         (intel_names_ymm): Likewise.
 815         (att_names_ymm): Likewise.
 816         (print_insn): Set names_mm, names_xmm and names_ymm.
 817         (OP_MMX): Use names_mm, names_xmm and names_ymm.
 818         (OP_XMM): Likewise.
 819         (OP_EM): Likewise.
 820         (OP_EMC): Likewise.
 821         (OP_MXC): Likewise.
 822         (OP_EX): Likewise.
 823         (XMM_Fixup): Likewise.
 824         (OP_VEX): Likewise.
 825         (OP_EX_VexReg): Likewise.
 826         (OP_Vex_2src): Likewise.
 827         (OP_Vex_2src_1): Likewise.
 828         (OP_Vex_2src_2): Likewise.
 829         (OP_REG_VexI4): Likewise.
 830
 831 2010-01-13  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         * i386-dis.c (print_insn): Update comments.
 834
 835 2010-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         * i386-dis.c (rex_original): Removed.
 838         (ckprefix): Remove rex_original.
 839         (print_insn): Update comments.
 840
 841 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 842
 843         * Makefile.in: Regenerate.
 844         * configure: Regenerate.
 845
 846 2010-01-07  Doug Evans  <dje@sebabeach.org>
 847
 848         * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
 849         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 850         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 851         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 852         * xstormy16-ibld.c: Regenerate.
 853
 854 2010-01-06  Quentin Neill  <quentin.neill@amd.com>
 855
 856         * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
 857         * i386-init.h: Regenerated.
 858
 859 2010-01-06  Daniel Gutson  <dgutson@codesourcery.com>
 860
 861         * arm-dis.c (print_insn): Fixed search for next symbol and data
 862         dumping condition, and the initial mapping symbol state.
 863
 864 2010-01-05  Doug Evans  <dje@sebabeach.org>
 865
 866         * cgen-ibld.in: #include "cgen/basic-modes.h".
 867         * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
 868         * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
 869         * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
 870         * xstormy16-ibld.c: Regenerate.
 871
 872 2010-01-04  Nick Clifton  <nickc@redhat.com>
 873
 874         PR 11123
 875         * arm-dis.c (print_insn_coprocessor): Initialise value.
 876
 877 2010-01-04  Edmar Wienskoski  <edmar@freescale.com>
 878
 879         * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
 880
 881 2010-01-02  Doug Evans  <dje@sebabeach.org>
 882
 883         * cgen-asm.in: Update copyright year.
 884         * cgen-dis.in: Update copyright year.
 885         * cgen-ibld.in: Update copyright year.
 886         * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
 887         * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
 888         * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
 889         * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
 890         * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
 891         * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
 892         * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
 893         * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
 894         * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
 895         * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
 896         * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
 897         * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
 898         * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
 899         * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
 900         * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
 901         * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
 902         * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
 903         * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
 904         * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
 905         * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
 906         * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
 907
 908 For older changes see ChangeLog-2009
 909 \f
 910 Local Variables:
 911 mode: change-log
 912 left-margin: 8
 913 fill-column: 74
 914 version-control: never
 915 End: