opcodes/ChangeLog

   1 2019-11-07  Jan Beulich  <jbeulich@suse.com>
   2
   3         PR/gas 25167
   4         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
   5         operand-less forms.
   6         * opcodes/i386-tbl.h: Re-generate.
   7
   8 2019-11-05  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-dis.c (OP_Mwaitx): Delete.
  11         (prefix_table): Use OP_Mwait for mwaitx entry.
  12         (OP_Mwait): Also handle mwaitx.
  13
  14 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
  17         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
  18         (prefix_table): Add respective entries.
  19         (rm_table): Link to those entries.
  20
  21 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
  24         (REG_0F1C_P_0_MOD_0): ... this.
  25         (REG_0F1E_MOD_3): Rename to ...
  26         (REG_0F1E_P_1_MOD_3): ... this.
  27         (RM_0F01_REG_5): Rename to ...
  28         (RM_0F01_REG_5_MOD_3): ... this.
  29         (RM_0F01_REG_7): Rename to ...
  30         (RM_0F01_REG_7_MOD_3): ... this.
  31         (RM_0F1E_MOD_3_REG_7): Rename to ...
  32         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
  33         (RM_0FAE_REG_6): Rename to ...
  34         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
  35         (RM_0FAE_REG_7): Rename to ...
  36         (RM_0FAE_REG_7_MOD_3): ... this.
  37         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
  38         (PREFIX_0F01_REG_5_MOD_0): ... this.
  39         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
  40         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
  41         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
  42         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
  43         (PREFIX_0FAE_REG_0): Rename to ...
  44         (PREFIX_0FAE_REG_0_MOD_3): ... this.
  45         (PREFIX_0FAE_REG_1): Rename to ...
  46         (PREFIX_0FAE_REG_1_MOD_3): ... this.
  47         (PREFIX_0FAE_REG_2): Rename to ...
  48         (PREFIX_0FAE_REG_2_MOD_3): ... this.
  49         (PREFIX_0FAE_REG_3): Rename to ...
  50         (PREFIX_0FAE_REG_3_MOD_3): ... this.
  51         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
  52         (PREFIX_0FAE_REG_4_MOD_0): ... this.
  53         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
  54         (PREFIX_0FAE_REG_4_MOD_3): ... this.
  55         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
  56         (PREFIX_0FAE_REG_5_MOD_0): ... this.
  57         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
  58         (PREFIX_0FAE_REG_5_MOD_3): ... this.
  59         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
  60         (PREFIX_0FAE_REG_6_MOD_0): ... this.
  61         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
  62         (PREFIX_0FAE_REG_6_MOD_3): ... this.
  63         (PREFIX_0FAE_REG_7): Rename to ...
  64         (PREFIX_0FAE_REG_7_MOD_0): ... this.
  65         (PREFIX_MOD_0_0FC3): Rename to ...
  66         (PREFIX_0FC3_MOD_0): ... this.
  67         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
  68         (PREFIX_0FC7_REG_6_MOD_0): ... this.
  69         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
  70         (PREFIX_0FC7_REG_6_MOD_3): ... this.
  71         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
  72         (PREFIX_0FC7_REG_7_MOD_3): ... this.
  73         (reg_table, prefix_table, mod_table, rm_table): Adjust
  74         accordingly.
  75
  76 2019-11-04  Nick Clifton  <nickc@redhat.com>
  77
  78         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
  79         of a v850 system register.  Move the v850_sreg_names array into
  80         this function.
  81         (get_v850_reg_name): Likewise for ordinary register names.
  82         (get_v850_vreg_name): Likewise for vector register names.
  83         (get_v850_cc_name): Likewise for condition codes.
  84         * get_v850_float_cc_name): Likewise for floating point condition
  85         codes.
  86         (get_v850_cacheop_name): Likewise for cache-ops.
  87         (get_v850_prefop_name): Likewise for pref-ops.
  88         (disassemble): Use the new accessor functions.
  89
  90 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
  91
  92         * aarch64-opc.c (print_immediate_offset_address): Don't print the
  93         immediate for the writeback form of ldraa/ldrab if it is 0.
  94         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
  95         * aarch64-opc-2.c: Regenerated.
  96
  97 2019-10-30  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-gen.c (operand_type_shorthands): Delete.
 100         (operand_type_init): Expand previous shorthands.
 101         (set_bitfield_from_shorthand): Rename back to ...
 102         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 103         of operand_type_init[].
 104         (set_bitfield): Adjust call to the above function.
 105         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 106         RegXMM, RegYMM, RegZMM): Define.
 107         * i386-reg.tbl: Expand prior shorthands.
 108
 109 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-gen.c (output_i386_opcode): Change order of fields
 112         emitted to output.
 113         * i386-opc.h (struct insn_template): Move operands field.
 114         Convert extension_opcode field to unsigned short.
 115         * i386-tbl.h: Re-generate.
 116
 117 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 120         of W.
 121         * i386-opc.h (W): Extend comment.
 122         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 123         general purpose variants not allowing for byte operands.
 124         * i386-tbl.h: Re-generate.
 125
 126 2019-10-29  Nick Clifton  <nickc@redhat.com>
 127
 128         * tic30-dis.c (print_branch): Correct size of operand array.
 129
 130 2019-10-29  Nick Clifton  <nickc@redhat.com>
 131
 132         * d30v-dis.c (print_insn): Check that operand index is valid
 133         before attempting to access the operands array.
 134
 135 2019-10-29  Nick Clifton  <nickc@redhat.com>
 136
 137         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 138         locating the bit to be tested.
 139
 140 2019-10-29  Nick Clifton  <nickc@redhat.com>
 141
 142         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 143         values.
 144         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 145         (print_insn_s12z):  Check for illegal size values.
 146
 147 2019-10-28  Nick Clifton  <nickc@redhat.com>
 148
 149         * csky-dis.c (csky_chars_to_number): Check for a negative
 150         count. Use an unsigned integer to construct the return value.
 151
 152 2019-10-28  Nick Clifton  <nickc@redhat.com>
 153
 154         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 155         operand buffer.  Set value to 15 not 13.
 156         (get_register_operand): Use OPERAND_BUFFER_LEN.
 157         (get_indirect_operand): Likewise.
 158         (print_two_operand): Likewise.
 159         (print_three_operand): Likewise.
 160         (print_oar_insn): Likewise.
 161
 162 2019-10-28  Nick Clifton  <nickc@redhat.com>
 163
 164         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 165         (bit_extract_simple): Likewise.
 166         (bit_copy): Likewise.
 167         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 168         index_offset array are not accessed.
 169
 170 2019-10-28  Nick Clifton  <nickc@redhat.com>
 171
 172         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 173         operand.
 174
 175 2019-10-25  Nick Clifton  <nickc@redhat.com>
 176
 177         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 178         access to opcodes.op array element.
 179
 180 2019-10-23  Nick Clifton  <nickc@redhat.com>
 181
 182         * rx-dis.c (get_register_name): Fix spelling typo in error
 183         message.
 184         (get_condition_name, get_flag_name, get_double_register_name)
 185         (get_double_register_high_name, get_double_register_low_name)
 186         (get_double_control_register_name, get_double_condition_name)
 187         (get_opsize_name, get_size_name): Likewise.
 188
 189 2019-10-22  Nick Clifton  <nickc@redhat.com>
 190
 191         * rx-dis.c (get_size_name): New function.  Provides safe
 192         access to name array.
 193         (get_opsize_name): Likewise.
 194         (print_insn_rx): Use the accessor functions.
 195
 196 2019-10-16  Nick Clifton  <nickc@redhat.com>
 197
 198         * rx-dis.c (get_register_name): New function.  Provides safe
 199         access to name array.
 200         (get_condition_name, get_flag_name, get_double_register_name)
 201         (get_double_register_high_name, get_double_register_low_name)
 202         (get_double_control_register_name, get_double_condition_name):
 203         Likewise.
 204         (print_insn_rx): Use the accessor functions.
 205
 206 2019-10-09  Nick Clifton  <nickc@redhat.com>
 207
 208         PR 25041
 209         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 210         instructions.
 211
 212 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 213
 214         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 215         (cmpsd): Likewise. Move EsSeg to other operand.
 216         * opcodes/i386-tbl.h: Re-generate.
 217
 218 2019-09-23  Alan Modra  <amodra@gmail.com>
 219
 220         * m68k-dis.c: Include cpu-m68k.h
 221
 222 2019-09-23  Alan Modra  <amodra@gmail.com>
 223
 224         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 225         "elf/mips.h" earlier.
 226
 227 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 228
 229         PR gas/25012
 230         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 231         with SReg operand.
 232         * i386-tbl.h: Re-generate.
 233
 234 2019-09-18  Alan Modra  <amodra@gmail.com>
 235
 236         * arc-ext.c: Update throughout for bfd section macro changes.
 237
 238 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 239
 240         * Makefile.in: Re-generate.
 241         * configure: Re-generate.
 242
 243 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 244
 245         * riscv-opc.c (riscv_opcodes): Change subset field
 246         to insn_class field for all instructions.
 247         (riscv_insn_types): Likewise.
 248
 249 2019-09-16  Phil Blundell  <pb@pbcl.net>
 250
 251         * configure: Regenerated.
 252
 253 2019-09-10  Miod Vallat  <miod@online.fr>
 254
 255         PR 24982
 256         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 257
 258 2019-09-09  Phil Blundell  <pb@pbcl.net>
 259
 260         binutils 2.33 branch created.
 261
 262 2019-09-03  Nick Clifton  <nickc@redhat.com>
 263
 264         PR 24961
 265         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 266         greater than zero before indexing via (bufcnt -1).
 267
 268 2019-09-03  Nick Clifton  <nickc@redhat.com>
 269
 270         PR 24958
 271         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 272         (MAX_SPEC_REG_NAME_LEN): Define.
 273         (struct mmix_dis_info): Use defined constants for array lengths.
 274         (get_reg_name): New function.
 275         (get_sprec_reg_name): New function.
 276         (print_insn_mmix): Use new functions.
 277
 278 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 279
 280         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 281         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 282         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 283
 284 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 285
 286         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 287         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 288         (aarch64_sys_reg_supported_p): Update checks for the above.
 289
 290 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 291
 292         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 293         cases MVE_SQRSHRL and MVE_UQRSHLL.
 294         (print_insn_mve): Add case for specifier 'k' to check
 295         specific bit of the instruction.
 296
 297 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 298
 299         PR 24854
 300         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 301         encountering an unknown machine type.
 302         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 303         cases return -1 rather than calling abort.
 304
 305 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 308         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 309         IgnoreSize.
 310         * i386-tbl.h: Re-generate.
 311
 312 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 313
 314         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 315         instructions.
 316
 317 2019-07-30  Mel Chen <mel.chen@sifive.com>
 318
 319         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 320         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 321
 322         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 323         fscsr.
 324
 325 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 326
 327         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 328         and MPY class instructions.
 329         (parse_option): Add nps400 option.
 330         (print_arc_disassembler_options): Add nps400 info.
 331
 332 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 333
 334         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 335         (bspop): Likewise.
 336         (modapp): Likewise.
 337         * arc-opc.c (RAD_CHK): Add.
 338         * arc-tbl.h: Regenerate.
 339
 340 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 341
 342         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 343         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 344
 345 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 346
 347         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 348         instructions as UNPREDICTABLE.
 349
 350 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 351
 352         * bpf-desc.c: Regenerated.
 353
 354 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-gen.c (static_assert): Define.
 357         (main): Use it.
 358         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 359         (Opcode_Modifier_Num): ... this.
 360         (Mem): Delete.
 361
 362 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-gen.c (operand_types): Move RegMem ...
 365         (opcode_modifiers): ... here.
 366         * i386-opc.h (RegMem): Move to opcode modifer enum.
 367         (union i386_operand_type): Move regmem field ...
 368         (struct i386_opcode_modifier): ... here.
 369         * i386-opc.tbl (RegMem): Define.
 370         (mov, movq): Move RegMem on segment, control, debug, and test
 371         register flavors.
 372         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 373         to non-SSE2AVX flavor.
 374         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 375         Move RegMem on register only flavors. Drop IgnoreSize from
 376         legacy encoding flavors.
 377         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 378         flavors.
 379         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 380         register only flavors.
 381         (vmovd): Move RegMem and drop IgnoreSize on register only
 382         flavor. Change opcode and operand order to store form.
 383         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 384
 385 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 388         entries.
 389         * i386-opc.h (SReg2, SReg3): Replace by ...
 390         (SReg): ... this.
 391         (union i386_operand_type): Replace sreg fields.
 392         * i386-opc.tbl (mov, ): Use SReg.
 393         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 394         register flavors.
 395         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 396         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 397
 398 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 399
 400         * bpf-desc.c: Regenerate.
 401         * bpf-opc.c: Likewise.
 402         * bpf-opc.h: Likewise.
 403
 404 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 405
 406         * bpf-desc.c: Regenerate.
 407         * bpf-opc.c: Likewise.
 408
 409 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 410
 411         * arm-dis.c (print_insn_coprocessor): Rename index to
 412         index_operand.
 413
 414 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 415
 416         * riscv-opc.c (riscv_insn_types): Add r4 type.
 417
 418         * riscv-opc.c (riscv_insn_types): Add b and j type.
 419
 420         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 421         format for sb type and correct s type.
 422
 423 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 424
 425         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 426         SVE FMOV alias of FCPY.
 427
 428 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 429
 430         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 431         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 432
 433 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 434
 435         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 436         registers in an instruction prefixed by MOVPRFX.
 437
 438 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 439
 440         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 441         sve_size_13 icode to account for variant behaviour of
 442         pmull{t,b}.
 443         * aarch64-dis-2.c: Regenerate.
 444         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 445         sve_size_13 icode to account for variant behaviour of
 446         pmull{t,b}.
 447         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 448         (OP_SVE_VVV_Q_D): Add new qualifier.
 449         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 450         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 451         AES and those not.
 452
 453 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 454
 455         * opcodes/i386-gen.c (operand_type_init): Remove
 456         OPERAND_TYPE_VEC_IMM4 entry.
 457         (operand_types): Remove Vec_Imm4.
 458         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 459         (union i386_operand_type): Remove vec_imm4.
 460         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 461         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 462
 463 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 464
 465         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 466         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 467         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 468         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 469         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 470         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 471         * i386-tbl.h: Re-generate.
 472
 473 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 476         register operands.
 477         * i386-tbl.h: Re-generate.
 478
 479 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl (C): New.
 482         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 483         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 484         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 485         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 486         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 487         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 488         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 489         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 490         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 491         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 492         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 493         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 494         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 495         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 496         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 497         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 498         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 499         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 500         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 501         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 502         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 503         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 504         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 505         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 506         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 507         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 508         flavors.
 509         * i386-tbl.h: Re-generate.
 510
 511 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 514         register operands.
 515         * i386-tbl.h: Re-generate.
 516
 517 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 520         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 521         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 522         * i386-tbl.h: Re-generate.
 523
 524 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 527         Disp8MemShift from register only templates.
 528         * i386-tbl.h: Re-generate.
 529
 530 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 533         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 534         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 535         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 536         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 537         EVEX_W_0F11_P_3_M_1): Delete.
 538         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 539         EVEX_W_0F11_P_3): New.
 540         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 541         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 542         MOD_EVEX_0F11_PREFIX_3 table entries.
 543         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 544         PREFIX_EVEX_0F11 table entries.
 545         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 546         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 547         EVEX_W_0F11_P_3_M_{0,1} table entries.
 548
 549 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 552         Delete.
 553
 554 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         PR binutils/24719
 557         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 558         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 559         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 560         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 561         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 562         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 563         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 564         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 565         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 566         PREFIX_EVEX_0F38C6_REG_6 entries.
 567         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 568         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 569         EVEX_W_0F38C7_R_6_P_2 entries.
 570         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 571         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 572         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 573         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 574         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 575         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 576         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 577
 578 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 581         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 582         VEX_LEN_0F2D_P_3): Delete.
 583         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 584         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 585         (prefix_table): ... here.
 586
 587 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-dis.c (Iq): Delete.
 590         (Id): New.
 591         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 592         TBM insns.
 593         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 594         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 595         (OP_E_memory): Also honor needindex when deciding whether an
 596         address size prefix needs printing.
 597         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 598
 599 2019-06-26  Jim Wilson  <jimw@sifive.com>
 600
 601         PR binutils/24739
 602         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 603         Set info->display_endian to info->endian_code.
 604
 605 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 608         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 609         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 610         OPERAND_TYPE_ACC64 entries.
 611         * i386-init.h: Re-generate.
 612
 613 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 616         Delete.
 617         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 618         of dqa_mode.
 619         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 620         entries here.
 621         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 622         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 623
 624 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 627         variables.
 628
 629 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 632         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 633         movnti.
 634         * i386-opc.tbl (movnti): Add IgnoreSize.
 635         * i386-tbl.h: Re-generate.
 636
 637 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 640         * i386-tbl.h: Re-generate.
 641
 642 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 643
 644         * i386-dis-evex.h: Break into ...
 645         * i386-dis-evex-len.h: New file.
 646         * i386-dis-evex-mod.h: Likewise.
 647         * i386-dis-evex-prefix.h: Likewise.
 648         * i386-dis-evex-reg.h: Likewise.
 649         * i386-dis-evex-w.h: Likewise.
 650         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 651         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 652         i386-dis-evex-mod.h.
 653
 654 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 655
 656         PR binutils/24700
 657         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 658         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 659         EVEX_W_0F385B_P_2.
 660         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 661         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 662         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 663         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 664         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 665         EVEX_LEN_0F385B_P_2_W_1.
 666         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 667         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 668         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 669         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 670         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 671         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 672         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 673         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 674         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 675         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 676
 677 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 678
 679         PR binutils/24691
 680         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 681         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 682         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 683         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 684         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 685         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 686         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 687         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 688         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 689         EVEX_LEN_0F3A43_P_2_W_1.
 690         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 691         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 692         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 693         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 694         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 695         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 696         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 697         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 698         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 699         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 700         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 701         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 702
 703 2019-06-14  Nick Clifton  <nickc@redhat.com>
 704
 705         * po/fr.po; Updated French translation.
 706
 707 2019-06-13  Stafford Horne  <shorne@gmail.com>
 708
 709         * or1k-asm.c: Regenerated.
 710         * or1k-desc.c: Regenerated.
 711         * or1k-desc.h: Regenerated.
 712         * or1k-dis.c: Regenerated.
 713         * or1k-ibld.c: Regenerated.
 714         * or1k-opc.c: Regenerated.
 715         * or1k-opc.h: Regenerated.
 716         * or1k-opinst.c: Regenerated.
 717
 718 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 719
 720         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 721
 722 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 723
 724         PR binutils/24633
 725         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 726         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 727         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 728         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 729         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 730         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 731         EVEX_LEN_0F3A1B_P_2_W_1.
 732         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 733         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 734         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 735         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 736         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 737         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 738         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 739         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 740
 741 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         PR binutils/24626
 744         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 745         EVEX.vvvv when disassembling VEX and EVEX instructions.
 746         (OP_VEX): Set vex.register_specifier to 0 after readding
 747         vex.register_specifier.
 748         (OP_Vex_2src_1): Likewise.
 749         (OP_Vex_2src_2): Likewise.
 750         (OP_LWP_E): Likewise.
 751         (OP_EX_Vex): Don't check vex.register_specifier.
 752         (OP_XMM_Vex): Likewise.
 753
 754 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 755             Lili Cui  <lili.cui@intel.com>
 756
 757         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 758         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 759         instructions.
 760         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 761         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 762         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 763         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 764         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 765         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 766         * i386-init.h: Regenerated.
 767         * i386-tbl.h: Likewise.
 768
 769 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 770             Lili Cui  <lili.cui@intel.com>
 771
 772         * doc/c-i386.texi: Document enqcmd.
 773         * testsuite/gas/i386/enqcmd-intel.d: New file.
 774         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 775         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 776         * testsuite/gas/i386/enqcmd.d: Likewise.
 777         * testsuite/gas/i386/enqcmd.s: Likewise.
 778         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 779         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 780         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 781         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 782         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 783         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 784         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 785         and x86-64-enqcmd.
 786
 787 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 788
 789         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 790
 791 2019-06-03  Alan Modra  <amodra@gmail.com>
 792
 793         * ppc-dis.c (prefix_opcd_indices): Correct size.
 794
 795 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 796
 797         PR gas/24625
 798         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 799         Disp8ShiftVL.
 800         * i386-tbl.h: Regenerated.
 801
 802 2019-05-24  Alan Modra  <amodra@gmail.com>
 803
 804         * po/POTFILES.in: Regenerate.
 805
 806 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 807             Alan Modra  <amodra@gmail.com>
 808
 809         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 810         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 811         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 812         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 813         XTOP>): Define and add entries.
 814         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 815         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 816         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 817         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 818
 819 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 820             Alan Modra  <amodra@gmail.com>
 821
 822         * ppc-dis.c (ppc_opts): Add "future" entry.
 823         (PREFIX_OPCD_SEGS): Define.
 824         (prefix_opcd_indices): New array.
 825         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 826         (lookup_prefix): New function.
 827         (print_insn_powerpc): Handle 64-bit prefix instructions.
 828         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 829         (PMRR, POWERXX): Define.
 830         (prefix_opcodes): New instruction table.
 831         (prefix_num_opcodes): New constant.
 832
 833 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 834
 835         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 836         * configure: Regenerated.
 837         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 838         and cpu/bpf.opc.
 839         (HFILES): Add bpf-desc.h and bpf-opc.h.
 840         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 841         bpf-ibld.c and bpf-opc.c.
 842         (BPF_DEPS): Define.
 843         * Makefile.in: Regenerated.
 844         * disassemble.c (ARCH_bpf): Define.
 845         (disassembler): Add case for bfd_arch_bpf.
 846         (disassemble_init_for_target): Likewise.
 847         (enum epbf_isa_attr): Define.
 848         * disassemble.h: extern print_insn_bpf.
 849         * bpf-asm.c: Generated.
 850         * bpf-opc.h: Likewise.
 851         * bpf-opc.c: Likewise.
 852         * bpf-ibld.c: Likewise.
 853         * bpf-dis.c: Likewise.
 854         * bpf-desc.h: Likewise.
 855         * bpf-desc.c: Likewise.
 856
 857 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 858
 859         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 860         and VMSR with the new operands.
 861
 862 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 863
 864         * arm-dis.c (enum mve_instructions): New enum
 865         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 866         and cneg.
 867         (mve_opcodes): New instructions as above.
 868         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 869         csneg and csel.
 870         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 871
 872 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 873
 874         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 875         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 876         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 877         uqshl, urshrl and urshr.
 878         (is_mve_okay_in_it): Add new instructions to TRUE list.
 879         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 880         (print_insn_mve): Updated to accept new %j,
 881         %<bitfield>m and %<bitfield>n patterns.
 882
 883 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 884
 885         * mips-opc.c (mips_builtin_opcodes): Change source register
 886         constraint for DAUI.
 887
 888 2019-05-20  Nick Clifton  <nickc@redhat.com>
 889
 890         * po/fr.po: Updated French translation.
 891
 892 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 893             Michael Collison <michael.collison@arm.com>
 894
 895         * arm-dis.c (thumb32_opcodes): Add new instructions.
 896         (enum mve_instructions): Likewise.
 897         (enum mve_undefined): Add new reasons.
 898         (is_mve_encoding_conflict): Handle new instructions.
 899         (is_mve_undefined): Likewise.
 900         (is_mve_unpredictable): Likewise.
 901         (print_mve_undefined): Likewise.
 902         (print_mve_size): Likewise.
 903
 904 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 905             Michael Collison <michael.collison@arm.com>
 906
 907         * arm-dis.c (thumb32_opcodes): Add new instructions.
 908         (enum mve_instructions): Likewise.
 909         (is_mve_encoding_conflict): Handle new instructions.
 910         (is_mve_undefined): Likewise.
 911         (is_mve_unpredictable): Likewise.
 912         (print_mve_size): Likewise.
 913
 914 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 915             Michael Collison <michael.collison@arm.com>
 916
 917         * arm-dis.c (thumb32_opcodes): Add new instructions.
 918         (enum mve_instructions): Likewise.
 919         (is_mve_encoding_conflict): Likewise.
 920         (is_mve_unpredictable): Likewise.
 921         (print_mve_size): Likewise.
 922
 923 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 924             Michael Collison <michael.collison@arm.com>
 925
 926         * arm-dis.c (thumb32_opcodes): Add new instructions.
 927         (enum mve_instructions): Likewise.
 928         (is_mve_encoding_conflict): Handle new instructions.
 929         (is_mve_undefined): Likewise.
 930         (is_mve_unpredictable): Likewise.
 931         (print_mve_size): Likewise.
 932
 933 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 934             Michael Collison <michael.collison@arm.com>
 935
 936         * arm-dis.c (thumb32_opcodes): Add new instructions.
 937         (enum mve_instructions): Likewise.
 938         (is_mve_encoding_conflict): Handle new instructions.
 939         (is_mve_undefined): Likewise.
 940         (is_mve_unpredictable): Likewise.
 941         (print_mve_size): Likewise.
 942         (print_insn_mve): Likewise.
 943
 944 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 945             Michael Collison <michael.collison@arm.com>
 946
 947         * arm-dis.c (thumb32_opcodes): Add new instructions.
 948         (print_insn_thumb32): Handle new instructions.
 949
 950 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 951             Michael Collison <michael.collison@arm.com>
 952
 953         * arm-dis.c (enum mve_instructions): Add new instructions.
 954         (enum mve_undefined): Add new reasons.
 955         (is_mve_encoding_conflict): Handle new instructions.
 956         (is_mve_undefined): Likewise.
 957         (is_mve_unpredictable): Likewise.
 958         (print_mve_undefined): Likewise.
 959         (print_mve_size): Likewise.
 960         (print_mve_shift_n): Likewise.
 961         (print_insn_mve): Likewise.
 962
 963 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 964             Michael Collison <michael.collison@arm.com>
 965
 966         * arm-dis.c (enum mve_instructions): Add new instructions.
 967         (is_mve_encoding_conflict): Handle new instructions.
 968         (is_mve_unpredictable): Likewise.
 969         (print_mve_rotate): Likewise.
 970         (print_mve_size): Likewise.
 971         (print_insn_mve): Likewise.
 972
 973 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 974             Michael Collison <michael.collison@arm.com>
 975
 976         * arm-dis.c (enum mve_instructions): Add new instructions.
 977         (is_mve_encoding_conflict): Handle new instructions.
 978         (is_mve_unpredictable): Likewise.
 979         (print_mve_size): Likewise.
 980         (print_insn_mve): Likewise.
 981
 982 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 983             Michael Collison <michael.collison@arm.com>
 984
 985         * arm-dis.c (enum mve_instructions): Add new instructions.
 986         (enum mve_undefined): Add new reasons.
 987         (is_mve_encoding_conflict): Handle new instructions.
 988         (is_mve_undefined): Likewise.
 989         (is_mve_unpredictable): Likewise.
 990         (print_mve_undefined): Likewise.
 991         (print_mve_size): Likewise.
 992         (print_insn_mve): Likewise.
 993
 994 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 995             Michael Collison <michael.collison@arm.com>
 996
 997         * arm-dis.c (enum mve_instructions): Add new instructions.
 998         (is_mve_encoding_conflict): Handle new instructions.
 999         (is_mve_undefined): Likewise.
1000         (is_mve_unpredictable): Likewise.
1001         (print_mve_size): Likewise.
1002         (print_insn_mve): Likewise.
1003
1004 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1005             Michael Collison <michael.collison@arm.com>
1006
1007         * arm-dis.c (enum mve_instructions): Add new instructions.
1008         (enum mve_unpredictable): Add new reasons.
1009         (enum mve_undefined): Likewise.
1010         (is_mve_okay_in_it): Handle new isntructions.
1011         (is_mve_encoding_conflict): Likewise.
1012         (is_mve_undefined): Likewise.
1013         (is_mve_unpredictable): Likewise.
1014         (print_mve_vmov_index): Likewise.
1015         (print_simd_imm8): Likewise.
1016         (print_mve_undefined): Likewise.
1017         (print_mve_unpredictable): Likewise.
1018         (print_mve_size): Likewise.
1019         (print_insn_mve): Likewise.
1020
1021 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1022             Michael Collison <michael.collison@arm.com>
1023
1024         * arm-dis.c (enum mve_instructions): Add new instructions.
1025         (enum mve_unpredictable): Add new reasons.
1026         (enum mve_undefined): Likewise.
1027         (is_mve_encoding_conflict): Handle new instructions.
1028         (is_mve_undefined): Likewise.
1029         (is_mve_unpredictable): Likewise.
1030         (print_mve_undefined): Likewise.
1031         (print_mve_unpredictable): Likewise.
1032         (print_mve_rounding_mode): Likewise.
1033         (print_mve_vcvt_size): Likewise.
1034         (print_mve_size): Likewise.
1035         (print_insn_mve): Likewise.
1036
1037 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1038             Michael Collison <michael.collison@arm.com>
1039
1040         * arm-dis.c (enum mve_instructions): Add new instructions.
1041         (enum mve_unpredictable): Add new reasons.
1042         (enum mve_undefined): Likewise.
1043         (is_mve_undefined): Handle new instructions.
1044         (is_mve_unpredictable): Likewise.
1045         (print_mve_undefined): Likewise.
1046         (print_mve_unpredictable): Likewise.
1047         (print_mve_size): Likewise.
1048         (print_insn_mve): Likewise.
1049
1050 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1051             Michael Collison <michael.collison@arm.com>
1052
1053         * arm-dis.c (enum mve_instructions): Add new instructions.
1054         (enum mve_undefined): Add new reasons.
1055         (insns): Add new instructions.
1056         (is_mve_encoding_conflict):
1057         (print_mve_vld_str_addr): New print function.
1058         (is_mve_undefined): Handle new instructions.
1059         (is_mve_unpredictable): Likewise.
1060         (print_mve_undefined): Likewise.
1061         (print_mve_size): Likewise.
1062         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1063         (print_insn_mve):  Handle new operands.
1064
1065 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1066             Michael Collison <michael.collison@arm.com>
1067
1068         * arm-dis.c (enum mve_instructions): Add new instructions.
1069         (enum mve_unpredictable): Add new reasons.
1070         (is_mve_encoding_conflict): Handle new instructions.
1071         (is_mve_unpredictable): Likewise.
1072         (mve_opcodes): Add new instructions.
1073         (print_mve_unpredictable): Handle new reasons.
1074         (print_mve_register_blocks): New print function.
1075         (print_mve_size): Handle new instructions.
1076         (print_insn_mve): Likewise.
1077
1078 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1079             Michael Collison <michael.collison@arm.com>
1080
1081         * arm-dis.c (enum mve_instructions): Add new instructions.
1082         (enum mve_unpredictable): Add new reasons.
1083         (enum mve_undefined): Likewise.
1084         (is_mve_encoding_conflict): Handle new instructions.
1085         (is_mve_undefined): Likewise.
1086         (is_mve_unpredictable): Likewise.
1087         (coprocessor_opcodes): Move NEON VDUP from here...
1088         (neon_opcodes): ... to here.
1089         (mve_opcodes): Add new instructions.
1090         (print_mve_undefined):  Handle new reasons.
1091         (print_mve_unpredictable): Likewise.
1092         (print_mve_size): Handle new instructions.
1093         (print_insn_neon): Handle vdup.
1094         (print_insn_mve): Handle new operands.
1095
1096 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1097             Michael Collison <michael.collison@arm.com>
1098
1099         * arm-dis.c (enum mve_instructions): Add new instructions.
1100         (enum mve_unpredictable): Add new values.
1101         (mve_opcodes): Add new instructions.
1102         (vec_condnames): New array with vector conditions.
1103         (mve_predicatenames): New array with predicate suffixes.
1104         (mve_vec_sizename): New array with vector sizes.
1105         (enum vpt_pred_state): New enum with vector predication states.
1106         (struct vpt_block): New struct type for vpt blocks.
1107         (vpt_block_state): Global struct to keep track of state.
1108         (mve_extract_pred_mask): New helper function.
1109         (num_instructions_vpt_block): Likewise.
1110         (mark_outside_vpt_block): Likewise.
1111         (mark_inside_vpt_block): Likewise.
1112         (invert_next_predicate_state): Likewise.
1113         (update_next_predicate_state): Likewise.
1114         (update_vpt_block_state): Likewise.
1115         (is_vpt_instruction): Likewise.
1116         (is_mve_encoding_conflict): Add entries for new instructions.
1117         (is_mve_unpredictable): Likewise.
1118         (print_mve_unpredictable): Handle new cases.
1119         (print_instruction_predicate): Likewise.
1120         (print_mve_size): New function.
1121         (print_vec_condition): New function.
1122         (print_insn_mve): Handle vpt blocks and new print operands.
1123
1124 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1125
1126         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1127         8, 14 and 15 for Armv8.1-M Mainline.
1128
1129 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1130             Michael Collison <michael.collison@arm.com>
1131
1132         * arm-dis.c (enum mve_instructions): New enum.
1133         (enum mve_unpredictable): Likewise.
1134         (enum mve_undefined): Likewise.
1135         (struct mopcode32): New struct.
1136         (is_mve_okay_in_it): New function.
1137         (is_mve_architecture): Likewise.
1138         (arm_decode_field): Likewise.
1139         (arm_decode_field_multiple): Likewise.
1140         (is_mve_encoding_conflict): Likewise.
1141         (is_mve_undefined): Likewise.
1142         (is_mve_unpredictable): Likewise.
1143         (print_mve_undefined): Likewise.
1144         (print_mve_unpredictable): Likewise.
1145         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1146         (print_insn_mve): New function.
1147         (print_insn_thumb32): Handle MVE architecture.
1148         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1149
1150 2019-05-10  Nick Clifton  <nickc@redhat.com>
1151
1152         PR 24538
1153         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1154         end of the table prematurely.
1155
1156 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1157
1158         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1159         macros for R6.
1160
1161 2019-05-11  Alan Modra  <amodra@gmail.com>
1162
1163         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1164         when -Mraw is in effect.
1165
1166 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1167
1168         * aarch64-dis-2.c: Regenerate.
1169         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1170         (OP_SVE_BBB): New variant set.
1171         (OP_SVE_DDDD): New variant set.
1172         (OP_SVE_HHH): New variant set.
1173         (OP_SVE_HHHU): New variant set.
1174         (OP_SVE_SSS): New variant set.
1175         (OP_SVE_SSSU): New variant set.
1176         (OP_SVE_SHH): New variant set.
1177         (OP_SVE_SBBU): New variant set.
1178         (OP_SVE_DSS): New variant set.
1179         (OP_SVE_DHHU): New variant set.
1180         (OP_SVE_VMV_HSD_BHS): New variant set.
1181         (OP_SVE_VVU_HSD_BHS): New variant set.
1182         (OP_SVE_VVVU_SD_BH): New variant set.
1183         (OP_SVE_VVVU_BHSD): New variant set.
1184         (OP_SVE_VVV_QHD_DBS): New variant set.
1185         (OP_SVE_VVV_HSD_BHS): New variant set.
1186         (OP_SVE_VVV_HSD_BHS2): New variant set.
1187         (OP_SVE_VVV_BHS_HSD): New variant set.
1188         (OP_SVE_VV_BHS_HSD): New variant set.
1189         (OP_SVE_VVV_SD): New variant set.
1190         (OP_SVE_VVU_BHS_HSD): New variant set.
1191         (OP_SVE_VZVV_SD): New variant set.
1192         (OP_SVE_VZVV_BH): New variant set.
1193         (OP_SVE_VZV_SD): New variant set.
1194         (aarch64_opcode_table): Add sve2 instructions.
1195
1196 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1197
1198         * aarch64-asm-2.c: Regenerated.
1199         * aarch64-dis-2.c: Regenerated.
1200         * aarch64-opc-2.c: Regenerated.
1201         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1202         for SVE_SHLIMM_UNPRED_22.
1203         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1204         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1205         operand.
1206
1207 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1208
1209         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1210         sve_size_tsz_bhs iclass encode.
1211         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1212         sve_size_tsz_bhs iclass decode.
1213
1214 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1215
1216         * aarch64-asm-2.c: Regenerated.
1217         * aarch64-dis-2.c: Regenerated.
1218         * aarch64-opc-2.c: Regenerated.
1219         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1220         for SVE_Zm4_11_INDEX.
1221         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1222         (fields): Handle SVE_i2h field.
1223         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1224         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1225
1226 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1227
1228         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1229         sve_shift_tsz_bhsd iclass encode.
1230         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1231         sve_shift_tsz_bhsd iclass decode.
1232
1233 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1234
1235         * aarch64-asm-2.c: Regenerated.
1236         * aarch64-dis-2.c: Regenerated.
1237         * aarch64-opc-2.c: Regenerated.
1238         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1239         (aarch64_encode_variant_using_iclass): Handle
1240         sve_shift_tsz_hsd iclass encode.
1241         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1242         sve_shift_tsz_hsd iclass decode.
1243         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1244         for SVE_SHRIMM_UNPRED_22.
1245         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1246         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1247         operand.
1248
1249 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1250
1251         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1252         sve_size_013 iclass encode.
1253         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1254         sve_size_013 iclass decode.
1255
1256 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1257
1258         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1259         sve_size_bh iclass encode.
1260         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1261         sve_size_bh iclass decode.
1262
1263 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1264
1265         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1266         sve_size_sd2 iclass encode.
1267         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1268         sve_size_sd2 iclass decode.
1269         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1270         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1271
1272 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1273
1274         * aarch64-asm-2.c: Regenerated.
1275         * aarch64-dis-2.c: Regenerated.
1276         * aarch64-opc-2.c: Regenerated.
1277         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1278         for SVE_ADDR_ZX.
1279         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1280         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1281
1282 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1283
1284         * aarch64-asm-2.c: Regenerated.
1285         * aarch64-dis-2.c: Regenerated.
1286         * aarch64-opc-2.c: Regenerated.
1287         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1288         for SVE_Zm3_11_INDEX.
1289         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1290         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1291         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1292         fields.
1293         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1294
1295 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1296
1297         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1298         sve_size_hsd2 iclass encode.
1299         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1300         sve_size_hsd2 iclass decode.
1301         * aarch64-opc.c (fields): Handle SVE_size field.
1302         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1303
1304 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1305
1306         * aarch64-asm-2.c: Regenerated.
1307         * aarch64-dis-2.c: Regenerated.
1308         * aarch64-opc-2.c: Regenerated.
1309         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1310         for SVE_IMM_ROT3.
1311         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1312         (fields): Handle SVE_rot3 field.
1313         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1314         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1315
1316 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1317
1318         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1319         instructions.
1320
1321 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1322
1323         * aarch64-tbl.h
1324         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1325         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1326         aarch64_feature_sve2bitperm): New feature sets.
1327         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1328         for feature set addresses.
1329         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1330         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1331
1332 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1333             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1334
1335         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1336         argument and set ASE_EVA_R6 appropriately.
1337         (set_default_mips_dis_options): Pass ISA to above.
1338         (parse_mips_dis_option): Likewise.
1339         * mips-opc.c (EVAR6): New macro.
1340         (mips_builtin_opcodes): Add llwpe, scwpe.
1341
1342 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1343
1344         * aarch64-asm-2.c: Regenerated.
1345         * aarch64-dis-2.c: Regenerated.
1346         * aarch64-opc-2.c: Regenerated.
1347         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1348         AARCH64_OPND_TME_UIMM16.
1349         (aarch64_print_operand): Likewise.
1350         * aarch64-tbl.h (QL_IMM_NIL): New.
1351         (TME): New.
1352         (_TME_INSN): New.
1353         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1354
1355 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1356
1357         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1358
1359 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1360             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1361
1362         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1363
1364 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1365
1366         * s12z-opc.h: Add extern "C" bracketing to help
1367         users who wish to use this interface in c++ code.
1368
1369 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1370
1371         * s12z-opc.c (bm_decode): Handle bit map operations with the
1372         "reserved0" mode.
1373
1374 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1375
1376         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1377         specifier.  Add entries for VLDR and VSTR of system registers.
1378         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1379         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1380         of %J and %K format specifier.
1381
1382 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1383
1384         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1385         Add new entries for VSCCLRM instruction.
1386         (print_insn_coprocessor): Handle new %C format control code.
1387
1388 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1389
1390         * arm-dis.c (enum isa): New enum.
1391         (struct sopcode32): New structure.
1392         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1393         set isa field of all current entries to ANY.
1394         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1395         Only match an entry if its isa field allows the current mode.
1396
1397 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1398
1399         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1400         CLRM.
1401         (print_insn_thumb32): Add logic to print %n CLRM register list.
1402
1403 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1404
1405         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1406         and %Q patterns.
1407
1408 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1409
1410         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1411         (print_insn_thumb32): Edit the switch case for %Z.
1412
1413 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1414
1415         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1416
1417 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1418
1419         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1420
1421 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1422
1423         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1424
1425 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1426
1427         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1428         Arm register with r13 and r15 unpredictable.
1429         (thumb32_opcodes): New instructions for bfx and bflx.
1430
1431 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1432
1433         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1434
1435 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1436
1437         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1438
1439 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1440
1441         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1442
1443 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1444
1445         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1446
1447 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1448
1449         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1450         "optr". ("operator" is a reserved word in c++).
1451
1452 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1453
1454         * aarch64-opc.c (aarch64_print_operand): Add case for
1455         AARCH64_OPND_Rt_SP.
1456         (verify_constraints): Likewise.
1457         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1458         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1459         to accept Rt|SP as first operand.
1460         (AARCH64_OPERANDS): Add new Rt_SP.
1461         * aarch64-asm-2.c: Regenerated.
1462         * aarch64-dis-2.c: Regenerated.
1463         * aarch64-opc-2.c: Regenerated.
1464
1465 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1466
1467         * aarch64-asm-2.c: Regenerated.
1468         * aarch64-dis-2.c: Likewise.
1469         * aarch64-opc-2.c: Likewise.
1470         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1471
1472 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1473
1474         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1475
1476 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1477
1478         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1479         * i386-init.h: Regenerated.
1480
1481 2019-04-07  Alan Modra  <amodra@gmail.com>
1482
1483         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1484         op_separator to control printing of spaces, comma and parens
1485         rather than need_comma, need_paren and spaces vars.
1486
1487 2019-04-07  Alan Modra  <amodra@gmail.com>
1488
1489         PR 24421
1490         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1491         (print_insn_neon, print_insn_arm): Likewise.
1492
1493 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1494
1495         * i386-dis-evex.h (evex_table): Updated to support BF16
1496         instructions.
1497         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1498         and EVEX_W_0F3872_P_3.
1499         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1500         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1501         * i386-opc.h (enum): Add CpuAVX512_BF16.
1502         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1503         * i386-opc.tbl: Add AVX512 BF16 instructions.
1504         * i386-init.h: Regenerated.
1505         * i386-tbl.h: Likewise.
1506
1507 2019-04-05  Alan Modra  <amodra@gmail.com>
1508
1509         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1510         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1511         to favour printing of "-" branch hint when using the "y" bit.
1512         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1513
1514 2019-04-05  Alan Modra  <amodra@gmail.com>
1515
1516         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1517         opcode until first operand is output.
1518
1519 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1520
1521         PR gas/24349
1522         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1523         (valid_bo_post_v2): Add support for 'at' branch hints.
1524         (insert_bo): Only error on branch on ctr.
1525         (get_bo_hint_mask): New function.
1526         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1527         for inserting 'at' branch hints.
1528         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1529         for extracting 'at' branch hints.
1530         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1531         (BOE): Delete operand.
1532         (BOM, BOP): New operands.
1533         (RM): Update value.
1534         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1535         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1536         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1537         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1538         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1539         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1540         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1541         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1542         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1543         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1544         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1545         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1546         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1547         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1548         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1549         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1550         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1551         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1552         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1553         bttarl+>: New extended mnemonics.
1554
1555 2019-03-28  Alan Modra  <amodra@gmail.com>
1556
1557         PR 24390
1558         * ppc-opc.c (BTF): Define.
1559         (powerpc_opcodes): Use for mtfsb*.
1560         * ppc-dis.c (print_insn_powerpc): Print fields with both
1561         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1562
1563 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1564
1565         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1566         (mapping_symbol_for_insn): Implement new algorithm.
1567         (print_insn): Remove duplicate code.
1568
1569 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1570
1571         * aarch64-dis.c (print_insn_aarch64):
1572         Implement override.
1573
1574 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1575
1576         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1577         order.
1578
1579 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1580
1581         * aarch64-dis.c (last_stop_offset): New.
1582         (print_insn_aarch64): Use stop_offset.
1583
1584 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1585
1586         PR gas/24359
1587         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1588         CPU_ANY_AVX2_FLAGS.
1589         * i386-init.h: Regenerated.
1590
1591 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1592
1593         PR gas/24348
1594         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1595         vmovdqu16, vmovdqu32 and vmovdqu64.
1596         * i386-tbl.h: Regenerated.
1597
1598 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1599
1600         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1601         from vstrszb, vstrszh, and vstrszf.
1602
1603 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1604
1605         * s390-opc.txt: Add instruction descriptions.
1606
1607 2019-02-08  Jim Wilson  <jimw@sifive.com>
1608
1609         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1610         <bne>: Likewise.
1611
1612 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1613
1614         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1615
1616 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1617
1618         PR binutils/23212
1619         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1620         * aarch64-opc.c (verify_elem_sd): New.
1621         (fields): Add FLD_sz entr.
1622         * aarch64-tbl.h (_SIMD_INSN): New.
1623         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1624         fmulx scalar and vector by element isns.
1625
1626 2019-02-07  Nick Clifton  <nickc@redhat.com>
1627
1628         * po/sv.po: Updated Swedish translation.
1629
1630 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1631
1632         * s390-mkopc.c (main): Accept arch13 as cpu string.
1633         * s390-opc.c: Add new instruction formats and instruction opcode
1634         masks.
1635         * s390-opc.txt: Add new arch13 instructions.
1636
1637 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1638
1639         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1640         (aarch64_opcode): Change encoding for stg, stzg
1641         st2g and st2zg.
1642         * aarch64-asm-2.c: Regenerated.
1643         * aarch64-dis-2.c: Regenerated.
1644         * aarch64-opc-2.c: Regenerated.
1645
1646 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1647
1648         * aarch64-asm-2.c: Regenerated.
1649         * aarch64-dis-2.c: Likewise.
1650         * aarch64-opc-2.c: Likewise.
1651         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1652
1653 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1654             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1655
1656         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1657         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1658         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1659         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1660         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1661         case for ldstgv_indexed.
1662         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1663         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1664         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1665         * aarch64-asm-2.c: Regenerated.
1666         * aarch64-dis-2.c: Regenerated.
1667         * aarch64-opc-2.c: Regenerated.
1668
1669 2019-01-23  Nick Clifton  <nickc@redhat.com>
1670
1671         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1672
1673 2019-01-21  Nick Clifton  <nickc@redhat.com>
1674
1675         * po/de.po: Updated German translation.
1676         * po/uk.po: Updated Ukranian translation.
1677
1678 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1679         * mips-dis.c (mips_arch_choices): Fix typo in
1680         gs464, gs464e and gs264e descriptors.
1681
1682 2019-01-19  Nick Clifton  <nickc@redhat.com>
1683
1684         * configure: Regenerate.
1685         * po/opcodes.pot: Regenerate.
1686
1687 2018-06-24  Nick Clifton  <nickc@redhat.com>
1688
1689         2.32 branch created.
1690
1691 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1692
1693         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1694         if it is null.
1695         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1696         zero.
1697
1698 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1699
1700         * configure: Regenerate.
1701
1702 2019-01-07  Alan Modra  <amodra@gmail.com>
1703
1704         * configure: Regenerate.
1705         * po/POTFILES.in: Regenerate.
1706
1707 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1708
1709         * s12z-opc.c: New file.
1710         * s12z-opc.h: New file.
1711         * s12z-dis.c: Removed all code not directly related to display
1712         of instructions.  Used the interface provided by the new files
1713         instead.
1714         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1715         * Makefile.in: Regenerate.
1716         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1717         * configure: Regenerate.
1718
1719 2019-01-01  Alan Modra  <amodra@gmail.com>
1720
1721         Update year range in copyright notice of all files.
1722
1723 For older changes see ChangeLog-2018
1724 \f
1725 Copyright (C) 2019 Free Software Foundation, Inc.
1726
1727 Copying and distribution of this file, with or without modification,
1728 are permitted in any medium without royalty provided the copyright
1729 notice and this notice are preserved.
1730
1731 Local Variables:
1732 mode: change-log
1733 left-margin: 8
1734 fill-column: 74
1735 version-control: never
1736 End: