1 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
3 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
6 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
9 (aarch64_feature_sve2, aarch64_feature_sve2aes,
10 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
11 aarch64_feature_sve2bitperm): New feature sets.
12 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
13 for feature set addresses.
14 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
15 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
17 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
18 Faraz Shahbazker <fshahbazker@wavecomp.com>
20 * mips-dis.c (mips_calculate_combination_ases): Add ISA
21 argument and set ASE_EVA_R6 appropriately.
22 (set_default_mips_dis_options): Pass ISA to above.
23 (parse_mips_dis_option): Likewise.
24 * mips-opc.c (EVAR6): New macro.
25 (mips_builtin_opcodes): Add llwpe, scwpe.
27 2019-05-01 Sudakshina Das <sudi.das@arm.com>
29 * aarch64-asm-2.c: Regenerated.
30 * aarch64-dis-2.c: Regenerated.
31 * aarch64-opc-2.c: Regenerated.
32 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
33 AARCH64_OPND_TME_UIMM16.
34 (aarch64_print_operand): Likewise.
35 * aarch64-tbl.h (QL_IMM_NIL): New.
38 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
40 2019-04-29 John Darrington <john@darrington.wattle.id.au>
42 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
44 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
45 Faraz Shahbazker <fshahbazker@wavecomp.com>
47 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
49 2019-04-24 John Darrington <john@darrington.wattle.id.au>
51 * s12z-opc.h: Add extern "C" bracketing to help
52 users who wish to use this interface in c++ code.
54 2019-04-24 John Darrington <john@darrington.wattle.id.au>
56 * s12z-opc.c (bm_decode): Handle bit map operations with the
59 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
61 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
62 specifier. Add entries for VLDR and VSTR of system registers.
63 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
64 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
65 of %J and %K format specifier.
67 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
69 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
70 Add new entries for VSCCLRM instruction.
71 (print_insn_coprocessor): Handle new %C format control code.
73 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
75 * arm-dis.c (enum isa): New enum.
76 (struct sopcode32): New structure.
77 (coprocessor_opcodes): change type of entries to struct sopcode32 and
78 set isa field of all current entries to ANY.
79 (print_insn_coprocessor): Change type of insn to struct sopcode32.
80 Only match an entry if its isa field allows the current mode.
82 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
84 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
86 (print_insn_thumb32): Add logic to print %n CLRM register list.
88 2019-04-15 Sudakshina Das <sudi.das@arm.com>
90 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
93 2019-04-15 Sudakshina Das <sudi.das@arm.com>
95 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
96 (print_insn_thumb32): Edit the switch case for %Z.
98 2019-04-15 Sudakshina Das <sudi.das@arm.com>
100 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
102 2019-04-15 Sudakshina Das <sudi.das@arm.com>
104 * arm-dis.c (thumb32_opcodes): New instruction bfl.
106 2019-04-15 Sudakshina Das <sudi.das@arm.com>
108 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
110 2019-04-15 Sudakshina Das <sudi.das@arm.com>
112 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
113 Arm register with r13 and r15 unpredictable.
114 (thumb32_opcodes): New instructions for bfx and bflx.
116 2019-04-15 Sudakshina Das <sudi.das@arm.com>
118 * arm-dis.c (thumb32_opcodes): New instructions for bf.
120 2019-04-15 Sudakshina Das <sudi.das@arm.com>
122 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
124 2019-04-15 Sudakshina Das <sudi.das@arm.com>
126 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
128 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
130 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
132 2019-04-12 John Darrington <john@darrington.wattle.id.au>
134 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
135 "optr". ("operator" is a reserved word in c++).
137 2019-04-11 Sudakshina Das <sudi.das@arm.com>
139 * aarch64-opc.c (aarch64_print_operand): Add case for
141 (verify_constraints): Likewise.
142 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
143 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
144 to accept Rt|SP as first operand.
145 (AARCH64_OPERANDS): Add new Rt_SP.
146 * aarch64-asm-2.c: Regenerated.
147 * aarch64-dis-2.c: Regenerated.
148 * aarch64-opc-2.c: Regenerated.
150 2019-04-11 Sudakshina Das <sudi.das@arm.com>
152 * aarch64-asm-2.c: Regenerated.
153 * aarch64-dis-2.c: Likewise.
154 * aarch64-opc-2.c: Likewise.
155 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
157 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
159 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
161 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
163 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
164 * i386-init.h: Regenerated.
166 2019-04-07 Alan Modra <amodra@gmail.com>
168 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
169 op_separator to control printing of spaces, comma and parens
170 rather than need_comma, need_paren and spaces vars.
172 2019-04-07 Alan Modra <amodra@gmail.com>
175 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
176 (print_insn_neon, print_insn_arm): Likewise.
178 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
180 * i386-dis-evex.h (evex_table): Updated to support BF16
182 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
183 and EVEX_W_0F3872_P_3.
184 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
185 (cpu_flags): Add bitfield for CpuAVX512_BF16.
186 * i386-opc.h (enum): Add CpuAVX512_BF16.
187 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
188 * i386-opc.tbl: Add AVX512 BF16 instructions.
189 * i386-init.h: Regenerated.
190 * i386-tbl.h: Likewise.
192 2019-04-05 Alan Modra <amodra@gmail.com>
194 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
195 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
196 to favour printing of "-" branch hint when using the "y" bit.
197 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
199 2019-04-05 Alan Modra <amodra@gmail.com>
201 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
202 opcode until first operand is output.
204 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
207 * ppc-opc.c (valid_bo_pre_v2): Add comments.
208 (valid_bo_post_v2): Add support for 'at' branch hints.
209 (insert_bo): Only error on branch on ctr.
210 (get_bo_hint_mask): New function.
211 (insert_boe): Add new 'branch_taken' formal argument. Add support
212 for inserting 'at' branch hints.
213 (extract_boe): Add new 'branch_taken' formal argument. Add support
214 for extracting 'at' branch hints.
215 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
216 (BOE): Delete operand.
217 (BOM, BOP): New operands.
219 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
220 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
221 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
222 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
223 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
224 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
225 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
226 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
227 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
228 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
229 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
230 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
231 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
232 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
233 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
234 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
235 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
236 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
237 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
238 bttarl+>: New extended mnemonics.
240 2019-03-28 Alan Modra <amodra@gmail.com>
243 * ppc-opc.c (BTF): Define.
244 (powerpc_opcodes): Use for mtfsb*.
245 * ppc-dis.c (print_insn_powerpc): Print fields with both
246 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
248 2019-03-25 Tamar Christina <tamar.christina@arm.com>
250 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
251 (mapping_symbol_for_insn): Implement new algorithm.
252 (print_insn): Remove duplicate code.
254 2019-03-25 Tamar Christina <tamar.christina@arm.com>
256 * aarch64-dis.c (print_insn_aarch64):
259 2019-03-25 Tamar Christina <tamar.christina@arm.com>
261 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
264 2019-03-25 Tamar Christina <tamar.christina@arm.com>
266 * aarch64-dis.c (last_stop_offset): New.
267 (print_insn_aarch64): Use stop_offset.
269 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
274 * i386-init.h: Regenerated.
276 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
279 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
280 vmovdqu16, vmovdqu32 and vmovdqu64.
281 * i386-tbl.h: Regenerated.
283 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
285 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
286 from vstrszb, vstrszh, and vstrszf.
288 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
290 * s390-opc.txt: Add instruction descriptions.
292 2019-02-08 Jim Wilson <jimw@sifive.com>
294 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
297 2019-02-07 Tamar Christina <tamar.christina@arm.com>
299 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
301 2019-02-07 Tamar Christina <tamar.christina@arm.com>
304 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
305 * aarch64-opc.c (verify_elem_sd): New.
306 (fields): Add FLD_sz entr.
307 * aarch64-tbl.h (_SIMD_INSN): New.
308 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
309 fmulx scalar and vector by element isns.
311 2019-02-07 Nick Clifton <nickc@redhat.com>
313 * po/sv.po: Updated Swedish translation.
315 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
317 * s390-mkopc.c (main): Accept arch13 as cpu string.
318 * s390-opc.c: Add new instruction formats and instruction opcode
320 * s390-opc.txt: Add new arch13 instructions.
322 2019-01-25 Sudakshina Das <sudi.das@arm.com>
324 * aarch64-tbl.h (QL_LDST_AT): Update macro.
325 (aarch64_opcode): Change encoding for stg, stzg
327 * aarch64-asm-2.c: Regenerated.
328 * aarch64-dis-2.c: Regenerated.
329 * aarch64-opc-2.c: Regenerated.
331 2019-01-25 Sudakshina Das <sudi.das@arm.com>
333 * aarch64-asm-2.c: Regenerated.
334 * aarch64-dis-2.c: Likewise.
335 * aarch64-opc-2.c: Likewise.
336 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
338 2019-01-25 Sudakshina Das <sudi.das@arm.com>
339 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
341 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
342 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
343 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
344 * aarch64-dis.h (ext_addr_simple_2): Likewise.
345 * aarch64-opc.c (operand_general_constraint_met_p): Remove
346 case for ldstgv_indexed.
347 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
348 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
349 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
350 * aarch64-asm-2.c: Regenerated.
351 * aarch64-dis-2.c: Regenerated.
352 * aarch64-opc-2.c: Regenerated.
354 2019-01-23 Nick Clifton <nickc@redhat.com>
356 * po/pt_BR.po: Updated Brazilian Portuguese translation.
358 2019-01-21 Nick Clifton <nickc@redhat.com>
360 * po/de.po: Updated German translation.
361 * po/uk.po: Updated Ukranian translation.
363 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
364 * mips-dis.c (mips_arch_choices): Fix typo in
365 gs464, gs464e and gs264e descriptors.
367 2019-01-19 Nick Clifton <nickc@redhat.com>
369 * configure: Regenerate.
370 * po/opcodes.pot: Regenerate.
372 2018-06-24 Nick Clifton <nickc@redhat.com>
376 2019-01-09 John Darrington <john@darrington.wattle.id.au>
378 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
380 -dis.c (opr_emit_disassembly): Do not omit an index if it is
383 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
385 * configure: Regenerate.
387 2019-01-07 Alan Modra <amodra@gmail.com>
389 * configure: Regenerate.
390 * po/POTFILES.in: Regenerate.
392 2019-01-03 John Darrington <john@darrington.wattle.id.au>
394 * s12z-opc.c: New file.
395 * s12z-opc.h: New file.
396 * s12z-dis.c: Removed all code not directly related to display
397 of instructions. Used the interface provided by the new files
399 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
400 * Makefile.in: Regenerate.
401 * configure.ac (bfd_s12z_arch): Correct the dependencies.
402 * configure: Regenerate.
404 2019-01-01 Alan Modra <amodra@gmail.com>
406 Update year range in copyright notice of all files.
408 For older changes see ChangeLog-2018
410 Copyright (C) 2019 Free Software Foundation, Inc.
412 Copying and distribution of this file, with or without modification,
413 are permitted in any medium without royalty provided the copyright
414 notice and this notice are preserved.
420 version-control: never