opcodes/ChangeLog

   1 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
   4         (bspop): Likewise.
   5         (modapp): Likewise.
   6         * arc-opc.c (RAD_CHK): Add.
   7         * arc-tbl.h: Regenerate.
   8
   9 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  10
  11         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  12         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  13
  14 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  15
  16         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  17         instructions as UNPREDICTABLE.
  18
  19 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  20
  21         * bpf-desc.c: Regenerated.
  22
  23 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-gen.c (static_assert): Define.
  26         (main): Use it.
  27         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  28         (Opcode_Modifier_Num): ... this.
  29         (Mem): Delete.
  30
  31 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-gen.c (operand_types): Move RegMem ...
  34         (opcode_modifiers): ... here.
  35         * i386-opc.h (RegMem): Move to opcode modifer enum.
  36         (union i386_operand_type): Move regmem field ...
  37         (struct i386_opcode_modifier): ... here.
  38         * i386-opc.tbl (RegMem): Define.
  39         (mov, movq): Move RegMem on segment, control, debug, and test
  40         register flavors.
  41         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  42         to non-SSE2AVX flavor.
  43         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  44         Move RegMem on register only flavors. Drop IgnoreSize from
  45         legacy encoding flavors.
  46         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  47         flavors.
  48         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  49         register only flavors.
  50         (vmovd): Move RegMem and drop IgnoreSize on register only
  51         flavor. Change opcode and operand order to store form.
  52         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  53
  54 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  57         entries.
  58         * i386-opc.h (SReg2, SReg3): Replace by ...
  59         (SReg): ... this.
  60         (union i386_operand_type): Replace sreg fields.
  61         * i386-opc.tbl (mov, ): Use SReg.
  62         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  63         register flavors.
  64         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  65         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  66
  67 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  68
  69         * bpf-desc.c: Regenerate.
  70         * bpf-opc.c: Likewise.
  71         * bpf-opc.h: Likewise.
  72
  73 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  74
  75         * bpf-desc.c: Regenerate.
  76         * bpf-opc.c: Likewise.
  77
  78 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  79
  80         * arm-dis.c (print_insn_coprocessor): Rename index to
  81         index_operand.
  82
  83 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  84
  85         * riscv-opc.c (riscv_insn_types): Add r4 type.
  86
  87         * riscv-opc.c (riscv_insn_types): Add b and j type.
  88
  89         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  90         format for sb type and correct s type.
  91
  92 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  93
  94         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
  95         SVE FMOV alias of FCPY.
  96
  97 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
  98
  99         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 100         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 101
 102 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 103
 104         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 105         registers in an instruction prefixed by MOVPRFX.
 106
 107 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 108
 109         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 110         sve_size_13 icode to account for variant behaviour of
 111         pmull{t,b}.
 112         * aarch64-dis-2.c: Regenerate.
 113         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 114         sve_size_13 icode to account for variant behaviour of
 115         pmull{t,b}.
 116         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 117         (OP_SVE_VVV_Q_D): Add new qualifier.
 118         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 119         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 120         AES and those not.
 121
 122 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 123
 124         * opcodes/i386-gen.c (operand_type_init): Remove
 125         OPERAND_TYPE_VEC_IMM4 entry.
 126         (operand_types): Remove Vec_Imm4.
 127         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 128         (union i386_operand_type): Remove vec_imm4.
 129         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 130         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 131
 132 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 133
 134         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 135         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 136         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 137         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 138         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 139         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 140         * i386-tbl.h: Re-generate.
 141
 142 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 145         register operands.
 146         * i386-tbl.h: Re-generate.
 147
 148 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl (C): New.
 151         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 152         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 153         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 154         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 155         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 156         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 157         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 158         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 159         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 160         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 161         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 162         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 163         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 164         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 165         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 166         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 167         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 168         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 169         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 170         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 171         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 172         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 173         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 174         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 175         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 176         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 177         flavors.
 178         * i386-tbl.h: Re-generate.
 179
 180 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 183         register operands.
 184         * i386-tbl.h: Re-generate.
 185
 186 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 189         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 190         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 191         * i386-tbl.h: Re-generate.
 192
 193 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 196         Disp8MemShift from register only templates.
 197         * i386-tbl.h: Re-generate.
 198
 199 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 202         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 203         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 204         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 205         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 206         EVEX_W_0F11_P_3_M_1): Delete.
 207         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 208         EVEX_W_0F11_P_3): New.
 209         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 210         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 211         MOD_EVEX_0F11_PREFIX_3 table entries.
 212         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 213         PREFIX_EVEX_0F11 table entries.
 214         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 215         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 216         EVEX_W_0F11_P_3_M_{0,1} table entries.
 217
 218 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 221         Delete.
 222
 223 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         PR binutils/24719
 226         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 227         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 228         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 229         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 230         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 231         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 232         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 233         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 234         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 235         PREFIX_EVEX_0F38C6_REG_6 entries.
 236         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 237         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 238         EVEX_W_0F38C7_R_6_P_2 entries.
 239         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 240         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 241         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 242         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 243         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 244         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 245         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 246
 247 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 250         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 251         VEX_LEN_0F2D_P_3): Delete.
 252         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 253         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 254         (prefix_table): ... here.
 255
 256 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-dis.c (Iq): Delete.
 259         (Id): New.
 260         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 261         TBM insns.
 262         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 263         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 264         (OP_E_memory): Also honor needindex when deciding whether an
 265         address size prefix needs printing.
 266         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 267
 268 2019-06-26  Jim Wilson  <jimw@sifive.com>
 269
 270         PR binutils/24739
 271         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 272         Set info->display_endian to info->endian_code.
 273
 274 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 275
 276         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 277         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 278         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 279         OPERAND_TYPE_ACC64 entries.
 280         * i386-init.h: Re-generate.
 281
 282 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 285         Delete.
 286         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 287         of dqa_mode.
 288         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 289         entries here.
 290         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 291         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 292
 293 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 296         variables.
 297
 298 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 301         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 302         movnti.
 303         * i386-opc.tbl (movnti): Add IgnoreSize.
 304         * i386-tbl.h: Re-generate.
 305
 306 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 309         * i386-tbl.h: Re-generate.
 310
 311 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 312
 313         * i386-dis-evex.h: Break into ...
 314         * i386-dis-evex-len.h: New file.
 315         * i386-dis-evex-mod.h: Likewise.
 316         * i386-dis-evex-prefix.h: Likewise.
 317         * i386-dis-evex-reg.h: Likewise.
 318         * i386-dis-evex-w.h: Likewise.
 319         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 320         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 321         i386-dis-evex-mod.h.
 322
 323 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         PR binutils/24700
 326         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 327         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 328         EVEX_W_0F385B_P_2.
 329         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 330         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 331         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 332         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 333         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 334         EVEX_LEN_0F385B_P_2_W_1.
 335         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 336         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 337         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 338         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 339         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 340         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 341         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 342         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 343         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 344         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 345
 346 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 347
 348         PR binutils/24691
 349         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 350         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 351         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 352         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 353         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 354         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 355         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 356         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 357         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 358         EVEX_LEN_0F3A43_P_2_W_1.
 359         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 360         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 361         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 362         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 363         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 364         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 365         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 366         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 367         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 368         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 369         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 370         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 371
 372 2019-06-14  Nick Clifton  <nickc@redhat.com>
 373
 374         * po/fr.po; Updated French translation.
 375
 376 2019-06-13  Stafford Horne  <shorne@gmail.com>
 377
 378         * or1k-asm.c: Regenerated.
 379         * or1k-desc.c: Regenerated.
 380         * or1k-desc.h: Regenerated.
 381         * or1k-dis.c: Regenerated.
 382         * or1k-ibld.c: Regenerated.
 383         * or1k-opc.c: Regenerated.
 384         * or1k-opc.h: Regenerated.
 385         * or1k-opinst.c: Regenerated.
 386
 387 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 388
 389         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 390
 391 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 392
 393         PR binutils/24633
 394         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 395         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 396         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 397         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 398         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 399         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 400         EVEX_LEN_0F3A1B_P_2_W_1.
 401         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 402         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 403         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 404         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 405         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 406         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 407         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 408         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 409
 410 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 411
 412         PR binutils/24626
 413         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 414         EVEX.vvvv when disassembling VEX and EVEX instructions.
 415         (OP_VEX): Set vex.register_specifier to 0 after readding
 416         vex.register_specifier.
 417         (OP_Vex_2src_1): Likewise.
 418         (OP_Vex_2src_2): Likewise.
 419         (OP_LWP_E): Likewise.
 420         (OP_EX_Vex): Don't check vex.register_specifier.
 421         (OP_XMM_Vex): Likewise.
 422
 423 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 424             Lili Cui  <lili.cui@intel.com>
 425
 426         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 427         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 428         instructions.
 429         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 430         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 431         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 432         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 433         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 434         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 435         * i386-init.h: Regenerated.
 436         * i386-tbl.h: Likewise.
 437
 438 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 439             Lili Cui  <lili.cui@intel.com>
 440
 441         * doc/c-i386.texi: Document enqcmd.
 442         * testsuite/gas/i386/enqcmd-intel.d: New file.
 443         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 444         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 445         * testsuite/gas/i386/enqcmd.d: Likewise.
 446         * testsuite/gas/i386/enqcmd.s: Likewise.
 447         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 448         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 449         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 450         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 451         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 452         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 453         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 454         and x86-64-enqcmd.
 455
 456 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 457
 458         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 459
 460 2019-06-03  Alan Modra  <amodra@gmail.com>
 461
 462         * ppc-dis.c (prefix_opcd_indices): Correct size.
 463
 464 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         PR gas/24625
 467         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 468         Disp8ShiftVL.
 469         * i386-tbl.h: Regenerated.
 470
 471 2019-05-24  Alan Modra  <amodra@gmail.com>
 472
 473         * po/POTFILES.in: Regenerate.
 474
 475 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 476             Alan Modra  <amodra@gmail.com>
 477
 478         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 479         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 480         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 481         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 482         XTOP>): Define and add entries.
 483         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 484         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 485         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 486         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 487
 488 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 489             Alan Modra  <amodra@gmail.com>
 490
 491         * ppc-dis.c (ppc_opts): Add "future" entry.
 492         (PREFIX_OPCD_SEGS): Define.
 493         (prefix_opcd_indices): New array.
 494         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 495         (lookup_prefix): New function.
 496         (print_insn_powerpc): Handle 64-bit prefix instructions.
 497         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 498         (PMRR, POWERXX): Define.
 499         (prefix_opcodes): New instruction table.
 500         (prefix_num_opcodes): New constant.
 501
 502 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 503
 504         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 505         * configure: Regenerated.
 506         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 507         and cpu/bpf.opc.
 508         (HFILES): Add bpf-desc.h and bpf-opc.h.
 509         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 510         bpf-ibld.c and bpf-opc.c.
 511         (BPF_DEPS): Define.
 512         * Makefile.in: Regenerated.
 513         * disassemble.c (ARCH_bpf): Define.
 514         (disassembler): Add case for bfd_arch_bpf.
 515         (disassemble_init_for_target): Likewise.
 516         (enum epbf_isa_attr): Define.
 517         * disassemble.h: extern print_insn_bpf.
 518         * bpf-asm.c: Generated.
 519         * bpf-opc.h: Likewise.
 520         * bpf-opc.c: Likewise.
 521         * bpf-ibld.c: Likewise.
 522         * bpf-dis.c: Likewise.
 523         * bpf-desc.h: Likewise.
 524         * bpf-desc.c: Likewise.
 525
 526 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 527
 528         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 529         and VMSR with the new operands.
 530
 531 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 532
 533         * arm-dis.c (enum mve_instructions): New enum
 534         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 535         and cneg.
 536         (mve_opcodes): New instructions as above.
 537         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 538         csneg and csel.
 539         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 540
 541 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 542
 543         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 544         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 545         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 546         uqshl, urshrl and urshr.
 547         (is_mve_okay_in_it): Add new instructions to TRUE list.
 548         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 549         (print_insn_mve): Updated to accept new %j,
 550         %<bitfield>m and %<bitfield>n patterns.
 551
 552 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 553
 554         * mips-opc.c (mips_builtin_opcodes): Change source register
 555         constraint for DAUI.
 556
 557 2019-05-20  Nick Clifton  <nickc@redhat.com>
 558
 559         * po/fr.po: Updated French translation.
 560
 561 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 562             Michael Collison <michael.collison@arm.com>
 563
 564         * arm-dis.c (thumb32_opcodes): Add new instructions.
 565         (enum mve_instructions): Likewise.
 566         (enum mve_undefined): Add new reasons.
 567         (is_mve_encoding_conflict): Handle new instructions.
 568         (is_mve_undefined): Likewise.
 569         (is_mve_unpredictable): Likewise.
 570         (print_mve_undefined): Likewise.
 571         (print_mve_size): Likewise.
 572
 573 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 574             Michael Collison <michael.collison@arm.com>
 575
 576         * arm-dis.c (thumb32_opcodes): Add new instructions.
 577         (enum mve_instructions): Likewise.
 578         (is_mve_encoding_conflict): Handle new instructions.
 579         (is_mve_undefined): Likewise.
 580         (is_mve_unpredictable): Likewise.
 581         (print_mve_size): Likewise.
 582
 583 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 584             Michael Collison <michael.collison@arm.com>
 585
 586         * arm-dis.c (thumb32_opcodes): Add new instructions.
 587         (enum mve_instructions): Likewise.
 588         (is_mve_encoding_conflict): Likewise.
 589         (is_mve_unpredictable): Likewise.
 590         (print_mve_size): Likewise.
 591
 592 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 593             Michael Collison <michael.collison@arm.com>
 594
 595         * arm-dis.c (thumb32_opcodes): Add new instructions.
 596         (enum mve_instructions): Likewise.
 597         (is_mve_encoding_conflict): Handle new instructions.
 598         (is_mve_undefined): Likewise.
 599         (is_mve_unpredictable): Likewise.
 600         (print_mve_size): Likewise.
 601
 602 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 603             Michael Collison <michael.collison@arm.com>
 604
 605         * arm-dis.c (thumb32_opcodes): Add new instructions.
 606         (enum mve_instructions): Likewise.
 607         (is_mve_encoding_conflict): Handle new instructions.
 608         (is_mve_undefined): Likewise.
 609         (is_mve_unpredictable): Likewise.
 610         (print_mve_size): Likewise.
 611         (print_insn_mve): Likewise.
 612
 613 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 614             Michael Collison <michael.collison@arm.com>
 615
 616         * arm-dis.c (thumb32_opcodes): Add new instructions.
 617         (print_insn_thumb32): Handle new instructions.
 618
 619 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 620             Michael Collison <michael.collison@arm.com>
 621
 622         * arm-dis.c (enum mve_instructions): Add new instructions.
 623         (enum mve_undefined): Add new reasons.
 624         (is_mve_encoding_conflict): Handle new instructions.
 625         (is_mve_undefined): Likewise.
 626         (is_mve_unpredictable): Likewise.
 627         (print_mve_undefined): Likewise.
 628         (print_mve_size): Likewise.
 629         (print_mve_shift_n): Likewise.
 630         (print_insn_mve): Likewise.
 631
 632 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 633             Michael Collison <michael.collison@arm.com>
 634
 635         * arm-dis.c (enum mve_instructions): Add new instructions.
 636         (is_mve_encoding_conflict): Handle new instructions.
 637         (is_mve_unpredictable): Likewise.
 638         (print_mve_rotate): Likewise.
 639         (print_mve_size): Likewise.
 640         (print_insn_mve): Likewise.
 641
 642 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 643             Michael Collison <michael.collison@arm.com>
 644
 645         * arm-dis.c (enum mve_instructions): Add new instructions.
 646         (is_mve_encoding_conflict): Handle new instructions.
 647         (is_mve_unpredictable): Likewise.
 648         (print_mve_size): Likewise.
 649         (print_insn_mve): Likewise.
 650
 651 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 652             Michael Collison <michael.collison@arm.com>
 653
 654         * arm-dis.c (enum mve_instructions): Add new instructions.
 655         (enum mve_undefined): Add new reasons.
 656         (is_mve_encoding_conflict): Handle new instructions.
 657         (is_mve_undefined): Likewise.
 658         (is_mve_unpredictable): Likewise.
 659         (print_mve_undefined): Likewise.
 660         (print_mve_size): Likewise.
 661         (print_insn_mve): Likewise.
 662
 663 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 664             Michael Collison <michael.collison@arm.com>
 665
 666         * arm-dis.c (enum mve_instructions): Add new instructions.
 667         (is_mve_encoding_conflict): Handle new instructions.
 668         (is_mve_undefined): Likewise.
 669         (is_mve_unpredictable): Likewise.
 670         (print_mve_size): Likewise.
 671         (print_insn_mve): Likewise.
 672
 673 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 674             Michael Collison <michael.collison@arm.com>
 675
 676         * arm-dis.c (enum mve_instructions): Add new instructions.
 677         (enum mve_unpredictable): Add new reasons.
 678         (enum mve_undefined): Likewise.
 679         (is_mve_okay_in_it): Handle new isntructions.
 680         (is_mve_encoding_conflict): Likewise.
 681         (is_mve_undefined): Likewise.
 682         (is_mve_unpredictable): Likewise.
 683         (print_mve_vmov_index): Likewise.
 684         (print_simd_imm8): Likewise.
 685         (print_mve_undefined): Likewise.
 686         (print_mve_unpredictable): Likewise.
 687         (print_mve_size): Likewise.
 688         (print_insn_mve): Likewise.
 689
 690 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 691             Michael Collison <michael.collison@arm.com>
 692
 693         * arm-dis.c (enum mve_instructions): Add new instructions.
 694         (enum mve_unpredictable): Add new reasons.
 695         (enum mve_undefined): Likewise.
 696         (is_mve_encoding_conflict): Handle new instructions.
 697         (is_mve_undefined): Likewise.
 698         (is_mve_unpredictable): Likewise.
 699         (print_mve_undefined): Likewise.
 700         (print_mve_unpredictable): Likewise.
 701         (print_mve_rounding_mode): Likewise.
 702         (print_mve_vcvt_size): Likewise.
 703         (print_mve_size): Likewise.
 704         (print_insn_mve): Likewise.
 705
 706 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 707             Michael Collison <michael.collison@arm.com>
 708
 709         * arm-dis.c (enum mve_instructions): Add new instructions.
 710         (enum mve_unpredictable): Add new reasons.
 711         (enum mve_undefined): Likewise.
 712         (is_mve_undefined): Handle new instructions.
 713         (is_mve_unpredictable): Likewise.
 714         (print_mve_undefined): Likewise.
 715         (print_mve_unpredictable): Likewise.
 716         (print_mve_size): Likewise.
 717         (print_insn_mve): Likewise.
 718
 719 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 720             Michael Collison <michael.collison@arm.com>
 721
 722         * arm-dis.c (enum mve_instructions): Add new instructions.
 723         (enum mve_undefined): Add new reasons.
 724         (insns): Add new instructions.
 725         (is_mve_encoding_conflict):
 726         (print_mve_vld_str_addr): New print function.
 727         (is_mve_undefined): Handle new instructions.
 728         (is_mve_unpredictable): Likewise.
 729         (print_mve_undefined): Likewise.
 730         (print_mve_size): Likewise.
 731         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 732         (print_insn_mve):  Handle new operands.
 733
 734 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 735             Michael Collison <michael.collison@arm.com>
 736
 737         * arm-dis.c (enum mve_instructions): Add new instructions.
 738         (enum mve_unpredictable): Add new reasons.
 739         (is_mve_encoding_conflict): Handle new instructions.
 740         (is_mve_unpredictable): Likewise.
 741         (mve_opcodes): Add new instructions.
 742         (print_mve_unpredictable): Handle new reasons.
 743         (print_mve_register_blocks): New print function.
 744         (print_mve_size): Handle new instructions.
 745         (print_insn_mve): Likewise.
 746
 747 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 748             Michael Collison <michael.collison@arm.com>
 749
 750         * arm-dis.c (enum mve_instructions): Add new instructions.
 751         (enum mve_unpredictable): Add new reasons.
 752         (enum mve_undefined): Likewise.
 753         (is_mve_encoding_conflict): Handle new instructions.
 754         (is_mve_undefined): Likewise.
 755         (is_mve_unpredictable): Likewise.
 756         (coprocessor_opcodes): Move NEON VDUP from here...
 757         (neon_opcodes): ... to here.
 758         (mve_opcodes): Add new instructions.
 759         (print_mve_undefined):  Handle new reasons.
 760         (print_mve_unpredictable): Likewise.
 761         (print_mve_size): Handle new instructions.
 762         (print_insn_neon): Handle vdup.
 763         (print_insn_mve): Handle new operands.
 764
 765 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 766             Michael Collison <michael.collison@arm.com>
 767
 768         * arm-dis.c (enum mve_instructions): Add new instructions.
 769         (enum mve_unpredictable): Add new values.
 770         (mve_opcodes): Add new instructions.
 771         (vec_condnames): New array with vector conditions.
 772         (mve_predicatenames): New array with predicate suffixes.
 773         (mve_vec_sizename): New array with vector sizes.
 774         (enum vpt_pred_state): New enum with vector predication states.
 775         (struct vpt_block): New struct type for vpt blocks.
 776         (vpt_block_state): Global struct to keep track of state.
 777         (mve_extract_pred_mask): New helper function.
 778         (num_instructions_vpt_block): Likewise.
 779         (mark_outside_vpt_block): Likewise.
 780         (mark_inside_vpt_block): Likewise.
 781         (invert_next_predicate_state): Likewise.
 782         (update_next_predicate_state): Likewise.
 783         (update_vpt_block_state): Likewise.
 784         (is_vpt_instruction): Likewise.
 785         (is_mve_encoding_conflict): Add entries for new instructions.
 786         (is_mve_unpredictable): Likewise.
 787         (print_mve_unpredictable): Handle new cases.
 788         (print_instruction_predicate): Likewise.
 789         (print_mve_size): New function.
 790         (print_vec_condition): New function.
 791         (print_insn_mve): Handle vpt blocks and new print operands.
 792
 793 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 794
 795         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 796         8, 14 and 15 for Armv8.1-M Mainline.
 797
 798 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 799             Michael Collison <michael.collison@arm.com>
 800
 801         * arm-dis.c (enum mve_instructions): New enum.
 802         (enum mve_unpredictable): Likewise.
 803         (enum mve_undefined): Likewise.
 804         (struct mopcode32): New struct.
 805         (is_mve_okay_in_it): New function.
 806         (is_mve_architecture): Likewise.
 807         (arm_decode_field): Likewise.
 808         (arm_decode_field_multiple): Likewise.
 809         (is_mve_encoding_conflict): Likewise.
 810         (is_mve_undefined): Likewise.
 811         (is_mve_unpredictable): Likewise.
 812         (print_mve_undefined): Likewise.
 813         (print_mve_unpredictable): Likewise.
 814         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 815         (print_insn_mve): New function.
 816         (print_insn_thumb32): Handle MVE architecture.
 817         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 818
 819 2019-05-10  Nick Clifton  <nickc@redhat.com>
 820
 821         PR 24538
 822         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 823         end of the table prematurely.
 824
 825 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 826
 827         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 828         macros for R6.
 829
 830 2019-05-11  Alan Modra  <amodra@gmail.com>
 831
 832         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 833         when -Mraw is in effect.
 834
 835 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 836
 837         * aarch64-dis-2.c: Regenerate.
 838         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 839         (OP_SVE_BBB): New variant set.
 840         (OP_SVE_DDDD): New variant set.
 841         (OP_SVE_HHH): New variant set.
 842         (OP_SVE_HHHU): New variant set.
 843         (OP_SVE_SSS): New variant set.
 844         (OP_SVE_SSSU): New variant set.
 845         (OP_SVE_SHH): New variant set.
 846         (OP_SVE_SBBU): New variant set.
 847         (OP_SVE_DSS): New variant set.
 848         (OP_SVE_DHHU): New variant set.
 849         (OP_SVE_VMV_HSD_BHS): New variant set.
 850         (OP_SVE_VVU_HSD_BHS): New variant set.
 851         (OP_SVE_VVVU_SD_BH): New variant set.
 852         (OP_SVE_VVVU_BHSD): New variant set.
 853         (OP_SVE_VVV_QHD_DBS): New variant set.
 854         (OP_SVE_VVV_HSD_BHS): New variant set.
 855         (OP_SVE_VVV_HSD_BHS2): New variant set.
 856         (OP_SVE_VVV_BHS_HSD): New variant set.
 857         (OP_SVE_VV_BHS_HSD): New variant set.
 858         (OP_SVE_VVV_SD): New variant set.
 859         (OP_SVE_VVU_BHS_HSD): New variant set.
 860         (OP_SVE_VZVV_SD): New variant set.
 861         (OP_SVE_VZVV_BH): New variant set.
 862         (OP_SVE_VZV_SD): New variant set.
 863         (aarch64_opcode_table): Add sve2 instructions.
 864
 865 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 866
 867         * aarch64-asm-2.c: Regenerated.
 868         * aarch64-dis-2.c: Regenerated.
 869         * aarch64-opc-2.c: Regenerated.
 870         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 871         for SVE_SHLIMM_UNPRED_22.
 872         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 873         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 874         operand.
 875
 876 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 877
 878         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 879         sve_size_tsz_bhs iclass encode.
 880         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 881         sve_size_tsz_bhs iclass decode.
 882
 883 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 884
 885         * aarch64-asm-2.c: Regenerated.
 886         * aarch64-dis-2.c: Regenerated.
 887         * aarch64-opc-2.c: Regenerated.
 888         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 889         for SVE_Zm4_11_INDEX.
 890         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 891         (fields): Handle SVE_i2h field.
 892         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 893         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 894
 895 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 896
 897         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 898         sve_shift_tsz_bhsd iclass encode.
 899         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 900         sve_shift_tsz_bhsd iclass decode.
 901
 902 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 903
 904         * aarch64-asm-2.c: Regenerated.
 905         * aarch64-dis-2.c: Regenerated.
 906         * aarch64-opc-2.c: Regenerated.
 907         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 908         (aarch64_encode_variant_using_iclass): Handle
 909         sve_shift_tsz_hsd iclass encode.
 910         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 911         sve_shift_tsz_hsd iclass decode.
 912         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 913         for SVE_SHRIMM_UNPRED_22.
 914         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 915         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 916         operand.
 917
 918 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 919
 920         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 921         sve_size_013 iclass encode.
 922         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 923         sve_size_013 iclass decode.
 924
 925 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 926
 927         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 928         sve_size_bh iclass encode.
 929         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 930         sve_size_bh iclass decode.
 931
 932 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 933
 934         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 935         sve_size_sd2 iclass encode.
 936         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 937         sve_size_sd2 iclass decode.
 938         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 939         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 940
 941 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 942
 943         * aarch64-asm-2.c: Regenerated.
 944         * aarch64-dis-2.c: Regenerated.
 945         * aarch64-opc-2.c: Regenerated.
 946         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 947         for SVE_ADDR_ZX.
 948         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 949         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 950
 951 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 952
 953         * aarch64-asm-2.c: Regenerated.
 954         * aarch64-dis-2.c: Regenerated.
 955         * aarch64-opc-2.c: Regenerated.
 956         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 957         for SVE_Zm3_11_INDEX.
 958         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 959         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 960         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 961         fields.
 962         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 963
 964 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 965
 966         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 967         sve_size_hsd2 iclass encode.
 968         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 969         sve_size_hsd2 iclass decode.
 970         * aarch64-opc.c (fields): Handle SVE_size field.
 971         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 972
 973 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 974
 975         * aarch64-asm-2.c: Regenerated.
 976         * aarch64-dis-2.c: Regenerated.
 977         * aarch64-opc-2.c: Regenerated.
 978         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 979         for SVE_IMM_ROT3.
 980         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 981         (fields): Handle SVE_rot3 field.
 982         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 983         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 984
 985 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 986
 987         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 988         instructions.
 989
 990 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 991
 992         * aarch64-tbl.h
 993         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 994         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 995         aarch64_feature_sve2bitperm): New feature sets.
 996         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 997         for feature set addresses.
 998         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 999         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1000
1001 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1002             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1003
1004         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1005         argument and set ASE_EVA_R6 appropriately.
1006         (set_default_mips_dis_options): Pass ISA to above.
1007         (parse_mips_dis_option): Likewise.
1008         * mips-opc.c (EVAR6): New macro.
1009         (mips_builtin_opcodes): Add llwpe, scwpe.
1010
1011 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1012
1013         * aarch64-asm-2.c: Regenerated.
1014         * aarch64-dis-2.c: Regenerated.
1015         * aarch64-opc-2.c: Regenerated.
1016         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1017         AARCH64_OPND_TME_UIMM16.
1018         (aarch64_print_operand): Likewise.
1019         * aarch64-tbl.h (QL_IMM_NIL): New.
1020         (TME): New.
1021         (_TME_INSN): New.
1022         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1023
1024 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1025
1026         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1027
1028 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1029             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1030
1031         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1032
1033 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1034
1035         * s12z-opc.h: Add extern "C" bracketing to help
1036         users who wish to use this interface in c++ code.
1037
1038 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1039
1040         * s12z-opc.c (bm_decode): Handle bit map operations with the
1041         "reserved0" mode.
1042
1043 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1044
1045         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1046         specifier.  Add entries for VLDR and VSTR of system registers.
1047         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1048         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1049         of %J and %K format specifier.
1050
1051 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1052
1053         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1054         Add new entries for VSCCLRM instruction.
1055         (print_insn_coprocessor): Handle new %C format control code.
1056
1057 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1058
1059         * arm-dis.c (enum isa): New enum.
1060         (struct sopcode32): New structure.
1061         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1062         set isa field of all current entries to ANY.
1063         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1064         Only match an entry if its isa field allows the current mode.
1065
1066 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1067
1068         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1069         CLRM.
1070         (print_insn_thumb32): Add logic to print %n CLRM register list.
1071
1072 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1073
1074         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1075         and %Q patterns.
1076
1077 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1078
1079         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1080         (print_insn_thumb32): Edit the switch case for %Z.
1081
1082 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1083
1084         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1085
1086 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1087
1088         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1089
1090 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1091
1092         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1093
1094 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1095
1096         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1097         Arm register with r13 and r15 unpredictable.
1098         (thumb32_opcodes): New instructions for bfx and bflx.
1099
1100 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1101
1102         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1103
1104 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1105
1106         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1107
1108 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1109
1110         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1111
1112 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1113
1114         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1115
1116 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1117
1118         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1119         "optr". ("operator" is a reserved word in c++).
1120
1121 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1122
1123         * aarch64-opc.c (aarch64_print_operand): Add case for
1124         AARCH64_OPND_Rt_SP.
1125         (verify_constraints): Likewise.
1126         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1127         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1128         to accept Rt|SP as first operand.
1129         (AARCH64_OPERANDS): Add new Rt_SP.
1130         * aarch64-asm-2.c: Regenerated.
1131         * aarch64-dis-2.c: Regenerated.
1132         * aarch64-opc-2.c: Regenerated.
1133
1134 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1135
1136         * aarch64-asm-2.c: Regenerated.
1137         * aarch64-dis-2.c: Likewise.
1138         * aarch64-opc-2.c: Likewise.
1139         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1140
1141 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1142
1143         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1144
1145 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1146
1147         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1148         * i386-init.h: Regenerated.
1149
1150 2019-04-07  Alan Modra  <amodra@gmail.com>
1151
1152         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1153         op_separator to control printing of spaces, comma and parens
1154         rather than need_comma, need_paren and spaces vars.
1155
1156 2019-04-07  Alan Modra  <amodra@gmail.com>
1157
1158         PR 24421
1159         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1160         (print_insn_neon, print_insn_arm): Likewise.
1161
1162 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1163
1164         * i386-dis-evex.h (evex_table): Updated to support BF16
1165         instructions.
1166         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1167         and EVEX_W_0F3872_P_3.
1168         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1169         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1170         * i386-opc.h (enum): Add CpuAVX512_BF16.
1171         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1172         * i386-opc.tbl: Add AVX512 BF16 instructions.
1173         * i386-init.h: Regenerated.
1174         * i386-tbl.h: Likewise.
1175
1176 2019-04-05  Alan Modra  <amodra@gmail.com>
1177
1178         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1179         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1180         to favour printing of "-" branch hint when using the "y" bit.
1181         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1182
1183 2019-04-05  Alan Modra  <amodra@gmail.com>
1184
1185         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1186         opcode until first operand is output.
1187
1188 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1189
1190         PR gas/24349
1191         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1192         (valid_bo_post_v2): Add support for 'at' branch hints.
1193         (insert_bo): Only error on branch on ctr.
1194         (get_bo_hint_mask): New function.
1195         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1196         for inserting 'at' branch hints.
1197         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1198         for extracting 'at' branch hints.
1199         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1200         (BOE): Delete operand.
1201         (BOM, BOP): New operands.
1202         (RM): Update value.
1203         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1204         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1205         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1206         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1207         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1208         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1209         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1210         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1211         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1212         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1213         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1214         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1215         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1216         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1217         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1218         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1219         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1220         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1221         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1222         bttarl+>: New extended mnemonics.
1223
1224 2019-03-28  Alan Modra  <amodra@gmail.com>
1225
1226         PR 24390
1227         * ppc-opc.c (BTF): Define.
1228         (powerpc_opcodes): Use for mtfsb*.
1229         * ppc-dis.c (print_insn_powerpc): Print fields with both
1230         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1231
1232 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1233
1234         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1235         (mapping_symbol_for_insn): Implement new algorithm.
1236         (print_insn): Remove duplicate code.
1237
1238 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1239
1240         * aarch64-dis.c (print_insn_aarch64):
1241         Implement override.
1242
1243 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1244
1245         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1246         order.
1247
1248 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1249
1250         * aarch64-dis.c (last_stop_offset): New.
1251         (print_insn_aarch64): Use stop_offset.
1252
1253 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1254
1255         PR gas/24359
1256         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1257         CPU_ANY_AVX2_FLAGS.
1258         * i386-init.h: Regenerated.
1259
1260 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1261
1262         PR gas/24348
1263         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1264         vmovdqu16, vmovdqu32 and vmovdqu64.
1265         * i386-tbl.h: Regenerated.
1266
1267 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1268
1269         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1270         from vstrszb, vstrszh, and vstrszf.
1271
1272 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1273
1274         * s390-opc.txt: Add instruction descriptions.
1275
1276 2019-02-08  Jim Wilson  <jimw@sifive.com>
1277
1278         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1279         <bne>: Likewise.
1280
1281 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1282
1283         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1284
1285 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1286
1287         PR binutils/23212
1288         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1289         * aarch64-opc.c (verify_elem_sd): New.
1290         (fields): Add FLD_sz entr.
1291         * aarch64-tbl.h (_SIMD_INSN): New.
1292         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1293         fmulx scalar and vector by element isns.
1294
1295 2019-02-07  Nick Clifton  <nickc@redhat.com>
1296
1297         * po/sv.po: Updated Swedish translation.
1298
1299 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1300
1301         * s390-mkopc.c (main): Accept arch13 as cpu string.
1302         * s390-opc.c: Add new instruction formats and instruction opcode
1303         masks.
1304         * s390-opc.txt: Add new arch13 instructions.
1305
1306 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1307
1308         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1309         (aarch64_opcode): Change encoding for stg, stzg
1310         st2g and st2zg.
1311         * aarch64-asm-2.c: Regenerated.
1312         * aarch64-dis-2.c: Regenerated.
1313         * aarch64-opc-2.c: Regenerated.
1314
1315 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1316
1317         * aarch64-asm-2.c: Regenerated.
1318         * aarch64-dis-2.c: Likewise.
1319         * aarch64-opc-2.c: Likewise.
1320         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1321
1322 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1323             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1324
1325         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1326         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1327         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1328         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1329         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1330         case for ldstgv_indexed.
1331         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1332         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1333         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1334         * aarch64-asm-2.c: Regenerated.
1335         * aarch64-dis-2.c: Regenerated.
1336         * aarch64-opc-2.c: Regenerated.
1337
1338 2019-01-23  Nick Clifton  <nickc@redhat.com>
1339
1340         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1341
1342 2019-01-21  Nick Clifton  <nickc@redhat.com>
1343
1344         * po/de.po: Updated German translation.
1345         * po/uk.po: Updated Ukranian translation.
1346
1347 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1348         * mips-dis.c (mips_arch_choices): Fix typo in
1349         gs464, gs464e and gs264e descriptors.
1350
1351 2019-01-19  Nick Clifton  <nickc@redhat.com>
1352
1353         * configure: Regenerate.
1354         * po/opcodes.pot: Regenerate.
1355
1356 2018-06-24  Nick Clifton  <nickc@redhat.com>
1357
1358         2.32 branch created.
1359
1360 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1361
1362         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1363         if it is null.
1364         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1365         zero.
1366
1367 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1368
1369         * configure: Regenerate.
1370
1371 2019-01-07  Alan Modra  <amodra@gmail.com>
1372
1373         * configure: Regenerate.
1374         * po/POTFILES.in: Regenerate.
1375
1376 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1377
1378         * s12z-opc.c: New file.
1379         * s12z-opc.h: New file.
1380         * s12z-dis.c: Removed all code not directly related to display
1381         of instructions.  Used the interface provided by the new files
1382         instead.
1383         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1384         * Makefile.in: Regenerate.
1385         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1386         * configure: Regenerate.
1387
1388 2019-01-01  Alan Modra  <amodra@gmail.com>
1389
1390         Update year range in copyright notice of all files.
1391
1392 For older changes see ChangeLog-2018
1393 \f
1394 Copyright (C) 2019 Free Software Foundation, Inc.
1395
1396 Copying and distribution of this file, with or without modification,
1397 are permitted in any medium without royalty provided the copyright
1398 notice and this notice are preserved.
1399
1400 Local Variables:
1401 mode: change-log
1402 left-margin: 8
1403 fill-column: 74
1404 version-control: never
1405 End: