1 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
2 Edmar Wienskoski <edmar.wienskoski@nxp.com>
4 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
5 PPC_OPCODE_EFS2 flag to "e200z4" entry.
6 New entries efs2 and spe2.
7 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
8 (SPE2_OPCD_SEGS): New macro.
9 (spe2_opcd_indices): New.
10 (disassemble_init_powerpc): Handle SPE2 opcodes.
11 (lookup_spe2): New function.
12 (print_insn_powerpc): call lookup_spe2.
13 * ppc-opc.c (insert_evuimm1_ex0): New function.
14 (extract_evuimm1_ex0): Likewise.
15 (insert_evuimm_lt8): Likewise.
16 (extract_evuimm_lt8): Likewise.
17 (insert_off_spe2): Likewise.
18 (extract_off_spe2): Likewise.
19 (insert_Ddd): Likewise.
20 (extract_Ddd): Likewise.
22 (EVUIMM_LT8): Likewise.
23 (EVUIMM_LT16): Adjust.
26 (EVUIMM_1_EX0): Likewise.
29 (VX_OFF_SPE2): Likewise.
32 (VX_MASK_DDD): New mask.
34 (VX_RA_CONST): New macro.
35 (VX_RA_CONST_MASK): Likewise.
36 (VX_RB_CONST): Likewise.
37 (VX_RB_CONST_MASK): Likewise.
38 (VX_OFF_SPE2_MASK): Likewise.
39 (VX_SPE_CRFD): Likewise.
40 (VX_SPE_CRFD_MASK VX): Likewise.
41 (VX_SPE2_CLR): Likewise.
42 (VX_SPE2_CLR_MASK): Likewise.
43 (VX_SPE2_SPLATB): Likewise.
44 (VX_SPE2_SPLATB_MASK): Likewise.
45 (VX_SPE2_OCTET): Likewise.
46 (VX_SPE2_OCTET_MASK): Likewise.
47 (VX_SPE2_DDHH): Likewise.
48 (VX_SPE2_DDHH_MASK): Likewise.
49 (VX_SPE2_HH): Likewise.
50 (VX_SPE2_HH_MASK): Likewise.
51 (VX_SPE2_EVMAR): Likewise.
52 (VX_SPE2_EVMAR_MASK): Likewise.
55 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
56 (powerpc_macros): Map old SPE instructions have new names
57 with the same opcodes. Add SPE2 instructions which just are
59 (spe2_opcodes): Add SPE2 opcodes.
61 2017-08-23 Alan Modra <amodra@gmail.com>
63 * ppc-opc.c: Formatting and comment fixes. Move insert and
64 extract functions earlier, deleting forward declarations.
65 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
68 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
70 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
72 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
73 Edmar Wienskoski <edmar.wienskoski@nxp.com>
75 * ppc-opc.c (insert_evuimm2_ex0): New function.
76 (extract_evuimm2_ex0): Likewise.
77 (insert_evuimm4_ex0): Likewise.
78 (extract_evuimm4_ex0): Likewise.
79 (insert_evuimm8_ex0): Likewise.
80 (extract_evuimm8_ex0): Likewise.
81 (insert_evuimm_lt16): Likewise.
82 (extract_evuimm_lt16): Likewise.
83 (insert_rD_rS_even): Likewise.
84 (extract_rD_rS_even): Likewise.
85 (insert_off_lsp): Likewise.
86 (extract_off_lsp): Likewise.
87 (RD_EVEN): New operand.
90 (EVUIMM_LT16): New operand.
92 (EVUIMM_2_EX0): New operand.
94 (EVUIMM_4_EX0): New operand.
96 (EVUIMM_8_EX0): New operand.
98 (VX_OFF): New operand.
100 (VX_LSP_MASK): Likewise.
101 (VX_LSP_OFF_MASK): Likewise.
102 (PPC_OPCODE_LSP): Likewise.
103 (vle_opcodes): Add LSP opcodes.
104 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
106 2017-08-09 Jiong Wang <jiong.wang@arm.com>
108 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
109 register operands in CRC instructions.
110 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
113 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
115 * disassemble.c (disassembler): Mark big and mach with
118 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
120 * disassemble.c (disassembler): Remove arch/mach/endian
123 2017-07-25 Nick Clifton <nickc@redhat.com>
126 * arc-opc.c (insert_rhv2): Use lower case first letter in error
128 (insert_r0): Likewise.
129 (insert_r1): Likewise.
130 (insert_r2): Likewise.
131 (insert_r3): Likewise.
132 (insert_sp): Likewise.
133 (insert_gp): Likewise.
134 (insert_pcl): Likewise.
135 (insert_blink): Likewise.
136 (insert_ilink1): Likewise.
137 (insert_ilink2): Likewise.
138 (insert_ras): Likewise.
139 (insert_rbs): Likewise.
140 (insert_rcs): Likewise.
141 (insert_simm3s): Likewise.
142 (insert_rrange): Likewise.
143 (insert_r13el): Likewise.
144 (insert_fpel): Likewise.
145 (insert_blinkel): Likewise.
146 (insert_pclel): Likewise.
147 (insert_nps_bitop_size_2b): Likewise.
148 (insert_nps_imm_offset): Likewise.
149 (insert_nps_imm_entry): Likewise.
150 (insert_nps_size_16bit): Likewise.
151 (insert_nps_##NAME##_pos): Likewise.
152 (insert_nps_##NAME): Likewise.
153 (insert_nps_bitop_ins_ext): Likewise.
154 (insert_nps_##NAME): Likewise.
155 (insert_nps_min_hofs): Likewise.
156 (insert_nps_##NAME): Likewise.
157 (insert_nps_rbdouble_64): Likewise.
158 (insert_nps_misc_imm_offset): Likewise.
159 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
162 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
163 Jiong Wang <jiong.wang@arm.com>
165 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
167 * aarch64-dis-2.c: Regenerated.
169 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
171 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
174 2017-07-20 Nick Clifton <nickc@redhat.com>
176 * po/de.po: Updated German translation.
178 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
180 * arc-regs.h (sec_stat): New aux register.
181 (aux_kernel_sp): Likewise.
182 (aux_sec_u_sp): Likewise.
183 (aux_sec_k_sp): Likewise.
184 (sec_vecbase_build): Likewise.
185 (nsc_table_top): Likewise.
186 (nsc_table_base): Likewise.
187 (ersec_stat): Likewise.
188 (aux_sec_except): Likewise.
190 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
192 * arc-opc.c (extract_uimm12_20): New function.
193 (UIMM12_20): New operand.
195 * arc-tbl.h (sjli): Add new instruction.
197 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
198 John Eric Martin <John.Martin@emmicro-us.com>
200 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
201 (UIMM3_23): Adjust accordingly.
202 * arc-regs.h: Add/correct jli_base register.
203 * arc-tbl.h (jli_s): Likewise.
205 2017-07-18 Nick Clifton <nickc@redhat.com>
208 * aarch64-opc.c: Fix spelling typos.
209 * i386-dis.c: Likewise.
211 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
213 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
214 max_addr_offset and octets variables to size_t.
216 2017-07-12 Alan Modra <amodra@gmail.com>
218 * po/da.po: Update from translationproject.org/latest/opcodes/.
219 * po/de.po: Likewise.
220 * po/es.po: Likewise.
221 * po/fi.po: Likewise.
222 * po/fr.po: Likewise.
223 * po/id.po: Likewise.
224 * po/it.po: Likewise.
225 * po/nl.po: Likewise.
226 * po/pt_BR.po: Likewise.
227 * po/ro.po: Likewise.
228 * po/sv.po: Likewise.
229 * po/tr.po: Likewise.
230 * po/uk.po: Likewise.
231 * po/vi.po: Likewise.
232 * po/zh_CN.po: Likewise.
234 2017-07-11 Yao Qi <yao.qi@linaro.org>
235 Alan Modra <amodra@gmail.com>
237 * cgen.sh: Mark generated files read-only.
238 * epiphany-asm.c: Regenerate.
239 * epiphany-desc.c: Regenerate.
240 * epiphany-desc.h: Regenerate.
241 * epiphany-dis.c: Regenerate.
242 * epiphany-ibld.c: Regenerate.
243 * epiphany-opc.c: Regenerate.
244 * epiphany-opc.h: Regenerate.
245 * fr30-asm.c: Regenerate.
246 * fr30-desc.c: Regenerate.
247 * fr30-desc.h: Regenerate.
248 * fr30-dis.c: Regenerate.
249 * fr30-ibld.c: Regenerate.
250 * fr30-opc.c: Regenerate.
251 * fr30-opc.h: Regenerate.
252 * frv-asm.c: Regenerate.
253 * frv-desc.c: Regenerate.
254 * frv-desc.h: Regenerate.
255 * frv-dis.c: Regenerate.
256 * frv-ibld.c: Regenerate.
257 * frv-opc.c: Regenerate.
258 * frv-opc.h: Regenerate.
259 * ip2k-asm.c: Regenerate.
260 * ip2k-desc.c: Regenerate.
261 * ip2k-desc.h: Regenerate.
262 * ip2k-dis.c: Regenerate.
263 * ip2k-ibld.c: Regenerate.
264 * ip2k-opc.c: Regenerate.
265 * ip2k-opc.h: Regenerate.
266 * iq2000-asm.c: Regenerate.
267 * iq2000-desc.c: Regenerate.
268 * iq2000-desc.h: Regenerate.
269 * iq2000-dis.c: Regenerate.
270 * iq2000-ibld.c: Regenerate.
271 * iq2000-opc.c: Regenerate.
272 * iq2000-opc.h: Regenerate.
273 * lm32-asm.c: Regenerate.
274 * lm32-desc.c: Regenerate.
275 * lm32-desc.h: Regenerate.
276 * lm32-dis.c: Regenerate.
277 * lm32-ibld.c: Regenerate.
278 * lm32-opc.c: Regenerate.
279 * lm32-opc.h: Regenerate.
280 * lm32-opinst.c: Regenerate.
281 * m32c-asm.c: Regenerate.
282 * m32c-desc.c: Regenerate.
283 * m32c-desc.h: Regenerate.
284 * m32c-dis.c: Regenerate.
285 * m32c-ibld.c: Regenerate.
286 * m32c-opc.c: Regenerate.
287 * m32c-opc.h: Regenerate.
288 * m32r-asm.c: Regenerate.
289 * m32r-desc.c: Regenerate.
290 * m32r-desc.h: Regenerate.
291 * m32r-dis.c: Regenerate.
292 * m32r-ibld.c: Regenerate.
293 * m32r-opc.c: Regenerate.
294 * m32r-opc.h: Regenerate.
295 * m32r-opinst.c: Regenerate.
296 * mep-asm.c: Regenerate.
297 * mep-desc.c: Regenerate.
298 * mep-desc.h: Regenerate.
299 * mep-dis.c: Regenerate.
300 * mep-ibld.c: Regenerate.
301 * mep-opc.c: Regenerate.
302 * mep-opc.h: Regenerate.
303 * mt-asm.c: Regenerate.
304 * mt-desc.c: Regenerate.
305 * mt-desc.h: Regenerate.
306 * mt-dis.c: Regenerate.
307 * mt-ibld.c: Regenerate.
308 * mt-opc.c: Regenerate.
309 * mt-opc.h: Regenerate.
310 * or1k-asm.c: Regenerate.
311 * or1k-desc.c: Regenerate.
312 * or1k-desc.h: Regenerate.
313 * or1k-dis.c: Regenerate.
314 * or1k-ibld.c: Regenerate.
315 * or1k-opc.c: Regenerate.
316 * or1k-opc.h: Regenerate.
317 * or1k-opinst.c: Regenerate.
318 * xc16x-asm.c: Regenerate.
319 * xc16x-desc.c: Regenerate.
320 * xc16x-desc.h: Regenerate.
321 * xc16x-dis.c: Regenerate.
322 * xc16x-ibld.c: Regenerate.
323 * xc16x-opc.c: Regenerate.
324 * xc16x-opc.h: Regenerate.
325 * xstormy16-asm.c: Regenerate.
326 * xstormy16-desc.c: Regenerate.
327 * xstormy16-desc.h: Regenerate.
328 * xstormy16-dis.c: Regenerate.
329 * xstormy16-ibld.c: Regenerate.
330 * xstormy16-opc.c: Regenerate.
331 * xstormy16-opc.h: Regenerate.
333 2017-07-07 Alan Modra <amodra@gmail.com>
335 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
336 * m32c-dis.c: Regenerate.
337 * mep-dis.c: Regenerate.
339 2017-07-05 Borislav Petkov <bp@suse.de>
341 * i386-dis.c: Enable ModRM.reg /6 aliases.
343 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
345 * opcodes/arm-dis.c: Support MVFR2 in disassembly
348 2017-07-04 Tristan Gingold <gingold@adacore.com>
350 * configure: Regenerate.
352 2017-07-03 Tristan Gingold <gingold@adacore.com>
354 * po/opcodes.pot: Regenerate.
356 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
358 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
359 entries to the MSA ASE instruction block.
361 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
362 Maciej W. Rozycki <macro@imgtec.com>
364 * micromips-opc.c (XPA, XPAVZ): New macros.
365 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
368 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
369 Maciej W. Rozycki <macro@imgtec.com>
371 * micromips-opc.c (I36): New macro.
372 (micromips_opcodes): Add "eretnc".
374 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
375 Andrew Bennett <andrew.bennett@imgtec.com>
377 * mips-dis.c (mips_calculate_combination_ases): Handle the
379 (parse_mips_ase_option): New function.
380 (parse_mips_dis_option): Factor out ASE option handling to the
381 new function. Call `mips_calculate_combination_ases'.
382 * mips-opc.c (XPAVZ): New macro.
383 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
384 "mfhgc0", "mthc0" and "mthgc0".
386 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
388 * mips-dis.c (mips_calculate_combination_ases): New function.
389 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
390 calculation to the new function.
391 (set_default_mips_dis_options): Call the new function.
393 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
395 * arc-dis.c (parse_disassembler_options): Use
396 FOR_EACH_DISASSEMBLER_OPTION.
398 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
400 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
401 disassembler option strings.
402 (parse_cpu_option): Likewise.
404 2017-06-28 Tamar Christina <tamar.christina@arm.com>
406 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
407 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
408 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
409 (aarch64_feature_dotprod, DOT_INSN): New.
411 * aarch64-dis-2.c: Regenerated.
413 2017-06-28 Jiong Wang <jiong.wang@arm.com>
415 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
417 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
418 Matthew Fortune <matthew.fortune@imgtec.com>
419 Andrew Bennett <andrew.bennett@imgtec.com>
421 * mips-formats.h (INT_BIAS): New macro.
422 (INT_ADJ): Redefine in INT_BIAS terms.
423 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
424 (mips_print_save_restore): New function.
425 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
426 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
428 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
429 (print_mips16_insn_arg): Call `mips_print_save_restore' for
430 OP_SAVE_RESTORE_LIST handling, factored out from here.
431 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
432 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
433 (mips_builtin_opcodes): Add "restore" and "save" entries.
434 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
436 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
438 2017-06-23 Andrew Waterman <andrew@sifive.com>
440 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
441 alias; do not mark SLTI instruction as an alias.
443 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
445 * i386-dis.c (RM_0FAE_REG_5): Removed.
446 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
447 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
448 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
449 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
450 PREFIX_MOD_3_0F01_REG_5_RM_0.
451 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
452 PREFIX_MOD_3_0FAE_REG_5.
453 (mod_table): Update MOD_0FAE_REG_5.
454 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
455 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
456 * i386-tbl.h: Regenerated.
458 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
460 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
461 * i386-opc.tbl: Likewise.
462 * i386-tbl.h: Regenerated.
464 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
468 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
471 2017-06-19 Nick Clifton <nickc@redhat.com>
474 * score-dis.c (score_opcodes): Add sentinel.
476 2017-06-16 Alan Modra <amodra@gmail.com>
478 * rx-decode.c: Regenerate.
480 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
483 * i386-dis.c (OP_E_register): Check valid bnd register.
486 2017-06-15 Nick Clifton <nickc@redhat.com>
489 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
492 2017-06-15 Nick Clifton <nickc@redhat.com>
495 * rl78-decode.opc (OP_BUF_LEN): Define.
496 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
497 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
499 * rl78-decode.c: Regenerate.
501 2017-06-15 Nick Clifton <nickc@redhat.com>
504 * bfin-dis.c (gregs): Clip index to prevent overflow.
509 2017-06-14 Nick Clifton <nickc@redhat.com>
512 * score7-dis.c (score_opcodes): Add sentinel.
514 2017-06-14 Yao Qi <yao.qi@linaro.org>
516 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
517 * arm-dis.c: Likewise.
518 * ia64-dis.c: Likewise.
519 * mips-dis.c: Likewise.
520 * spu-dis.c: Likewise.
521 * disassemble.h (print_insn_aarch64): New declaration, moved from
523 (print_insn_big_arm, print_insn_big_mips): Likewise.
524 (print_insn_i386, print_insn_ia64): Likewise.
525 (print_insn_little_arm, print_insn_little_mips): Likewise.
527 2017-06-14 Nick Clifton <nickc@redhat.com>
530 * rx-decode.opc: Include libiberty.h
531 (GET_SCALE): New macro - validates access to SCALE array.
532 (GET_PSCALE): New macro - validates access to PSCALE array.
533 (DIs, SIs, S2Is, rx_disp): Use new macros.
534 * rx-decode.c: Regenerate.
536 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
538 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
540 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
542 * arc-dis.c (enforced_isa_mask): Declare.
543 (cpu_types): Likewise.
544 (parse_cpu_option): New function.
545 (parse_disassembler_options): Use it.
546 (print_insn_arc): Use enforced_isa_mask.
547 (print_arc_disassembler_options): Document new options.
549 2017-05-24 Yao Qi <yao.qi@linaro.org>
551 * alpha-dis.c: Include disassemble.h, don't include
553 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
554 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
555 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
556 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
557 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
558 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
559 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
560 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
561 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
562 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
563 * moxie-dis.c, msp430-dis.c, mt-dis.c:
564 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
565 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
566 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
567 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
568 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
569 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
570 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
571 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
572 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
573 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
574 * z80-dis.c, z8k-dis.c: Likewise.
575 * disassemble.h: New file.
577 2017-05-24 Yao Qi <yao.qi@linaro.org>
579 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
580 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
582 2017-05-24 Yao Qi <yao.qi@linaro.org>
584 * disassemble.c (disassembler): Add arguments a, big and mach.
587 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
589 * i386-dis.c (NOTRACK_Fixup): New.
591 (NOTRACK_PREFIX): Likewise.
592 (last_active_prefix): Likewise.
593 (reg_table): Use NOTRACK on indirect call and jmp.
594 (ckprefix): Set last_active_prefix.
595 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
596 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
597 * i386-opc.h (NoTrackPrefixOk): New.
598 (i386_opcode_modifier): Add notrackprefixok.
599 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
601 * i386-tbl.h: Regenerated.
603 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
605 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
607 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
609 (print_insn_sparc): Handle new operand types.
610 * sparc-opc.c (MASK_M8): Define.
612 (v6notlet): Likewise.
623 (v9andleon): Likewise.
626 (HWS2_VM8): Likewise.
627 (sparc_opcode_archs): Add entry for "m8".
628 (sparc_opcodes): Add OSA2017 and M8 instructions
629 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
631 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
632 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
633 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
634 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
635 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
636 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
637 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
638 ASI_CORE_SELECT_COMMIT_NHT.
640 2017-05-18 Alan Modra <amodra@gmail.com>
642 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
643 * aarch64-dis.c: Likewise.
644 * aarch64-gen.c: Likewise.
645 * aarch64-opc.c: Likewise.
647 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
648 Matthew Fortune <matthew.fortune@imgtec.com>
650 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
651 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
652 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
653 (print_insn_arg) <OP_REG28>: Add handler.
654 (validate_insn_args) <OP_REG28>: Handle.
655 (print_mips16_insn_arg): Handle MIPS16 instructions that require
656 32-bit encoding and 9-bit immediates.
657 (print_insn_mips16): Handle MIPS16 instructions that require
658 32-bit encoding and MFC0/MTC0 operand decoding.
659 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
660 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
661 (RD_C0, WR_C0, E2, E2MT): New macros.
662 (mips16_opcodes): Add entries for MIPS16e2 instructions:
663 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
664 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
665 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
666 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
667 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
668 instructions, "swl", "swr", "sync" and its "sync_acquire",
669 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
670 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
671 regular/extended entries for original MIPS16 ISA revision
672 instructions whose extended forms are subdecoded in the MIPS16e2
673 ISA revision: "li", "sll" and "srl".
675 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
677 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
678 reference in CP0 move operand decoding.
680 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
682 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
684 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
686 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
688 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
689 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
690 "sync_rmb" and "sync_wmb" as aliases.
691 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
692 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
694 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
696 * arc-dis.c (parse_option): Update quarkse_em option..
697 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
699 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
701 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
703 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
705 2017-05-01 Michael Clark <michaeljclark@mac.com>
707 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
710 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
712 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
713 and branches and not synthetic data instructions.
715 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
717 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
719 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
721 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
722 * arc-opc.c (insert_r13el): New function.
724 * arc-tbl.h: Add new enter/leave variants.
726 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
728 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
730 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
732 * mips-dis.c (print_mips_disassembler_options): Add
735 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
737 * mips16-opc.c (AL): New macro.
738 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
739 of "ld" and "lw" as aliases.
741 2017-04-24 Tamar Christina <tamar.christina@arm.com>
743 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
746 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
747 Alan Modra <amodra@gmail.com>
749 * ppc-opc.c (ELEV): Define.
750 (vle_opcodes): Add se_rfgi and e_sc.
751 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
754 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
756 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
758 2017-04-21 Nick Clifton <nickc@redhat.com>
761 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
764 2017-04-13 Alan Modra <amodra@gmail.com>
766 * epiphany-desc.c: Regenerate.
767 * fr30-desc.c: Regenerate.
768 * frv-desc.c: Regenerate.
769 * ip2k-desc.c: Regenerate.
770 * iq2000-desc.c: Regenerate.
771 * lm32-desc.c: Regenerate.
772 * m32c-desc.c: Regenerate.
773 * m32r-desc.c: Regenerate.
774 * mep-desc.c: Regenerate.
775 * mt-desc.c: Regenerate.
776 * or1k-desc.c: Regenerate.
777 * xc16x-desc.c: Regenerate.
778 * xstormy16-desc.c: Regenerate.
780 2017-04-11 Alan Modra <amodra@gmail.com>
782 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
783 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
784 PPC_OPCODE_TMR for e6500.
785 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
786 (PPCVEC3): Define as PPC_OPCODE_POWER9.
787 (PPCVSX2): Define as PPC_OPCODE_POWER8.
788 (PPCVSX3): Define as PPC_OPCODE_POWER9.
789 (PPCHTM): Define as PPC_OPCODE_POWER8.
790 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
792 2017-04-10 Alan Modra <amodra@gmail.com>
794 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
795 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
796 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
797 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
799 2017-04-09 Pip Cet <pipcet@gmail.com>
801 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
802 appropriate floating-point precision directly.
804 2017-04-07 Alan Modra <amodra@gmail.com>
806 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
807 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
808 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
809 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
810 vector instructions with E6500 not PPCVEC2.
812 2017-04-06 Pip Cet <pipcet@gmail.com>
814 * Makefile.am: Add wasm32-dis.c.
815 * configure.ac: Add wasm32-dis.c to wasm32 target.
816 * disassemble.c: Add wasm32 disassembler code.
817 * wasm32-dis.c: New file.
818 * Makefile.in: Regenerate.
819 * configure: Regenerate.
820 * po/POTFILES.in: Regenerate.
821 * po/opcodes.pot: Regenerate.
823 2017-04-05 Pedro Alves <palves@redhat.com>
825 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
826 * arm-dis.c (parse_arm_disassembler_options): Constify.
827 * ppc-dis.c (powerpc_init_dialect): Constify local.
828 * vax-dis.c (parse_disassembler_options): Constify.
830 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
832 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
835 2017-03-30 Pip Cet <pipcet@gmail.com>
837 * configure.ac: Add (empty) bfd_wasm32_arch target.
838 * configure: Regenerate
839 * po/opcodes.pot: Regenerate.
841 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
843 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
845 * opcodes/sparc-opc.c (asi_table): New ASIs.
847 2017-03-29 Alan Modra <amodra@gmail.com>
849 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
851 (lookup_powerpc): Don't special case -1 dialect. Handle
853 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
854 lookup_powerpc call, pass it on second.
856 2017-03-27 Alan Modra <amodra@gmail.com>
859 * ppc-dis.c (struct ppc_mopt): Comment.
860 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
862 2017-03-27 Rinat Zelig <rinat@mellanox.com>
864 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
865 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
866 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
867 (insert_nps_misc_imm_offset): New function.
868 (extract_nps_misc imm_offset): New function.
869 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
870 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
872 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
874 * s390-mkopc.c (main): Remove vx2 check.
875 * s390-opc.txt: Remove vx2 instruction flags.
877 2017-03-21 Rinat Zelig <rinat@mellanox.com>
879 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
880 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
881 (insert_nps_imm_offset): New function.
882 (extract_nps_imm_offset): New function.
883 (insert_nps_imm_entry): New function.
884 (extract_nps_imm_entry): New function.
886 2017-03-17 Alan Modra <amodra@gmail.com>
889 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
890 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
891 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
893 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
895 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
899 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
901 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
903 2017-03-13 Andrew Waterman <andrew@sifive.com>
905 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
910 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
912 * i386-gen.c (opcode_modifiers): Replace S with Load.
913 * i386-opc.h (S): Removed.
915 (i386_opcode_modifier): Replace s with load.
916 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
917 and {evex}. Replace S with Load.
918 * i386-tbl.h: Regenerated.
920 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
922 * i386-opc.tbl: Use CpuCET on rdsspq.
923 * i386-tbl.h: Regenerated.
925 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
927 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
928 <vsx>: Do not use PPC_OPCODE_VSX3;
930 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
932 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
934 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
936 * i386-dis.c (REG_0F1E_MOD_3): New enum.
937 (MOD_0F1E_PREFIX_1): Likewise.
938 (MOD_0F38F5_PREFIX_2): Likewise.
939 (MOD_0F38F6_PREFIX_0): Likewise.
940 (RM_0F1E_MOD_3_REG_7): Likewise.
941 (PREFIX_MOD_0_0F01_REG_5): Likewise.
942 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
943 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
944 (PREFIX_0F1E): Likewise.
945 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
946 (PREFIX_0F38F5): Likewise.
947 (dis386_twobyte): Use PREFIX_0F1E.
948 (reg_table): Add REG_0F1E_MOD_3.
949 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
950 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
951 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
952 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
953 (three_byte_table): Use PREFIX_0F38F5.
954 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
955 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
956 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
957 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
958 PREFIX_MOD_3_0F01_REG_5_RM_2.
959 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
960 (cpu_flags): Add CpuCET.
961 * i386-opc.h (CpuCET): New enum.
962 (CpuUnused): Commented out.
963 (i386_cpu_flags): Add cpucet.
964 * i386-opc.tbl: Add Intel CET instructions.
965 * i386-init.h: Regenerated.
966 * i386-tbl.h: Likewise.
968 2017-03-06 Alan Modra <amodra@gmail.com>
971 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
972 (extract_raq, extract_ras, extract_rbx): New functions.
973 (powerpc_operands): Use opposite corresponding insert function.
975 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
976 register restriction.
978 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
980 * disassemble.c Include "safe-ctype.h".
981 (disassemble_init_for_target): Handle s390 init.
982 (remove_whitespace_and_extra_commas): New function.
983 (disassembler_options_cmp): Likewise.
984 * arm-dis.c: Include "libiberty.h".
986 (regnames): Use long disassembler style names.
987 Add force-thumb and no-force-thumb options.
988 (NUM_ARM_REGNAMES): Rename from this...
989 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
990 (get_arm_regname_num_options): Delete.
991 (set_arm_regname_option): Likewise.
992 (get_arm_regnames): Likewise.
993 (parse_disassembler_options): Likewise.
994 (parse_arm_disassembler_option): Rename from this...
995 (parse_arm_disassembler_options): ...to this. Make static.
996 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
997 (print_insn): Use parse_arm_disassembler_options.
998 (disassembler_options_arm): New function.
999 (print_arm_disassembler_options): Handle updated regnames.
1000 * ppc-dis.c: Include "libiberty.h".
1001 (ppc_opts): Add "32" and "64" entries.
1002 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1003 (powerpc_init_dialect): Add break to switch statement.
1004 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1005 (disassembler_options_powerpc): New function.
1006 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1007 Remove printing of "32" and "64".
1008 * s390-dis.c: Include "libiberty.h".
1009 (init_flag): Remove unneeded variable.
1010 (struct s390_options_t): New structure type.
1011 (options): New structure.
1012 (init_disasm): Rename from this...
1013 (disassemble_init_s390): ...to this. Add initializations for
1014 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1015 (print_insn_s390): Delete call to init_disasm.
1016 (disassembler_options_s390): New function.
1017 (print_s390_disassembler_options): Print using information from
1019 * po/opcodes.pot: Regenerate.
1021 2017-02-28 Jan Beulich <jbeulich@suse.com>
1023 * i386-dis.c (PCMPESTR_Fixup): New.
1024 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1025 (prefix_table): Use PCMPESTR_Fixup.
1026 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1028 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1029 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1030 Split 64-bit and non-64-bit variants.
1031 * opcodes/i386-tbl.h: Re-generate.
1033 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1035 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1036 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1037 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1038 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1039 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1040 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1041 (OP_SVE_V_HSD): New macros.
1042 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1043 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1044 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1045 (aarch64_opcode_table): Add new SVE instructions.
1046 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1047 for rotation operands. Add new SVE operands.
1048 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1049 (ins_sve_quad_index): Likewise.
1050 (ins_imm_rotate): Split into...
1051 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1052 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1053 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1055 (aarch64_ins_sve_addr_ri_s4): New function.
1056 (aarch64_ins_sve_quad_index): Likewise.
1057 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1058 * aarch64-asm-2.c: Regenerate.
1059 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1060 (ext_sve_quad_index): Likewise.
1061 (ext_imm_rotate): Split into...
1062 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1063 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1064 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1066 (aarch64_ext_sve_addr_ri_s4): New function.
1067 (aarch64_ext_sve_quad_index): Likewise.
1068 (aarch64_ext_sve_index): Allow quad indices.
1069 (do_misc_decoding): Likewise.
1070 * aarch64-dis-2.c: Regenerate.
1071 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1072 aarch64_field_kinds.
1073 (OPD_F_OD_MASK): Widen by one bit.
1074 (OPD_F_NO_ZR): Bump accordingly.
1075 (get_operand_field_width): New function.
1076 * aarch64-opc.c (fields): Add new SVE fields.
1077 (operand_general_constraint_met_p): Handle new SVE operands.
1078 (aarch64_print_operand): Likewise.
1079 * aarch64-opc-2.c: Regenerate.
1081 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1083 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1084 (aarch64_feature_compnum): ...this.
1085 (SIMD_V8_3): Replace with...
1087 (CNUM_INSN): New macro.
1088 (aarch64_opcode_table): Use it for the complex number instructions.
1090 2017-02-24 Jan Beulich <jbeulich@suse.com>
1092 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1094 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1096 Add support for associating SPARC ASIs with an architecture level.
1097 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1098 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1099 decoding of SPARC ASIs.
1101 2017-02-23 Jan Beulich <jbeulich@suse.com>
1103 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1104 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1106 2017-02-21 Jan Beulich <jbeulich@suse.com>
1108 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1109 1 (instead of to itself). Correct typo.
1111 2017-02-14 Andrew Waterman <andrew@sifive.com>
1113 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1116 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1118 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1119 (aarch64_sys_reg_supported_p): Handle them.
1121 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1123 * arc-opc.c (UIMM6_20R): Define.
1124 (SIMM12_20): Use above.
1125 (SIMM12_20R): Define.
1126 (SIMM3_5_S): Use above.
1127 (UIMM7_A32_11R_S): Define.
1128 (UIMM7_9_S): Use above.
1129 (UIMM3_13R_S): Define.
1130 (SIMM11_A32_7_S): Use above.
1132 (UIMM10_A32_8_S): Use above.
1133 (UIMM8_8R_S): Define.
1135 (arc_relax_opcodes): Use all above defines.
1137 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1139 * arc-regs.h: Distinguish some of the registers different on
1140 ARC700 and HS38 cpus.
1142 2017-02-14 Alan Modra <amodra@gmail.com>
1145 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1146 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1148 2017-02-11 Stafford Horne <shorne@gmail.com>
1149 Alan Modra <amodra@gmail.com>
1151 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1152 Use insn_bytes_value and insn_int_value directly instead. Don't
1153 free allocated memory until function exit.
1155 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1157 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1159 2017-02-03 Nick Clifton <nickc@redhat.com>
1162 * aarch64-opc.c (print_register_list): Ensure that the register
1163 list index will fir into the tb buffer.
1164 (print_register_offset_address): Likewise.
1165 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1167 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1170 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1171 instructions when the previous fetch packet ends with a 32-bit
1174 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1176 * pru-opc.c: Remove vague reference to a future GDB port.
1178 2017-01-20 Nick Clifton <nickc@redhat.com>
1180 * po/ga.po: Updated Irish translation.
1182 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1184 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1186 2017-01-13 Yao Qi <yao.qi@linaro.org>
1188 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1189 if FETCH_DATA returns 0.
1190 (m68k_scan_mask): Likewise.
1191 (print_insn_m68k): Update code to handle -1 return value.
1193 2017-01-13 Yao Qi <yao.qi@linaro.org>
1195 * m68k-dis.c (enum print_insn_arg_error): New.
1196 (NEXTBYTE): Replace -3 with
1197 PRINT_INSN_ARG_MEMORY_ERROR.
1198 (NEXTULONG): Likewise.
1199 (NEXTSINGLE): Likewise.
1200 (NEXTDOUBLE): Likewise.
1201 (NEXTDOUBLE): Likewise.
1202 (NEXTPACKED): Likewise.
1203 (FETCH_ARG): Likewise.
1204 (FETCH_DATA): Update comments.
1205 (print_insn_arg): Update comments. Replace magic numbers with
1207 (match_insn_m68k): Likewise.
1209 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1211 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1212 * i386-dis-evex.h (evex_table): Updated.
1213 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1214 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1215 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1216 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1217 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1218 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1219 * i386-init.h: Regenerate.
1220 * i386-tbl.h: Ditto.
1222 2017-01-12 Yao Qi <yao.qi@linaro.org>
1224 * msp430-dis.c (msp430_singleoperand): Return -1 if
1225 msp430dis_opcode_signed returns false.
1226 (msp430_doubleoperand): Likewise.
1227 (msp430_branchinstr): Return -1 if
1228 msp430dis_opcode_unsigned returns false.
1229 (msp430x_calla_instr): Likewise.
1230 (print_insn_msp430): Likewise.
1232 2017-01-05 Nick Clifton <nickc@redhat.com>
1235 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1236 could not be matched.
1237 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1240 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1242 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1243 (aarch64_opcode_table): Use RCPC_INSN.
1245 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1247 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1249 * riscv-opcodes/all-opcodes: Likewise.
1251 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1253 * riscv-dis.c (print_insn_args): Add fall through comment.
1255 2017-01-03 Nick Clifton <nickc@redhat.com>
1257 * po/sr.po: New Serbian translation.
1258 * configure.ac (ALL_LINGUAS): Add sr.
1259 * configure: Regenerate.
1261 2017-01-02 Alan Modra <amodra@gmail.com>
1263 * epiphany-desc.h: Regenerate.
1264 * epiphany-opc.h: Regenerate.
1265 * fr30-desc.h: Regenerate.
1266 * fr30-opc.h: Regenerate.
1267 * frv-desc.h: Regenerate.
1268 * frv-opc.h: Regenerate.
1269 * ip2k-desc.h: Regenerate.
1270 * ip2k-opc.h: Regenerate.
1271 * iq2000-desc.h: Regenerate.
1272 * iq2000-opc.h: Regenerate.
1273 * lm32-desc.h: Regenerate.
1274 * lm32-opc.h: Regenerate.
1275 * m32c-desc.h: Regenerate.
1276 * m32c-opc.h: Regenerate.
1277 * m32r-desc.h: Regenerate.
1278 * m32r-opc.h: Regenerate.
1279 * mep-desc.h: Regenerate.
1280 * mep-opc.h: Regenerate.
1281 * mt-desc.h: Regenerate.
1282 * mt-opc.h: Regenerate.
1283 * or1k-desc.h: Regenerate.
1284 * or1k-opc.h: Regenerate.
1285 * xc16x-desc.h: Regenerate.
1286 * xc16x-opc.h: Regenerate.
1287 * xstormy16-desc.h: Regenerate.
1288 * xstormy16-opc.h: Regenerate.
1290 2017-01-02 Alan Modra <amodra@gmail.com>
1292 Update year range in copyright notice of all files.
1294 For older changes see ChangeLog-2016
1296 Copyright (C) 2017 Free Software Foundation, Inc.
1298 Copying and distribution of this file, with or without modification,
1299 are permitted in any medium without royalty provided the copyright
1300 notice and this notice are preserved.
1306 version-control: never