opcodes/ChangeLog

   1 2017-07-11  Yao Qi  <yao.qi@linaro.org>
   2             Alan Modra  <amodra@gmail.com>
   3
   4         * cgen.sh: Mark generated files read-only.
   5         * epiphany-asm.c: Regenerate.
   6         * epiphany-desc.c: Regenerate.
   7         * epiphany-desc.h: Regenerate.
   8         * epiphany-dis.c: Regenerate.
   9         * epiphany-ibld.c: Regenerate.
  10         * epiphany-opc.c: Regenerate.
  11         * epiphany-opc.h: Regenerate.
  12         * fr30-asm.c: Regenerate.
  13         * fr30-desc.c: Regenerate.
  14         * fr30-desc.h: Regenerate.
  15         * fr30-dis.c: Regenerate.
  16         * fr30-ibld.c: Regenerate.
  17         * fr30-opc.c: Regenerate.
  18         * fr30-opc.h: Regenerate.
  19         * frv-asm.c: Regenerate.
  20         * frv-desc.c: Regenerate.
  21         * frv-desc.h: Regenerate.
  22         * frv-dis.c: Regenerate.
  23         * frv-ibld.c: Regenerate.
  24         * frv-opc.c: Regenerate.
  25         * frv-opc.h: Regenerate.
  26         * ip2k-asm.c: Regenerate.
  27         * ip2k-desc.c: Regenerate.
  28         * ip2k-desc.h: Regenerate.
  29         * ip2k-dis.c: Regenerate.
  30         * ip2k-ibld.c: Regenerate.
  31         * ip2k-opc.c: Regenerate.
  32         * ip2k-opc.h: Regenerate.
  33         * iq2000-asm.c: Regenerate.
  34         * iq2000-desc.c: Regenerate.
  35         * iq2000-desc.h: Regenerate.
  36         * iq2000-dis.c: Regenerate.
  37         * iq2000-ibld.c: Regenerate.
  38         * iq2000-opc.c: Regenerate.
  39         * iq2000-opc.h: Regenerate.
  40         * lm32-asm.c: Regenerate.
  41         * lm32-desc.c: Regenerate.
  42         * lm32-desc.h: Regenerate.
  43         * lm32-dis.c: Regenerate.
  44         * lm32-ibld.c: Regenerate.
  45         * lm32-opc.c: Regenerate.
  46         * lm32-opc.h: Regenerate.
  47         * lm32-opinst.c: Regenerate.
  48         * m32c-asm.c: Regenerate.
  49         * m32c-desc.c: Regenerate.
  50         * m32c-desc.h: Regenerate.
  51         * m32c-dis.c: Regenerate.
  52         * m32c-ibld.c: Regenerate.
  53         * m32c-opc.c: Regenerate.
  54         * m32c-opc.h: Regenerate.
  55         * m32r-asm.c: Regenerate.
  56         * m32r-desc.c: Regenerate.
  57         * m32r-desc.h: Regenerate.
  58         * m32r-dis.c: Regenerate.
  59         * m32r-ibld.c: Regenerate.
  60         * m32r-opc.c: Regenerate.
  61         * m32r-opc.h: Regenerate.
  62         * m32r-opinst.c: Regenerate.
  63         * mep-asm.c: Regenerate.
  64         * mep-desc.c: Regenerate.
  65         * mep-desc.h: Regenerate.
  66         * mep-dis.c: Regenerate.
  67         * mep-ibld.c: Regenerate.
  68         * mep-opc.c: Regenerate.
  69         * mep-opc.h: Regenerate.
  70         * mt-asm.c: Regenerate.
  71         * mt-desc.c: Regenerate.
  72         * mt-desc.h: Regenerate.
  73         * mt-dis.c: Regenerate.
  74         * mt-ibld.c: Regenerate.
  75         * mt-opc.c: Regenerate.
  76         * mt-opc.h: Regenerate.
  77         * or1k-asm.c: Regenerate.
  78         * or1k-desc.c: Regenerate.
  79         * or1k-desc.h: Regenerate.
  80         * or1k-dis.c: Regenerate.
  81         * or1k-ibld.c: Regenerate.
  82         * or1k-opc.c: Regenerate.
  83         * or1k-opc.h: Regenerate.
  84         * or1k-opinst.c: Regenerate.
  85         * xc16x-asm.c: Regenerate.
  86         * xc16x-desc.c: Regenerate.
  87         * xc16x-desc.h: Regenerate.
  88         * xc16x-dis.c: Regenerate.
  89         * xc16x-ibld.c: Regenerate.
  90         * xc16x-opc.c: Regenerate.
  91         * xc16x-opc.h: Regenerate.
  92         * xstormy16-asm.c: Regenerate.
  93         * xstormy16-desc.c: Regenerate.
  94         * xstormy16-desc.h: Regenerate.
  95         * xstormy16-dis.c: Regenerate.
  96         * xstormy16-ibld.c: Regenerate.
  97         * xstormy16-opc.c: Regenerate.
  98         * xstormy16-opc.h: Regenerate.
  99
 100 2017-07-07  Alan Modra  <amodra@gmail.com>
 101
 102         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 103         * m32c-dis.c: Regenerate.
 104         * mep-dis.c: Regenerate.
 105
 106 2017-07-05  Borislav Petkov  <bp@suse.de>
 107
 108         * i386-dis.c: Enable ModRM.reg /6 aliases.
 109
 110 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 111
 112         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 113         with vmrs and vmsr.
 114
 115 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 116
 117         * configure: Regenerate.
 118
 119 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 120
 121         * po/opcodes.pot: Regenerate.
 122
 123 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 124
 125         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 126         entries to the MSA ASE instruction block.
 127
 128 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 129             Maciej W. Rozycki  <macro@imgtec.com>
 130
 131         * micromips-opc.c (XPA, XPAVZ): New macros.
 132         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 133         "mthgc0".
 134
 135 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 136             Maciej W. Rozycki  <macro@imgtec.com>
 137
 138         * micromips-opc.c (I36): New macro.
 139         (micromips_opcodes): Add "eretnc".
 140
 141 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 142             Andrew Bennett  <andrew.bennett@imgtec.com>
 143
 144         * mips-dis.c (mips_calculate_combination_ases): Handle the
 145         ASE_XPA_VIRT flag.
 146         (parse_mips_ase_option): New function.
 147         (parse_mips_dis_option): Factor out ASE option handling to the
 148         new function.  Call `mips_calculate_combination_ases'.
 149         * mips-opc.c (XPAVZ): New macro.
 150         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 151         "mfhgc0", "mthc0" and "mthgc0".
 152
 153 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 154
 155         * mips-dis.c (mips_calculate_combination_ases): New function.
 156         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 157         calculation to the new function.
 158         (set_default_mips_dis_options): Call the new function.
 159
 160 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 161
 162         * arc-dis.c (parse_disassembler_options): Use
 163         FOR_EACH_DISASSEMBLER_OPTION.
 164
 165 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 166
 167         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 168         disassembler option strings.
 169         (parse_cpu_option): Likewise.
 170
 171 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 172
 173         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 174         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 175         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 176         (aarch64_feature_dotprod, DOT_INSN): New.
 177         (udot, sdot): New.
 178         * aarch64-dis-2.c: Regenerated.
 179
 180 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 181
 182         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 183
 184 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 185             Matthew Fortune  <matthew.fortune@imgtec.com>
 186             Andrew Bennett  <andrew.bennett@imgtec.com>
 187
 188         * mips-formats.h (INT_BIAS): New macro.
 189         (INT_ADJ): Redefine in INT_BIAS terms.
 190         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 191         (mips_print_save_restore): New function.
 192         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 193         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 194         call.
 195         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 196         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 197         OP_SAVE_RESTORE_LIST handling, factored out from here.
 198         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 199         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 200         (mips_builtin_opcodes): Add "restore" and "save" entries.
 201         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 202         (IAMR2): New macro.
 203         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 204
 205 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 206
 207         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 208         alias; do not mark SLTI instruction as an alias.
 209
 210 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * i386-dis.c (RM_0FAE_REG_5): Removed.
 213         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 214         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 215         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 216         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 217         PREFIX_MOD_3_0F01_REG_5_RM_0.
 218         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 219         PREFIX_MOD_3_0FAE_REG_5.
 220         (mod_table): Update MOD_0FAE_REG_5.
 221         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 222         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 223         * i386-tbl.h: Regenerated.
 224
 225 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 226
 227         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 228         * i386-opc.tbl: Likewise.
 229         * i386-tbl.h: Regenerated.
 230
 231 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 232
 233         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 234         and "jmp{&|}".
 235         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 236         prefix.
 237
 238 2017-06-19  Nick Clifton  <nickc@redhat.com>
 239
 240         PR binutils/21614
 241         * score-dis.c (score_opcodes): Add sentinel.
 242
 243 2017-06-16  Alan Modra  <amodra@gmail.com>
 244
 245         * rx-decode.c: Regenerate.
 246
 247 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 248
 249         PR binutils/21594
 250         * i386-dis.c (OP_E_register): Check valid bnd register.
 251         (OP_G): Likewise.
 252
 253 2017-06-15  Nick Clifton  <nickc@redhat.com>
 254
 255         PR binutils/21595
 256         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 257         range value.
 258
 259 2017-06-15  Nick Clifton  <nickc@redhat.com>
 260
 261         PR binutils/21588
 262         * rl78-decode.opc (OP_BUF_LEN): Define.
 263         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 264         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 265         array.
 266         * rl78-decode.c: Regenerate.
 267
 268 2017-06-15  Nick Clifton  <nickc@redhat.com>
 269
 270         PR binutils/21586
 271         * bfin-dis.c (gregs): Clip index to prevent overflow.
 272         (regs): Likewise.
 273         (regs_lo): Likewise.
 274         (regs_hi): Likewise.
 275
 276 2017-06-14  Nick Clifton  <nickc@redhat.com>
 277
 278         PR binutils/21576
 279         * score7-dis.c (score_opcodes): Add sentinel.
 280
 281 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 282
 283         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 284         * arm-dis.c: Likewise.
 285         * ia64-dis.c: Likewise.
 286         * mips-dis.c: Likewise.
 287         * spu-dis.c: Likewise.
 288         * disassemble.h (print_insn_aarch64): New declaration, moved from
 289         include/dis-asm.h.
 290         (print_insn_big_arm, print_insn_big_mips): Likewise.
 291         (print_insn_i386, print_insn_ia64): Likewise.
 292         (print_insn_little_arm, print_insn_little_mips): Likewise.
 293
 294 2017-06-14  Nick Clifton  <nickc@redhat.com>
 295
 296         PR binutils/21587
 297         * rx-decode.opc: Include libiberty.h
 298         (GET_SCALE): New macro - validates access to SCALE array.
 299         (GET_PSCALE): New macro - validates access to PSCALE array.
 300         (DIs, SIs, S2Is, rx_disp): Use new macros.
 301         * rx-decode.c: Regenerate.
 302
 303 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 304
 305         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 306
 307 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 308
 309         * arc-dis.c (enforced_isa_mask): Declare.
 310         (cpu_types): Likewise.
 311         (parse_cpu_option): New function.
 312         (parse_disassembler_options): Use it.
 313         (print_insn_arc): Use enforced_isa_mask.
 314         (print_arc_disassembler_options): Document new options.
 315
 316 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 317
 318         * alpha-dis.c: Include disassemble.h, don't include
 319         dis-asm.h.
 320         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 321         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 322         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 323         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 324         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 325         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 326         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 327         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 328         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 329         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 330         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 331         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 332         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 333         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 334         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 335         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 336         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 337         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 338         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 339         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 340         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 341         * z80-dis.c, z8k-dis.c: Likewise.
 342         * disassemble.h: New file.
 343
 344 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 345
 346         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 347         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 348
 349 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 350
 351         * disassemble.c (disassembler): Add arguments a, big and mach.
 352         Use them.
 353
 354 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 355
 356         * i386-dis.c (NOTRACK_Fixup): New.
 357         (NOTRACK): Likewise.
 358         (NOTRACK_PREFIX): Likewise.
 359         (last_active_prefix): Likewise.
 360         (reg_table): Use NOTRACK on indirect call and jmp.
 361         (ckprefix): Set last_active_prefix.
 362         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 363         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 364         * i386-opc.h (NoTrackPrefixOk): New.
 365         (i386_opcode_modifier): Add notrackprefixok.
 366         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 367         Add notrack.
 368         * i386-tbl.h: Regenerated.
 369
 370 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 371
 372         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 373         (X_IMM2): Define.
 374         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 375         bfd_mach_sparc_v9m8.
 376         (print_insn_sparc): Handle new operand types.
 377         * sparc-opc.c (MASK_M8): Define.
 378         (v6): Add MASK_M8.
 379         (v6notlet): Likewise.
 380         (v7): Likewise.
 381         (v8): Likewise.
 382         (v9): Likewise.
 383         (v9a): Likewise.
 384         (v9b): Likewise.
 385         (v9c): Likewise.
 386         (v9d): Likewise.
 387         (v9e): Likewise.
 388         (v9v): Likewise.
 389         (v9m): Likewise.
 390         (v9andleon): Likewise.
 391         (m8): Define.
 392         (HWS_VM8): Define.
 393         (HWS2_VM8): Likewise.
 394         (sparc_opcode_archs): Add entry for "m8".
 395         (sparc_opcodes): Add OSA2017 and M8 instructions
 396         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 397         fpx{ll,ra,rl}64x,
 398         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 399         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 400         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 401         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 402         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 403         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 404         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 405         ASI_CORE_SELECT_COMMIT_NHT.
 406
 407 2017-05-18  Alan Modra  <amodra@gmail.com>
 408
 409         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 410         * aarch64-dis.c: Likewise.
 411         * aarch64-gen.c: Likewise.
 412         * aarch64-opc.c: Likewise.
 413
 414 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 415             Matthew Fortune  <matthew.fortune@imgtec.com>
 416
 417         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 418         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 419         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 420         (print_insn_arg) <OP_REG28>: Add handler.
 421         (validate_insn_args) <OP_REG28>: Handle.
 422         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 423         32-bit encoding and 9-bit immediates.
 424         (print_insn_mips16): Handle MIPS16 instructions that require
 425         32-bit encoding and MFC0/MTC0 operand decoding.
 426         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 427         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 428         (RD_C0, WR_C0, E2, E2MT): New macros.
 429         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 430         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 431         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 432         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 433         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 434         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 435         instructions, "swl", "swr", "sync" and its "sync_acquire",
 436         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 437         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 438         regular/extended entries for original MIPS16 ISA revision
 439         instructions whose extended forms are subdecoded in the MIPS16e2
 440         ISA revision: "li", "sll" and "srl".
 441
 442 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 443
 444         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 445         reference in CP0 move operand decoding.
 446
 447 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 448
 449         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 450         type to hexadecimal.
 451         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 452
 453 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 454
 455         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 456         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 457         "sync_rmb" and "sync_wmb" as aliases.
 458         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 459         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 460
 461 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 462
 463         * arc-dis.c (parse_option): Update quarkse_em option..
 464         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 465         QUARKSE1.
 466         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 467
 468 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 469
 470         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 471
 472 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 473
 474         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 475         register.
 476
 477 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 478
 479         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 480         and branches and not synthetic data instructions.
 481
 482 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 483
 484         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 485
 486 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 487
 488         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 489         * arc-opc.c (insert_r13el): New function.
 490         (R13_EL): Define.
 491         * arc-tbl.h: Add new enter/leave variants.
 492
 493 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 494
 495         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 496
 497 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 498
 499         * mips-dis.c (print_mips_disassembler_options): Add
 500         `no-aliases'.
 501
 502 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 503
 504         * mips16-opc.c (AL): New macro.
 505         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 506         of "ld" and "lw" as aliases.
 507
 508 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 509
 510         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 511         arguments.
 512
 513 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 514             Alan Modra  <amodra@gmail.com>
 515
 516         * ppc-opc.c (ELEV): Define.
 517         (vle_opcodes): Add se_rfgi and e_sc.
 518         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 519         for E200Z4.
 520
 521 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 522
 523         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 524
 525 2017-04-21  Nick Clifton  <nickc@redhat.com>
 526
 527         PR binutils/21380
 528         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 529         LD3R and LD4R.
 530
 531 2017-04-13  Alan Modra  <amodra@gmail.com>
 532
 533         * epiphany-desc.c: Regenerate.
 534         * fr30-desc.c: Regenerate.
 535         * frv-desc.c: Regenerate.
 536         * ip2k-desc.c: Regenerate.
 537         * iq2000-desc.c: Regenerate.
 538         * lm32-desc.c: Regenerate.
 539         * m32c-desc.c: Regenerate.
 540         * m32r-desc.c: Regenerate.
 541         * mep-desc.c: Regenerate.
 542         * mt-desc.c: Regenerate.
 543         * or1k-desc.c: Regenerate.
 544         * xc16x-desc.c: Regenerate.
 545         * xstormy16-desc.c: Regenerate.
 546
 547 2017-04-11  Alan Modra  <amodra@gmail.com>
 548
 549         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 550         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 551         PPC_OPCODE_TMR for e6500.
 552         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 553         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 554         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 555         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 556         (PPCHTM): Define as PPC_OPCODE_POWER8.
 557         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 558
 559 2017-04-10  Alan Modra  <amodra@gmail.com>
 560
 561         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 562         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 563         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 564         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 565
 566 2017-04-09  Pip Cet  <pipcet@gmail.com>
 567
 568         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 569         appropriate floating-point precision directly.
 570
 571 2017-04-07  Alan Modra  <amodra@gmail.com>
 572
 573         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 574         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 575         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 576         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 577         vector instructions with E6500 not PPCVEC2.
 578
 579 2017-04-06  Pip Cet  <pipcet@gmail.com>
 580
 581         * Makefile.am: Add wasm32-dis.c.
 582         * configure.ac: Add wasm32-dis.c to wasm32 target.
 583         * disassemble.c: Add wasm32 disassembler code.
 584         * wasm32-dis.c: New file.
 585         * Makefile.in: Regenerate.
 586         * configure: Regenerate.
 587         * po/POTFILES.in: Regenerate.
 588         * po/opcodes.pot: Regenerate.
 589
 590 2017-04-05  Pedro Alves  <palves@redhat.com>
 591
 592         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 593         * arm-dis.c (parse_arm_disassembler_options): Constify.
 594         * ppc-dis.c (powerpc_init_dialect): Constify local.
 595         * vax-dis.c (parse_disassembler_options): Constify.
 596
 597 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 598
 599         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 600         RISCV_GP_SYMBOL.
 601
 602 2017-03-30  Pip Cet  <pipcet@gmail.com>
 603
 604         * configure.ac: Add (empty) bfd_wasm32_arch target.
 605         * configure: Regenerate
 606         * po/opcodes.pot: Regenerate.
 607
 608 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 609
 610         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 611         OSA2015.
 612         * opcodes/sparc-opc.c (asi_table): New ASIs.
 613
 614 2017-03-29  Alan Modra  <amodra@gmail.com>
 615
 616         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 617         "raw" option.
 618         (lookup_powerpc): Don't special case -1 dialect.  Handle
 619         PPC_OPCODE_RAW.
 620         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 621         lookup_powerpc call, pass it on second.
 622
 623 2017-03-27  Alan Modra  <amodra@gmail.com>
 624
 625         PR 21303
 626         * ppc-dis.c (struct ppc_mopt): Comment.
 627         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 628
 629 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 630
 631         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 632         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 633         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 634         (insert_nps_misc_imm_offset): New function.
 635         (extract_nps_misc imm_offset): New function.
 636         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 637         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 638
 639 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 640
 641         * s390-mkopc.c (main): Remove vx2 check.
 642         * s390-opc.txt: Remove vx2 instruction flags.
 643
 644 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 645
 646         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 647         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 648         (insert_nps_imm_offset): New function.
 649         (extract_nps_imm_offset): New function.
 650         (insert_nps_imm_entry): New function.
 651         (extract_nps_imm_entry): New function.
 652
 653 2017-03-17  Alan Modra  <amodra@gmail.com>
 654
 655         PR 21248
 656         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 657         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 658         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 659
 660 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 661
 662         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 663         <c.andi>: Likewise.
 664         <c.addiw> Likewise.
 665
 666 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 667
 668         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 669
 670 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 671
 672         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 673         <srl> Likewise.
 674         <srai> Likewise.
 675         <sra> Likewise.
 676
 677 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 678
 679         * i386-gen.c (opcode_modifiers): Replace S with Load.
 680         * i386-opc.h (S): Removed.
 681         (Load): New.
 682         (i386_opcode_modifier): Replace s with load.
 683         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 684         and {evex}.  Replace S with Load.
 685         * i386-tbl.h: Regenerated.
 686
 687 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 688
 689         * i386-opc.tbl: Use CpuCET on rdsspq.
 690         * i386-tbl.h: Regenerated.
 691
 692 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 693
 694         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 695         <vsx>: Do not use PPC_OPCODE_VSX3;
 696
 697 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 698
 699         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 700
 701 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 704         (MOD_0F1E_PREFIX_1): Likewise.
 705         (MOD_0F38F5_PREFIX_2): Likewise.
 706         (MOD_0F38F6_PREFIX_0): Likewise.
 707         (RM_0F1E_MOD_3_REG_7): Likewise.
 708         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 709         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 710         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 711         (PREFIX_0F1E): Likewise.
 712         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 713         (PREFIX_0F38F5): Likewise.
 714         (dis386_twobyte): Use PREFIX_0F1E.
 715         (reg_table): Add REG_0F1E_MOD_3.
 716         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 717         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 718         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 719         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 720         (three_byte_table): Use PREFIX_0F38F5.
 721         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 722         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 723         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 724         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 725         PREFIX_MOD_3_0F01_REG_5_RM_2.
 726         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 727         (cpu_flags): Add CpuCET.
 728         * i386-opc.h (CpuCET): New enum.
 729         (CpuUnused): Commented out.
 730         (i386_cpu_flags): Add cpucet.
 731         * i386-opc.tbl: Add Intel CET instructions.
 732         * i386-init.h: Regenerated.
 733         * i386-tbl.h: Likewise.
 734
 735 2017-03-06  Alan Modra  <amodra@gmail.com>
 736
 737         PR 21124
 738         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 739         (extract_raq, extract_ras, extract_rbx): New functions.
 740         (powerpc_operands): Use opposite corresponding insert function.
 741         (Q_MASK): Define.
 742         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 743         register restriction.
 744
 745 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 746
 747         * disassemble.c Include "safe-ctype.h".
 748         (disassemble_init_for_target): Handle s390 init.
 749         (remove_whitespace_and_extra_commas): New function.
 750         (disassembler_options_cmp): Likewise.
 751         * arm-dis.c: Include "libiberty.h".
 752         (NUM_ELEM): Delete.
 753         (regnames): Use long disassembler style names.
 754         Add force-thumb and no-force-thumb options.
 755         (NUM_ARM_REGNAMES): Rename from this...
 756         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 757         (get_arm_regname_num_options): Delete.
 758         (set_arm_regname_option): Likewise.
 759         (get_arm_regnames): Likewise.
 760         (parse_disassembler_options): Likewise.
 761         (parse_arm_disassembler_option): Rename from this...
 762         (parse_arm_disassembler_options): ...to this.  Make static.
 763         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 764         (print_insn): Use parse_arm_disassembler_options.
 765         (disassembler_options_arm): New function.
 766         (print_arm_disassembler_options): Handle updated regnames.
 767         * ppc-dis.c: Include "libiberty.h".
 768         (ppc_opts): Add "32" and "64" entries.
 769         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 770         (powerpc_init_dialect): Add break to switch statement.
 771         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 772         (disassembler_options_powerpc): New function.
 773         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 774         Remove printing of "32" and "64".
 775         * s390-dis.c: Include "libiberty.h".
 776         (init_flag): Remove unneeded variable.
 777         (struct s390_options_t): New structure type.
 778         (options): New structure.
 779         (init_disasm): Rename from this...
 780         (disassemble_init_s390): ...to this.  Add initializations for
 781         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 782         (print_insn_s390): Delete call to init_disasm.
 783         (disassembler_options_s390): New function.
 784         (print_s390_disassembler_options): Print using information from
 785         struct 'options'.
 786         * po/opcodes.pot: Regenerate.
 787
 788 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 789
 790         * i386-dis.c (PCMPESTR_Fixup): New.
 791         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 792         (prefix_table): Use PCMPESTR_Fixup.
 793         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 794         PCMPESTR_Fixup.
 795         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 796         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 797         Split 64-bit and non-64-bit variants.
 798         * opcodes/i386-tbl.h: Re-generate.
 799
 800 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 801
 802         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 803         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 804         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 805         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 806         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 807         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 808         (OP_SVE_V_HSD): New macros.
 809         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 810         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 811         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 812         (aarch64_opcode_table): Add new SVE instructions.
 813         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 814         for rotation operands.  Add new SVE operands.
 815         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 816         (ins_sve_quad_index): Likewise.
 817         (ins_imm_rotate): Split into...
 818         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 819         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 820         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 821         functions.
 822         (aarch64_ins_sve_addr_ri_s4): New function.
 823         (aarch64_ins_sve_quad_index): Likewise.
 824         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 825         * aarch64-asm-2.c: Regenerate.
 826         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 827         (ext_sve_quad_index): Likewise.
 828         (ext_imm_rotate): Split into...
 829         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 830         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 831         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 832         functions.
 833         (aarch64_ext_sve_addr_ri_s4): New function.
 834         (aarch64_ext_sve_quad_index): Likewise.
 835         (aarch64_ext_sve_index): Allow quad indices.
 836         (do_misc_decoding): Likewise.
 837         * aarch64-dis-2.c: Regenerate.
 838         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 839         aarch64_field_kinds.
 840         (OPD_F_OD_MASK): Widen by one bit.
 841         (OPD_F_NO_ZR): Bump accordingly.
 842         (get_operand_field_width): New function.
 843         * aarch64-opc.c (fields): Add new SVE fields.
 844         (operand_general_constraint_met_p): Handle new SVE operands.
 845         (aarch64_print_operand): Likewise.
 846         * aarch64-opc-2.c: Regenerate.
 847
 848 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 849
 850         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 851         (aarch64_feature_compnum): ...this.
 852         (SIMD_V8_3): Replace with...
 853         (COMPNUM): ...this.
 854         (CNUM_INSN): New macro.
 855         (aarch64_opcode_table): Use it for the complex number instructions.
 856
 857 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 858
 859         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 860
 861 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 862
 863         Add support for associating SPARC ASIs with an architecture level.
 864         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 865         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 866         decoding of SPARC ASIs.
 867
 868 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 871         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 872
 873 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 874
 875         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 876         1 (instead of to itself). Correct typo.
 877
 878 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 879
 880         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 881         pseudoinstructions.
 882
 883 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 884
 885         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 886         (aarch64_sys_reg_supported_p): Handle them.
 887
 888 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 889
 890         * arc-opc.c (UIMM6_20R): Define.
 891         (SIMM12_20): Use above.
 892         (SIMM12_20R): Define.
 893         (SIMM3_5_S): Use above.
 894         (UIMM7_A32_11R_S): Define.
 895         (UIMM7_9_S): Use above.
 896         (UIMM3_13R_S): Define.
 897         (SIMM11_A32_7_S): Use above.
 898         (SIMM9_8R): Define.
 899         (UIMM10_A32_8_S): Use above.
 900         (UIMM8_8R_S): Define.
 901         (W6): Use above.
 902         (arc_relax_opcodes): Use all above defines.
 903
 904 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 905
 906         * arc-regs.h: Distinguish some of the registers different on
 907         ARC700 and HS38 cpus.
 908
 909 2017-02-14  Alan Modra  <amodra@gmail.com>
 910
 911         PR 21118
 912         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 913         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 914
 915 2017-02-11  Stafford Horne  <shorne@gmail.com>
 916             Alan Modra  <amodra@gmail.com>
 917
 918         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 919         Use insn_bytes_value and insn_int_value directly instead.  Don't
 920         free allocated memory until function exit.
 921
 922 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 923
 924         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 925
 926 2017-02-03  Nick Clifton  <nickc@redhat.com>
 927
 928         PR 21096
 929         * aarch64-opc.c (print_register_list): Ensure that the register
 930         list index will fir into the tb buffer.
 931         (print_register_offset_address): Likewise.
 932         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 933
 934 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 935
 936         PR 21056
 937         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 938         instructions when the previous fetch packet ends with a 32-bit
 939         instruction.
 940
 941 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 942
 943         * pru-opc.c: Remove vague reference to a future GDB port.
 944
 945 2017-01-20  Nick Clifton  <nickc@redhat.com>
 946
 947         * po/ga.po: Updated Irish translation.
 948
 949 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 950
 951         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 952
 953 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 954
 955         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 956         if FETCH_DATA returns 0.
 957         (m68k_scan_mask): Likewise.
 958         (print_insn_m68k): Update code to handle -1 return value.
 959
 960 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 961
 962         * m68k-dis.c (enum print_insn_arg_error): New.
 963         (NEXTBYTE): Replace -3 with
 964         PRINT_INSN_ARG_MEMORY_ERROR.
 965         (NEXTULONG): Likewise.
 966         (NEXTSINGLE): Likewise.
 967         (NEXTDOUBLE): Likewise.
 968         (NEXTDOUBLE): Likewise.
 969         (NEXTPACKED): Likewise.
 970         (FETCH_ARG): Likewise.
 971         (FETCH_DATA): Update comments.
 972         (print_insn_arg): Update comments. Replace magic numbers with
 973         enum.
 974         (match_insn_m68k): Likewise.
 975
 976 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 977
 978         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 979         * i386-dis-evex.h (evex_table): Updated.
 980         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 981         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 982         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 983         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 984         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 985         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 986         * i386-init.h: Regenerate.
 987         * i386-tbl.h: Ditto.
 988
 989 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 990
 991         * msp430-dis.c (msp430_singleoperand): Return -1 if
 992         msp430dis_opcode_signed returns false.
 993         (msp430_doubleoperand): Likewise.
 994         (msp430_branchinstr): Return -1 if
 995         msp430dis_opcode_unsigned returns false.
 996         (msp430x_calla_instr): Likewise.
 997         (print_insn_msp430): Likewise.
 998
 999 2017-01-05  Nick Clifton  <nickc@redhat.com>
1000
1001         PR 20946
1002         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1003         could not be matched.
1004         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1005         NULL.
1006
1007 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1008
1009         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1010         (aarch64_opcode_table): Use RCPC_INSN.
1011
1012 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1013
1014         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1015         extension.
1016         * riscv-opcodes/all-opcodes: Likewise.
1017
1018 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1019
1020         * riscv-dis.c (print_insn_args): Add fall through comment.
1021
1022 2017-01-03  Nick Clifton  <nickc@redhat.com>
1023
1024         * po/sr.po: New Serbian translation.
1025         * configure.ac (ALL_LINGUAS): Add sr.
1026         * configure: Regenerate.
1027
1028 2017-01-02  Alan Modra  <amodra@gmail.com>
1029
1030         * epiphany-desc.h: Regenerate.
1031         * epiphany-opc.h: Regenerate.
1032         * fr30-desc.h: Regenerate.
1033         * fr30-opc.h: Regenerate.
1034         * frv-desc.h: Regenerate.
1035         * frv-opc.h: Regenerate.
1036         * ip2k-desc.h: Regenerate.
1037         * ip2k-opc.h: Regenerate.
1038         * iq2000-desc.h: Regenerate.
1039         * iq2000-opc.h: Regenerate.
1040         * lm32-desc.h: Regenerate.
1041         * lm32-opc.h: Regenerate.
1042         * m32c-desc.h: Regenerate.
1043         * m32c-opc.h: Regenerate.
1044         * m32r-desc.h: Regenerate.
1045         * m32r-opc.h: Regenerate.
1046         * mep-desc.h: Regenerate.
1047         * mep-opc.h: Regenerate.
1048         * mt-desc.h: Regenerate.
1049         * mt-opc.h: Regenerate.
1050         * or1k-desc.h: Regenerate.
1051         * or1k-opc.h: Regenerate.
1052         * xc16x-desc.h: Regenerate.
1053         * xc16x-opc.h: Regenerate.
1054         * xstormy16-desc.h: Regenerate.
1055         * xstormy16-opc.h: Regenerate.
1056
1057 2017-01-02  Alan Modra  <amodra@gmail.com>
1058
1059         Update year range in copyright notice of all files.
1060
1061 For older changes see ChangeLog-2016
1062 \f
1063 Copyright (C) 2017 Free Software Foundation, Inc.
1064
1065 Copying and distribution of this file, with or without modification,
1066 are permitted in any medium without royalty provided the copyright
1067 notice and this notice are preserved.
1068
1069 Local Variables:
1070 mode: change-log
1071 left-margin: 8
1072 fill-column: 74
1073 version-control: never
1074 End: