opcodes/ChangeLog

   1 2005-01-31  Jan Beulich  <jbeulich@novell.com>
   2
   3         * ia64-gen.c (NELEMS): Define.
   4         (shrink): Generate alias with missing second predicate register when
   5         opcode has two outputs and these are both predicates.
   6         * ia64-opc-i.c (FULL17): Define.
   7         (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
   8         here to generate output template.
   9         (TBITCM, TNATCM): Undefine after use.
  10         * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
  11         first input. Add ld16 aliases without ar.csd as second output. Add
  12         st16 aliases without ar.csd as second input. Add cmpxchg aliases
  13         without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
  14         ar.ccv as third/fourth inputs. Consolidate through...
  15         (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
  16         CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
  17         * ia64-asmtab.c: Regenerate.
  18
  19 2005-01-27  Andrew Cagney  <cagney@gnu.org>
  20
  21         * configure: Regenerate to track ../gettext.m4 change.
  22
  23 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  24
  25         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  26         * frv-asm.c: Rebuilt.
  27         * frv-desc.c: Rebuilt.
  28         * frv-desc.h: Rebuilt.
  29         * frv-dis.c: Rebuilt.
  30         * frv-ibld.c: Rebuilt.
  31         * frv-opc.c: Rebuilt.
  32         * frv-opc.h: Rebuilt.
  33
  34 2005-01-24  Andrew Cagney  <cagney@gnu.org>
  35
  36         * configure: Regenerate, ../gettext.m4 was updated.
  37
  38 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  39
  40         * mips-opc.c:  Change INSN_ALIAS to INSN2_ALIAS.
  41         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  42         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  43         * mips-dis.c: Ditto.
  44
  45 2005-01-20  Alan Modra  <amodra@bigpond.net.au>
  46
  47         * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
  48
  49 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  50
  51         * mips-dis.c (no_aliases): New disassembly option flag.
  52         (set_default_mips_dis_options): Init no_aliases to zero.
  53         (parse_mips_dis_option): Handle no-aliases option.
  54         (print_insn_mips): Ignore table entries that are aliases
  55         if no_aliases is set.
  56         (print_insn_mips16): Ditto.
  57         * mips-opc.c (mips_builtin_opcodes): Add initializer column for
  58         new pinfo2 member and add INSN_ALIAS initializers as needed.  Also
  59         move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
  60         * mips16-opc.c (mips16_opcodes): Ditto.
  61
  62 2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
  63
  64         * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
  65         (inheritance diagram): Add missing edge.
  66         (arch_sh1_up): Rename arch_sh_up to match external name to make life
  67         easier for the testsuite.
  68         (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
  69         (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
  70         (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
  71         arch_sh2a_or_sh4_up child.
  72         (sh_table): Do renaming as above.
  73         Correct comment for ldc.l for gas testsuite to read.
  74         Remove rogue mul.l from sh1 (duplicate of the one for sh2).
  75         Correct comments for movy.w and movy.l for gas testsuite to read.
  76         Correct comments for fmov.d and fmov.s for gas testsuite to read.
  77
  78 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  79
  80         * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
  81
  82 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
  85
  86 2005-01-10  Andreas Schwab  <schwab@suse.de>
  87
  88         * disassemble.c (disassemble_init_for_target) <case
  89         bfd_arch_ia64>: Set skip_zeroes to 16.
  90         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
  91
  92 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
  93
  94         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
  95
  96 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
  97
  98         * avr-dis.c: Prettyprint. Added printing of symbol names in all
  99         memory references. Convert avr_operand() to C90 formatting.
 100
 101 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
 102
 103         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
 104
 105 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 106
 107         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
 108         (no_op_insn): Initialize array with instructions that have no
 109         operands.
 110         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
 111
 112 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
 113
 114         * arm-dis.c: Correct top-level comment.
 115
 116 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
 117
 118         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
 119         architecuture defining the insn.
 120         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
 121         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
 122         field.
 123         Also include opcode/arm.h.
 124         * Makefile.am (arm-dis.lo): Update dependency list.
 125         * Makefile.in: Regenerate.
 126
 127 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 128
 129         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
 130         reflect the change to the short immediate syntax.
 131
 132 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 133
 134         * or32-opc.c (debug): Warning fix.
 135         * po/POTFILES.in: Regenerate.
 136
 137         * maxq-dis.c: Formatting.
 138         (print_insn): Warning fix.
 139
 140 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
 141
 142         * arm-dis.c (WORD_ADDRESS): Define.
 143         (print_insn): Use it.  Correct big-endian end-of-section handling.
 144
 145 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 146             Vineet Sharma      <vineets@noida.hcltech.com>
 147
 148         * maxq-dis.c: New file.
 149         * disassemble.c (ARCH_maxq): Define.
 150         (disassembler): Add 'print_insn_maxq_little' for handling maxq
 151         instructions..
 152         * configure.in: Add case for bfd_maxq_arch.
 153         * configure: Regenerate.
 154         * Makefile.am: Add support for maxq-dis.c
 155         * Makefile.in: Regenerate.
 156         * aclocal.m4: Regenerate.
 157
 158 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 159
 160         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
 161         mode.
 162         * crx-dis.c: Likewise.
 163
 164 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 165
 166         Generally, handle CRISv32.
 167         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
 168         (struct cris_disasm_data): New type.
 169         (format_reg, format_hex, cris_constraint, print_flags)
 170         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
 171         callers changed.
 172         (format_sup_reg, print_insn_crisv32_with_register_prefix)
 173         (print_insn_crisv32_without_register_prefix)
 174         (print_insn_crisv10_v32_with_register_prefix)
 175         (print_insn_crisv10_v32_without_register_prefix)
 176         (cris_parse_disassembler_options): New functions.
 177         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
 178         parameter.  All callers changed.
 179         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
 180         failure.
 181         (cris_constraint) <case 'Y', 'U'>: New cases.
 182         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
 183         for constraint 'n'.
 184         (print_with_operands) <case 'Y'>: New case.
 185         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 186         <case 'N', 'Y', 'Q'>: New cases.
 187         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 188         (print_insn_cris_with_register_prefix)
 189         (print_insn_cris_without_register_prefix): Call
 190         cris_parse_disassembler_options.
 191         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 192         for CRISv32 and the size of immediate operands.  New v32-only
 193         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 194         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 195         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 196         Change brp to be v3..v10.
 197         (cris_support_regs): New vector.
 198         (cris_opcodes): Update head comment.  New format characters '[',
 199         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 200         Add new opcodes for v32 and adjust existing opcodes to accommodate
 201         differences to earlier variants.
 202         (cris_cond15s): New vector.
 203
 204 2004-11-04 Jan Beulich <jbeulich@novell.com>
 205
 206         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 207         (indirEb): Remove.
 208         (Mp): Use f_mode rather than none at all.
 209         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 210         replaces what previously was x_mode; x_mode now means 128-bit SSE
 211         operands.
 212         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 213         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 214         pinsrw's second operand is Edqw.
 215         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 216         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 217         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 218         mode when an operand size override is present or always suffixing.
 219         More instructions will need to be added to this group.
 220         (putop): Handle new macro chars 'C' (short/long suffix selector),
 221         'I' (Intel mode override for following macro char), and 'J' (for
 222         adding the 'l' prefix to far branches in AT&T mode). When an
 223         alternative was specified in the template, honor macro character when
 224         specified for Intel mode.
 225         (OP_E): Handle new *_mode values. Correct pointer specifications for
 226         memory operands. Consolidate output of index register.
 227         (OP_G): Handle new *_mode values.
 228         (OP_I): Handle const_1_mode.
 229         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 230         respective opcode prefix bits have been consumed.
 231         (OP_EM, OP_EX): Provide some default handling for generating pointer
 232         specifications.
 233
 234 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 235
 236         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 237         COP_INST macro.
 238
 239 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 240
 241         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 242         (getregliststring): Support HI/LO and user registers.
 243         * crx-opc.c (crx_instruction): Update data structure according to the
 244         rearrangement done in CRX opcode header file.
 245         (crx_regtab):  Likewise.
 246         (crx_optab):  Likewise.
 247         (crx_instruction): Reorder load/stor instructions, remove unsupported
 248         formats.
 249         support new Co-Processor instruction 'cpi'.
 250
 251 2004-10-27  Nick Clifton  <nickc@redhat.com>
 252
 253         * opcodes/iq2000-asm.c: Regenerate.
 254         * opcodes/iq2000-desc.c: Regenerate.
 255         * opcodes/iq2000-desc.h: Regenerate.
 256         * opcodes/iq2000-dis.c: Regenerate.
 257         * opcodes/iq2000-ibld.c: Regenerate.
 258         * opcodes/iq2000-opc.c: Regenerate.
 259         * opcodes/iq2000-opc.h: Regenerate.
 260
 261 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 262
 263         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 264         us4, us5 (respectively).
 265         Remove unsupported 'popa' instruction.
 266         Reverse operands order in store co-processor instructions.
 267
 268 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 269
 270         * Makefile.am: Run "make dep-am"
 271         * Makefile.in: Regenerate.
 272
 273 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 274
 275         * xtensa-dis.c: Use ISO C90 formatting.
 276
 277 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 278
 279         * ppc-opc.c: Revert 2004-09-09 change.
 280
 281 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 282
 283         * xtensa-dis.c (state_names): Delete.
 284         (fetch_data): Use xtensa_isa_maxlength.
 285         (print_xtensa_operand): Replace operand parameter with opcode/operand
 286         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 287         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 288         instruction bundles.  Use xmalloc instead of malloc.
 289
 290 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 291
 292         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 293         initializers.
 294
 295 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 296
 297         * crx-opc.c (crx_instruction): Support Co-processor insns.
 298         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 299         (getregliststring): Change function to use the above enum.
 300         (print_arg): Handle CO-Processor insns.
 301         (crx_cinvs): Add 'b' option to invalidate the branch-target
 302         cache.
 303
 304 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 305
 306         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 307         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 308         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 309         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 310         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 311
 312 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 313
 314         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 315         rather than add it.
 316
 317 2004-09-30  Paul Brook  <paul@codesourcery.com>
 318
 319         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 320         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 321
 322 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 325         (CONFIG_STATUS_DEPENDENCIES): New.
 326         (Makefile): Removed.
 327         (config.status): Likewise.
 328         * Makefile.in: Regenerated.
 329
 330 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 331
 332         * Makefile.am: Run "make dep-am".
 333         * Makefile.in: Regenerate.
 334         * aclocal.m4: Regenerate.
 335         * configure: Regenerate.
 336         * po/POTFILES.in: Regenerate.
 337         * po/opcodes.pot: Regenerate.
 338
 339 2004-09-11  Andreas Schwab  <schwab@suse.de>
 340
 341         * configure: Rebuild.
 342
 343 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 344
 345         * ppc-opc.c (L): Make this field not optional.
 346
 347 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 348
 349         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 350         Fix parameter to 'm[t|f]csr' insns.
 351
 352 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 353
 354         * configure.in: Autoupdate to autoconf 2.59.
 355         * aclocal.m4: Rebuild with aclocal 1.4p6.
 356         * configure: Rebuild with autoconf 2.59.
 357         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 358         bfd changes for autoconf 2.59 on the way).
 359         * config.in: Rebuild with autoheader 2.59.
 360
 361 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 362
 363         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 364
 365 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 366
 367         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 368         (GRPPADLCK2): New define.
 369         (twobyte_has_modrm): True for 0xA6.
 370         (grps): GRPPADLCK2 for opcode 0xA6.
 371
 372 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 373
 374         Introduce SH2a support.
 375         * sh-opc.h (arch_sh2a_base): Renumber.
 376         (arch_sh2a_nofpu_base): Remove.
 377         (arch_sh_base_mask): Adjust.
 378         (arch_opann_mask): New.
 379         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 380         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 381         (sh_table): Adjust whitespace.
 382         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 383         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 384         instruction list throughout.
 385         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 386         of arch_sh2a in instruction list throughout.
 387         (arch_sh2e_up): Accomodate above changes.
 388         (arch_sh2_up): Ditto.
 389         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 390         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 391         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 392         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 393         * sh-opc.h (arch_sh2a_nofpu): New.
 394         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 395         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 396         instruction.
 397         2004-01-20  DJ Delorie  <dj@redhat.com>
 398         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 399         2003-12-29  DJ Delorie  <dj@redhat.com>
 400         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 401         sh_opcode_info, sh_table): Add sh2a support.
 402         (arch_op32): New, to tag 32-bit opcodes.
 403         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 404         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 405         * sh-opc.h (arch_sh2a): Add.
 406         * sh-dis.c (arch_sh2a): Handle.
 407         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 408
 409 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 410
 411         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 412
 413 2004-07-22  Nick Clifton  <nickc@redhat.com>
 414
 415         PR/280
 416         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 417         insns - this is done by objdump itself.
 418         * h8500-dis.c (print_insn_h8500): Likewise.
 419
 420 2004-07-21  Jan Beulich <jbeulich@novell.com>
 421
 422         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 423         regardless of address size prefix in effect.
 424         (ptr_reg): Size or address registers does not depend on rex64, but
 425         on the presence of an address size override.
 426         (OP_MMX): Use rex.x only for xmm registers.
 427         (OP_EM): Use rex.z only for xmm registers.
 428
 429 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 430
 431         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 432         move/branch operations to the bottom so that VR5400 multimedia
 433         instructions take precedence in disassembly.
 434
 435 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 436
 437         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 438         ISA-specific "break" encoding.
 439
 440 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 441
 442         * arm-opc.h: Fix typo in comment.
 443
 444 2004-07-11  Andreas Schwab  <schwab@suse.de>
 445
 446         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 447
 448 2004-07-09  Andreas Schwab  <schwab@suse.de>
 449
 450         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 451
 452 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 453
 454         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 455         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 456         (crx-dis.lo): New target.
 457         (crx-opc.lo): Likewise.
 458         * Makefile.in: Regenerate.
 459         * configure.in: Handle bfd_crx_arch.
 460         * configure: Regenerate.
 461         * crx-dis.c: New file.
 462         * crx-opc.c: New file.
 463         * disassemble.c (ARCH_crx): Define.
 464         (disassembler): Handle ARCH_crx.
 465
 466 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 467
 468         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 469         * ia64-asmtab.c: Regnerate.
 470
 471 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 472
 473         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 474         (extract_fxm): Don't test dialect.
 475         (XFXFXM_MASK): Include the power4 bit.
 476         (XFXM): Add p4 param.
 477         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 478
 479 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 480
 481         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 482         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 483
 484 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 485
 486         * ppc-opc.c (BH, XLBH_MASK): Define.
 487         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 488
 489 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 490
 491         * i386-dis.c (x_mode): Comment.
 492         (two_source_ops): File scope.
 493         (float_mem): Correct fisttpll and fistpll.
 494         (float_mem_mode): New table.
 495         (dofloat): Use it.
 496         (OP_E): Correct intel mode PTR output.
 497         (ptr_reg): Use open_char and close_char.
 498         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 499         operands.  Set two_source_ops.
 500
 501 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 502
 503         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 504         instead of _raw_size.
 505
 506 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 507
 508         * ia64-gen.c (in_iclass): Handle more postinc st
 509         and ld variants.
 510         * ia64-asmtab.c: Rebuilt.
 511
 512 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 513
 514         * s390-opc.txt: Correct architecture mask for some opcodes.
 515         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 516         in the esa mode as well.
 517
 518 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 519
 520         * sh-dis.c (target_arch): Make unsigned.
 521         (print_insn_sh): Replace (most of) switch with a call to
 522         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 523         * sh-opc.h: Redefine architecture flags values.
 524         Add sh3-nommu architecture.
 525         Reorganise <arch>_up macros so they make more visual sense.
 526         (SH_MERGE_ARCH_SET): Define new macro.
 527         (SH_VALID_BASE_ARCH_SET): Likewise.
 528         (SH_VALID_MMU_ARCH_SET): Likewise.
 529         (SH_VALID_CO_ARCH_SET): Likewise.
 530         (SH_VALID_ARCH_SET): Likewise.
 531         (SH_MERGE_ARCH_SET_VALID): Likewise.
 532         (SH_ARCH_SET_HAS_FPU): Likewise.
 533         (SH_ARCH_SET_HAS_DSP): Likewise.
 534         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 535         (sh_get_arch_from_bfd_mach): Add prototype.
 536         (sh_get_arch_up_from_bfd_mach): Likewise.
 537         (sh_get_bfd_mach_from_arch_set): Likewise.
 538         (sh_merge_bfd_arc): Likewise.
 539
 540 2004-05-24  Peter Barada  <peter@the-baradas.com>
 541
 542         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 543         into new match_insn_m68k function.  Loop over canidate
 544         matches and select first that completely matches.
 545         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 546         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 547         to verify addressing for MAC/EMAC.
 548         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 549         reigster halves since 'fpu' and 'spl' look misleading.
 550         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 551         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 552         first, tighten up match masks.
 553         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 554         'size' from special case code in print_insn_m68k to
 555         determine decode size of insns.
 556
 557 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 558
 559         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 560         well as when -mpower4.
 561
 562 2004-05-13  Nick Clifton  <nickc@redhat.com>
 563
 564         * po/fr.po: Updated French translation.
 565
 566 2004-05-05  Peter Barada  <peter@the-baradas.com>
 567
 568         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 569         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 570         * m68k-op.c: Switch from ColdFire chips to core variants.
 571
 572 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 573
 574         PR 147.
 575         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 576
 577 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 578
 579         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 580         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 581
 582 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 583
 584         * sh-dis.c (print_insn_sh): Print the value in constant pool
 585         as a symbol if it looks like a symbol.
 586
 587 2004-04-22  Peter Barada <peter@the-baradas.com>
 588
 589         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 590         appropriate ColdFire architectures.
 591         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 592         mask addressing.
 593         Add EMAC instructions, fix MAC instructions. Remove
 594         macmw/macml/msacmw/msacml instructions since mask addressing now
 595         supported.
 596
 597 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 598
 599         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 600         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 601         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 602         macro.  Adjust all users.
 603
 604 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 605
 606         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 607         separately.
 608
 609 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 610
 611         * m32r-asm.c: Regenerate.
 612
 613 2004-03-29  Stan Shebs  <shebs@apple.com>
 614
 615         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 616         used.
 617
 618 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 619
 620         * aclocal.m4: Regenerate.
 621         * config.in: Regenerate.
 622         * configure: Regenerate.
 623         * po/POTFILES.in: Regenerate.
 624         * po/opcodes.pot: Regenerate.
 625
 626 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 627
 628         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 629         PPC_OPERANDS_GPR_0.
 630         * ppc-opc.c (RA0): Define.
 631         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 632         (RAOPT): Rename from RAO.  Update all uses.
 633         (powerpc_opcodes): Use RA0 as appropriate.
 634
 635 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 636
 637         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 638
 639 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 640
 641         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 642
 643 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 644
 645         * i386-dis.c (GRPPLOCK): Delete.
 646         (grps): Delete GRPPLOCK entry.
 647
 648 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 649
 650         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 651         (M, Mp): Use OP_M.
 652         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 653         (GRPPADLCK): Define.
 654         (dis386): Use NOP_Fixup on "nop".
 655         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 656         (twobyte_has_modrm): Set for 0xa7.
 657         (padlock_table): Delete.  Move to..
 658         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 659         and clflush.
 660         (print_insn): Revert PADLOCK_SPECIAL code.
 661         (OP_E): Delete sfence, lfence, mfence checks.
 662
 663 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 664
 665         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 666         (INVLPG_Fixup): New function.
 667         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 668
 669 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 670
 671         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 672         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 673         (padlock_table): New struct with PadLock instructions.
 674         (print_insn): Handle PADLOCK_SPECIAL.
 675
 676 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 677
 678         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 679         (OP_E): Twiddle clflush to sfence here.
 680
 681 2004-03-08  Nick Clifton  <nickc@redhat.com>
 682
 683         * po/de.po: Updated German translation.
 684
 685 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 686
 687         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 688         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 689         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 690         accordingly.
 691
 692 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 693
 694         * frv-asm.c: Regenerate.
 695         * frv-desc.c: Regenerate.
 696         * frv-desc.h: Regenerate.
 697         * frv-dis.c: Regenerate.
 698         * frv-ibld.c: Regenerate.
 699         * frv-opc.c: Regenerate.
 700         * frv-opc.h: Regenerate.
 701
 702 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 703
 704         * frv-desc.c, frv-opc.c: Regenerate.
 705
 706 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 707
 708         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 709
 710 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 711
 712         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 713         Also correct mistake in the comment.
 714
 715 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 716
 717         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 718         ensure that double registers have even numbers.
 719         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 720         that reserved instruction 0xfffd does not decode the same
 721         as 0xfdfd (ftrv).
 722         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 723         REG_N refers to a double register.
 724         Add REG_N_B01 nibble type and use it instead of REG_NM
 725         in ftrv.
 726         Adjust the bit patterns in a few comments.
 727
 728 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 729
 730         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 731
 732 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 733
 734         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 735
 736 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 737
 738         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 739
 740 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 741
 742         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 743         mtivor32, mtivor33, mtivor34.
 744
 745 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 746
 747         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 748
 749 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 750
 751         * arm-opc.h Maverick accumulator register opcode fixes.
 752
 753 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 754
 755         * m32r-dis.c: Regenerate.
 756
 757 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 758
 759         * sh-opc.h (sh_table): "fsrra", not "fssra".
 760
 761 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 762
 763         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 764         contraints.
 765
 766 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 767
 768         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 769
 770 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 771
 772         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 773         1.  Don't print scale factor on AT&T mode when index missing.
 774
 775 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 776
 777         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 778         when loaded into XR registers.
 779
 780 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 781
 782         * frv-desc.h: Regenerate.
 783         * frv-desc.c: Regenerate.
 784         * frv-opc.c: Regenerate.
 785
 786 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 787
 788         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 789
 790 2004-01-09  Paul Brook  <paul@codesourcery.com>
 791
 792         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 793         specific opcodes.
 794
 795 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 796
 797         * Makefile.am (libopcodes_la_DEPENDENCIES)
 798         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 799         comment about the problem.
 800         * Makefile.in: Regenerate.
 801
 802 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 803
 804         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 805         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 806         cut&paste errors in shifting/truncating numerical operands.
 807         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 808         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 809         (parse_uslo16): Likewise.
 810         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 811         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 812         (parse_s12): Likewise.
 813         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 814         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 815         (parse_uslo16): Likewise.
 816         (parse_uhi16): Parse gothi and gotfuncdeschi.
 817         (parse_d12): Parse got12 and gotfuncdesc12.
 818         (parse_s12): Likewise.
 819
 820 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 821
 822         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 823         instruction which looks similar to an 'rla' instruction.
 824
 825 For older changes see ChangeLog-0203
 826 \f
 827 Local Variables:
 828 mode: change-log
 829 left-margin: 8
 830 fill-column: 74
 831 version-control: never
 832 End: