opcodes/ChangeLog

   1 2017-09-26  do  <do@nerilex.org>
   2
   3         PR 22123
   4         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
   5         be used on CPUs that have emacs support.
   6
   7 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
   8
   9         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
  10
  11 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
  12
  13         * nds32-asm.c: Rename __BIT() to N32_BIT().
  14         * nds32-asm.h: Likewise.
  15         * nds32-dis.c: Likewise.
  16
  17 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386-dis.c (last_active_prefix): Removed.
  20         (ckprefix): Don't set last_active_prefix.
  21         (NOTRACK_Fixup): Don't check last_active_prefix.
  22
  23 2017-08-31  Nick Clifton  <nickc@redhat.com>
  24
  25         * po/fr.po: Updated French translation.
  26
  27 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
  28
  29         * ft32-dis.c (print_insn_ft32): Correct display of non-address
  30         fields.
  31
  32 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
  33             Edmar Wienskoski <edmar.wienskoski@nxp.com>
  34
  35         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
  36         PPC_OPCODE_EFS2 flag to "e200z4" entry.
  37         New entries efs2 and spe2.
  38         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
  39         (SPE2_OPCD_SEGS): New macro.
  40         (spe2_opcd_indices): New.
  41         (disassemble_init_powerpc): Handle SPE2 opcodes.
  42         (lookup_spe2): New function.
  43         (print_insn_powerpc): call lookup_spe2.
  44         * ppc-opc.c (insert_evuimm1_ex0): New function.
  45         (extract_evuimm1_ex0): Likewise.
  46         (insert_evuimm_lt8): Likewise.
  47         (extract_evuimm_lt8): Likewise.
  48         (insert_off_spe2): Likewise.
  49         (extract_off_spe2): Likewise.
  50         (insert_Ddd): Likewise.
  51         (extract_Ddd): Likewise.
  52         (DD): New operand.
  53         (EVUIMM_LT8): Likewise.
  54         (EVUIMM_LT16): Adjust.
  55         (MMMM): New operand.
  56         (EVUIMM_1): Likewise.
  57         (EVUIMM_1_EX0): Likewise.
  58         (EVUIMM_2): Adjust.
  59         (NNN): New operand.
  60         (VX_OFF_SPE2): Likewise.
  61         (BBB): Likewise.
  62         (DDD): Likewise.
  63         (VX_MASK_DDD): New mask.
  64         (HH): New operand.
  65         (VX_RA_CONST): New macro.
  66         (VX_RA_CONST_MASK): Likewise.
  67         (VX_RB_CONST): Likewise.
  68         (VX_RB_CONST_MASK): Likewise.
  69         (VX_OFF_SPE2_MASK): Likewise.
  70         (VX_SPE_CRFD): Likewise.
  71         (VX_SPE_CRFD_MASK VX): Likewise.
  72         (VX_SPE2_CLR): Likewise.
  73         (VX_SPE2_CLR_MASK): Likewise.
  74         (VX_SPE2_SPLATB): Likewise.
  75         (VX_SPE2_SPLATB_MASK): Likewise.
  76         (VX_SPE2_OCTET): Likewise.
  77         (VX_SPE2_OCTET_MASK): Likewise.
  78         (VX_SPE2_DDHH): Likewise.
  79         (VX_SPE2_DDHH_MASK): Likewise.
  80         (VX_SPE2_HH): Likewise.
  81         (VX_SPE2_HH_MASK): Likewise.
  82         (VX_SPE2_EVMAR): Likewise.
  83         (VX_SPE2_EVMAR_MASK): Likewise.
  84         (PPCSPE2): Likewise.
  85         (PPCEFS2): Likewise.
  86         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
  87         (powerpc_macros): Map old SPE instructions have new names
  88         with the same opcodes. Add SPE2 instructions which just are
  89         mapped to SPE2.
  90         (spe2_opcodes): Add SPE2 opcodes.
  91
  92 2017-08-23  Alan Modra  <amodra@gmail.com>
  93
  94         * ppc-opc.c: Formatting and comment fixes.  Move insert and
  95         extract functions earlier, deleting forward declarations.
  96         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
  97         RA_MASK.
  98
  99 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 100
 101         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 102
 103 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 104             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 105
 106         * ppc-opc.c (insert_evuimm2_ex0): New function.
 107         (extract_evuimm2_ex0): Likewise.
 108         (insert_evuimm4_ex0): Likewise.
 109         (extract_evuimm4_ex0): Likewise.
 110         (insert_evuimm8_ex0): Likewise.
 111         (extract_evuimm8_ex0): Likewise.
 112         (insert_evuimm_lt16): Likewise.
 113         (extract_evuimm_lt16): Likewise.
 114         (insert_rD_rS_even): Likewise.
 115         (extract_rD_rS_even): Likewise.
 116         (insert_off_lsp): Likewise.
 117         (extract_off_lsp): Likewise.
 118         (RD_EVEN): New operand.
 119         (RS_EVEN): Likewise.
 120         (RSQ): Adjust.
 121         (EVUIMM_LT16): New operand.
 122         (HTM_SI): Adjust.
 123         (EVUIMM_2_EX0): New operand.
 124         (EVUIMM_4): Adjust.
 125         (EVUIMM_4_EX0): New operand.
 126         (EVUIMM_8): Adjust.
 127         (EVUIMM_8_EX0): New operand.
 128         (WS): Adjust.
 129         (VX_OFF): New operand.
 130         (VX_LSP): New macro.
 131         (VX_LSP_MASK): Likewise.
 132         (VX_LSP_OFF_MASK): Likewise.
 133         (PPC_OPCODE_LSP): Likewise.
 134         (vle_opcodes): Add LSP opcodes.
 135         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 136
 137 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 138
 139         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 140         register operands in CRC instructions.
 141         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 142         comments.
 143
 144 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         * disassemble.c (disassembler): Mark big and mach with
 147         ATTRIBUTE_UNUSED.
 148
 149 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 150
 151         * disassemble.c (disassembler): Remove arch/mach/endian
 152         assertions.
 153
 154 2017-07-25  Nick Clifton  <nickc@redhat.com>
 155
 156         PR 21739
 157         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 158         message.
 159         (insert_r0): Likewise.
 160         (insert_r1): Likewise.
 161         (insert_r2): Likewise.
 162         (insert_r3): Likewise.
 163         (insert_sp): Likewise.
 164         (insert_gp): Likewise.
 165         (insert_pcl): Likewise.
 166         (insert_blink): Likewise.
 167         (insert_ilink1): Likewise.
 168         (insert_ilink2): Likewise.
 169         (insert_ras): Likewise.
 170         (insert_rbs): Likewise.
 171         (insert_rcs): Likewise.
 172         (insert_simm3s): Likewise.
 173         (insert_rrange): Likewise.
 174         (insert_r13el): Likewise.
 175         (insert_fpel): Likewise.
 176         (insert_blinkel): Likewise.
 177         (insert_pclel): Likewise.
 178         (insert_nps_bitop_size_2b): Likewise.
 179         (insert_nps_imm_offset): Likewise.
 180         (insert_nps_imm_entry): Likewise.
 181         (insert_nps_size_16bit): Likewise.
 182         (insert_nps_##NAME##_pos): Likewise.
 183         (insert_nps_##NAME): Likewise.
 184         (insert_nps_bitop_ins_ext): Likewise.
 185         (insert_nps_##NAME): Likewise.
 186         (insert_nps_min_hofs): Likewise.
 187         (insert_nps_##NAME): Likewise.
 188         (insert_nps_rbdouble_64): Likewise.
 189         (insert_nps_misc_imm_offset): Likewise.
 190         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 191         option description.
 192
 193 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 194             Jiong Wang  <jiong.wang@arm.com>
 195
 196         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 197         correct the print.
 198         * aarch64-dis-2.c: Regenerated.
 199
 200 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 201
 202         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 203         table.
 204
 205 2017-07-20  Nick Clifton  <nickc@redhat.com>
 206
 207         * po/de.po: Updated German translation.
 208
 209 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 210
 211         * arc-regs.h (sec_stat): New aux register.
 212         (aux_kernel_sp): Likewise.
 213         (aux_sec_u_sp): Likewise.
 214         (aux_sec_k_sp): Likewise.
 215         (sec_vecbase_build): Likewise.
 216         (nsc_table_top): Likewise.
 217         (nsc_table_base): Likewise.
 218         (ersec_stat): Likewise.
 219         (aux_sec_except): Likewise.
 220
 221 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 222
 223         * arc-opc.c (extract_uimm12_20): New function.
 224         (UIMM12_20): New operand.
 225         (SIMM3_5_S): Adjust.
 226         * arc-tbl.h (sjli): Add new instruction.
 227
 228 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 229             John Eric Martin  <John.Martin@emmicro-us.com>
 230
 231         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 232         (UIMM3_23): Adjust accordingly.
 233         * arc-regs.h: Add/correct jli_base register.
 234         * arc-tbl.h (jli_s): Likewise.
 235
 236 2017-07-18  Nick Clifton  <nickc@redhat.com>
 237
 238         PR 21775
 239         * aarch64-opc.c: Fix spelling typos.
 240         * i386-dis.c: Likewise.
 241
 242 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 243
 244         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 245         max_addr_offset and octets variables to size_t.
 246
 247 2017-07-12  Alan Modra  <amodra@gmail.com>
 248
 249         * po/da.po: Update from translationproject.org/latest/opcodes/.
 250         * po/de.po: Likewise.
 251         * po/es.po: Likewise.
 252         * po/fi.po: Likewise.
 253         * po/fr.po: Likewise.
 254         * po/id.po: Likewise.
 255         * po/it.po: Likewise.
 256         * po/nl.po: Likewise.
 257         * po/pt_BR.po: Likewise.
 258         * po/ro.po: Likewise.
 259         * po/sv.po: Likewise.
 260         * po/tr.po: Likewise.
 261         * po/uk.po: Likewise.
 262         * po/vi.po: Likewise.
 263         * po/zh_CN.po: Likewise.
 264
 265 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 266             Alan Modra  <amodra@gmail.com>
 267
 268         * cgen.sh: Mark generated files read-only.
 269         * epiphany-asm.c: Regenerate.
 270         * epiphany-desc.c: Regenerate.
 271         * epiphany-desc.h: Regenerate.
 272         * epiphany-dis.c: Regenerate.
 273         * epiphany-ibld.c: Regenerate.
 274         * epiphany-opc.c: Regenerate.
 275         * epiphany-opc.h: Regenerate.
 276         * fr30-asm.c: Regenerate.
 277         * fr30-desc.c: Regenerate.
 278         * fr30-desc.h: Regenerate.
 279         * fr30-dis.c: Regenerate.
 280         * fr30-ibld.c: Regenerate.
 281         * fr30-opc.c: Regenerate.
 282         * fr30-opc.h: Regenerate.
 283         * frv-asm.c: Regenerate.
 284         * frv-desc.c: Regenerate.
 285         * frv-desc.h: Regenerate.
 286         * frv-dis.c: Regenerate.
 287         * frv-ibld.c: Regenerate.
 288         * frv-opc.c: Regenerate.
 289         * frv-opc.h: Regenerate.
 290         * ip2k-asm.c: Regenerate.
 291         * ip2k-desc.c: Regenerate.
 292         * ip2k-desc.h: Regenerate.
 293         * ip2k-dis.c: Regenerate.
 294         * ip2k-ibld.c: Regenerate.
 295         * ip2k-opc.c: Regenerate.
 296         * ip2k-opc.h: Regenerate.
 297         * iq2000-asm.c: Regenerate.
 298         * iq2000-desc.c: Regenerate.
 299         * iq2000-desc.h: Regenerate.
 300         * iq2000-dis.c: Regenerate.
 301         * iq2000-ibld.c: Regenerate.
 302         * iq2000-opc.c: Regenerate.
 303         * iq2000-opc.h: Regenerate.
 304         * lm32-asm.c: Regenerate.
 305         * lm32-desc.c: Regenerate.
 306         * lm32-desc.h: Regenerate.
 307         * lm32-dis.c: Regenerate.
 308         * lm32-ibld.c: Regenerate.
 309         * lm32-opc.c: Regenerate.
 310         * lm32-opc.h: Regenerate.
 311         * lm32-opinst.c: Regenerate.
 312         * m32c-asm.c: Regenerate.
 313         * m32c-desc.c: Regenerate.
 314         * m32c-desc.h: Regenerate.
 315         * m32c-dis.c: Regenerate.
 316         * m32c-ibld.c: Regenerate.
 317         * m32c-opc.c: Regenerate.
 318         * m32c-opc.h: Regenerate.
 319         * m32r-asm.c: Regenerate.
 320         * m32r-desc.c: Regenerate.
 321         * m32r-desc.h: Regenerate.
 322         * m32r-dis.c: Regenerate.
 323         * m32r-ibld.c: Regenerate.
 324         * m32r-opc.c: Regenerate.
 325         * m32r-opc.h: Regenerate.
 326         * m32r-opinst.c: Regenerate.
 327         * mep-asm.c: Regenerate.
 328         * mep-desc.c: Regenerate.
 329         * mep-desc.h: Regenerate.
 330         * mep-dis.c: Regenerate.
 331         * mep-ibld.c: Regenerate.
 332         * mep-opc.c: Regenerate.
 333         * mep-opc.h: Regenerate.
 334         * mt-asm.c: Regenerate.
 335         * mt-desc.c: Regenerate.
 336         * mt-desc.h: Regenerate.
 337         * mt-dis.c: Regenerate.
 338         * mt-ibld.c: Regenerate.
 339         * mt-opc.c: Regenerate.
 340         * mt-opc.h: Regenerate.
 341         * or1k-asm.c: Regenerate.
 342         * or1k-desc.c: Regenerate.
 343         * or1k-desc.h: Regenerate.
 344         * or1k-dis.c: Regenerate.
 345         * or1k-ibld.c: Regenerate.
 346         * or1k-opc.c: Regenerate.
 347         * or1k-opc.h: Regenerate.
 348         * or1k-opinst.c: Regenerate.
 349         * xc16x-asm.c: Regenerate.
 350         * xc16x-desc.c: Regenerate.
 351         * xc16x-desc.h: Regenerate.
 352         * xc16x-dis.c: Regenerate.
 353         * xc16x-ibld.c: Regenerate.
 354         * xc16x-opc.c: Regenerate.
 355         * xc16x-opc.h: Regenerate.
 356         * xstormy16-asm.c: Regenerate.
 357         * xstormy16-desc.c: Regenerate.
 358         * xstormy16-desc.h: Regenerate.
 359         * xstormy16-dis.c: Regenerate.
 360         * xstormy16-ibld.c: Regenerate.
 361         * xstormy16-opc.c: Regenerate.
 362         * xstormy16-opc.h: Regenerate.
 363
 364 2017-07-07  Alan Modra  <amodra@gmail.com>
 365
 366         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 367         * m32c-dis.c: Regenerate.
 368         * mep-dis.c: Regenerate.
 369
 370 2017-07-05  Borislav Petkov  <bp@suse.de>
 371
 372         * i386-dis.c: Enable ModRM.reg /6 aliases.
 373
 374 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 375
 376         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 377         with vmrs and vmsr.
 378
 379 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 380
 381         * configure: Regenerate.
 382
 383 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 384
 385         * po/opcodes.pot: Regenerate.
 386
 387 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 388
 389         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 390         entries to the MSA ASE instruction block.
 391
 392 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 393             Maciej W. Rozycki  <macro@imgtec.com>
 394
 395         * micromips-opc.c (XPA, XPAVZ): New macros.
 396         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 397         "mthgc0".
 398
 399 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 400             Maciej W. Rozycki  <macro@imgtec.com>
 401
 402         * micromips-opc.c (I36): New macro.
 403         (micromips_opcodes): Add "eretnc".
 404
 405 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 406             Andrew Bennett  <andrew.bennett@imgtec.com>
 407
 408         * mips-dis.c (mips_calculate_combination_ases): Handle the
 409         ASE_XPA_VIRT flag.
 410         (parse_mips_ase_option): New function.
 411         (parse_mips_dis_option): Factor out ASE option handling to the
 412         new function.  Call `mips_calculate_combination_ases'.
 413         * mips-opc.c (XPAVZ): New macro.
 414         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 415         "mfhgc0", "mthc0" and "mthgc0".
 416
 417 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 418
 419         * mips-dis.c (mips_calculate_combination_ases): New function.
 420         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 421         calculation to the new function.
 422         (set_default_mips_dis_options): Call the new function.
 423
 424 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 425
 426         * arc-dis.c (parse_disassembler_options): Use
 427         FOR_EACH_DISASSEMBLER_OPTION.
 428
 429 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 430
 431         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 432         disassembler option strings.
 433         (parse_cpu_option): Likewise.
 434
 435 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 436
 437         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 438         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 439         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 440         (aarch64_feature_dotprod, DOT_INSN): New.
 441         (udot, sdot): New.
 442         * aarch64-dis-2.c: Regenerated.
 443
 444 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 445
 446         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 447
 448 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 449             Matthew Fortune  <matthew.fortune@imgtec.com>
 450             Andrew Bennett  <andrew.bennett@imgtec.com>
 451
 452         * mips-formats.h (INT_BIAS): New macro.
 453         (INT_ADJ): Redefine in INT_BIAS terms.
 454         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 455         (mips_print_save_restore): New function.
 456         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 457         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 458         call.
 459         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 460         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 461         OP_SAVE_RESTORE_LIST handling, factored out from here.
 462         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 463         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 464         (mips_builtin_opcodes): Add "restore" and "save" entries.
 465         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 466         (IAMR2): New macro.
 467         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 468
 469 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 470
 471         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 472         alias; do not mark SLTI instruction as an alias.
 473
 474 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * i386-dis.c (RM_0FAE_REG_5): Removed.
 477         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 478         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 479         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 480         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 481         PREFIX_MOD_3_0F01_REG_5_RM_0.
 482         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 483         PREFIX_MOD_3_0FAE_REG_5.
 484         (mod_table): Update MOD_0FAE_REG_5.
 485         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 486         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 487         * i386-tbl.h: Regenerated.
 488
 489 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 490
 491         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 492         * i386-opc.tbl: Likewise.
 493         * i386-tbl.h: Regenerated.
 494
 495 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 498         and "jmp{&|}".
 499         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 500         prefix.
 501
 502 2017-06-19  Nick Clifton  <nickc@redhat.com>
 503
 504         PR binutils/21614
 505         * score-dis.c (score_opcodes): Add sentinel.
 506
 507 2017-06-16  Alan Modra  <amodra@gmail.com>
 508
 509         * rx-decode.c: Regenerate.
 510
 511 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 512
 513         PR binutils/21594
 514         * i386-dis.c (OP_E_register): Check valid bnd register.
 515         (OP_G): Likewise.
 516
 517 2017-06-15  Nick Clifton  <nickc@redhat.com>
 518
 519         PR binutils/21595
 520         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 521         range value.
 522
 523 2017-06-15  Nick Clifton  <nickc@redhat.com>
 524
 525         PR binutils/21588
 526         * rl78-decode.opc (OP_BUF_LEN): Define.
 527         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 528         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 529         array.
 530         * rl78-decode.c: Regenerate.
 531
 532 2017-06-15  Nick Clifton  <nickc@redhat.com>
 533
 534         PR binutils/21586
 535         * bfin-dis.c (gregs): Clip index to prevent overflow.
 536         (regs): Likewise.
 537         (regs_lo): Likewise.
 538         (regs_hi): Likewise.
 539
 540 2017-06-14  Nick Clifton  <nickc@redhat.com>
 541
 542         PR binutils/21576
 543         * score7-dis.c (score_opcodes): Add sentinel.
 544
 545 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 546
 547         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 548         * arm-dis.c: Likewise.
 549         * ia64-dis.c: Likewise.
 550         * mips-dis.c: Likewise.
 551         * spu-dis.c: Likewise.
 552         * disassemble.h (print_insn_aarch64): New declaration, moved from
 553         include/dis-asm.h.
 554         (print_insn_big_arm, print_insn_big_mips): Likewise.
 555         (print_insn_i386, print_insn_ia64): Likewise.
 556         (print_insn_little_arm, print_insn_little_mips): Likewise.
 557
 558 2017-06-14  Nick Clifton  <nickc@redhat.com>
 559
 560         PR binutils/21587
 561         * rx-decode.opc: Include libiberty.h
 562         (GET_SCALE): New macro - validates access to SCALE array.
 563         (GET_PSCALE): New macro - validates access to PSCALE array.
 564         (DIs, SIs, S2Is, rx_disp): Use new macros.
 565         * rx-decode.c: Regenerate.
 566
 567 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 568
 569         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 570
 571 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 572
 573         * arc-dis.c (enforced_isa_mask): Declare.
 574         (cpu_types): Likewise.
 575         (parse_cpu_option): New function.
 576         (parse_disassembler_options): Use it.
 577         (print_insn_arc): Use enforced_isa_mask.
 578         (print_arc_disassembler_options): Document new options.
 579
 580 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 581
 582         * alpha-dis.c: Include disassemble.h, don't include
 583         dis-asm.h.
 584         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
 585         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
 586         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
 587         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
 588         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
 589         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
 590         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
 591         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
 592         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
 593         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
 594         * moxie-dis.c, msp430-dis.c, mt-dis.c:
 595         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
 596         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
 597         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
 598         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
 599         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
 600         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
 601         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
 602         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
 603         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
 604         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
 605         * z80-dis.c, z8k-dis.c: Likewise.
 606         * disassemble.h: New file.
 607
 608 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 609
 610         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
 611         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
 612
 613 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 614
 615         * disassemble.c (disassembler): Add arguments a, big and mach.
 616         Use them.
 617
 618 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
 619
 620         * i386-dis.c (NOTRACK_Fixup): New.
 621         (NOTRACK): Likewise.
 622         (NOTRACK_PREFIX): Likewise.
 623         (last_active_prefix): Likewise.
 624         (reg_table): Use NOTRACK on indirect call and jmp.
 625         (ckprefix): Set last_active_prefix.
 626         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
 627         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
 628         * i386-opc.h (NoTrackPrefixOk): New.
 629         (i386_opcode_modifier): Add notrackprefixok.
 630         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
 631         Add notrack.
 632         * i386-tbl.h: Regenerated.
 633
 634 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 635
 636         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
 637         (X_IMM2): Define.
 638         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
 639         bfd_mach_sparc_v9m8.
 640         (print_insn_sparc): Handle new operand types.
 641         * sparc-opc.c (MASK_M8): Define.
 642         (v6): Add MASK_M8.
 643         (v6notlet): Likewise.
 644         (v7): Likewise.
 645         (v8): Likewise.
 646         (v9): Likewise.
 647         (v9a): Likewise.
 648         (v9b): Likewise.
 649         (v9c): Likewise.
 650         (v9d): Likewise.
 651         (v9e): Likewise.
 652         (v9v): Likewise.
 653         (v9m): Likewise.
 654         (v9andleon): Likewise.
 655         (m8): Define.
 656         (HWS_VM8): Define.
 657         (HWS2_VM8): Likewise.
 658         (sparc_opcode_archs): Add entry for "m8".
 659         (sparc_opcodes): Add OSA2017 and M8 instructions
 660         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
 661         fpx{ll,ra,rl}64x,
 662         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
 663         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
 664         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
 665         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
 666         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
 667         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
 668         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
 669         ASI_CORE_SELECT_COMMIT_NHT.
 670
 671 2017-05-18  Alan Modra  <amodra@gmail.com>
 672
 673         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
 674         * aarch64-dis.c: Likewise.
 675         * aarch64-gen.c: Likewise.
 676         * aarch64-opc.c: Likewise.
 677
 678 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 679             Matthew Fortune  <matthew.fortune@imgtec.com>
 680
 681         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
 682         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
 683         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
 684         (print_insn_arg) <OP_REG28>: Add handler.
 685         (validate_insn_args) <OP_REG28>: Handle.
 686         (print_mips16_insn_arg): Handle MIPS16 instructions that require
 687         32-bit encoding and 9-bit immediates.
 688         (print_insn_mips16): Handle MIPS16 instructions that require
 689         32-bit encoding and MFC0/MTC0 operand decoding.
 690         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
 691         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
 692         (RD_C0, WR_C0, E2, E2MT): New macros.
 693         (mips16_opcodes): Add entries for MIPS16e2 instructions:
 694         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
 695         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
 696         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
 697         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
 698         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
 699         instructions, "swl", "swr", "sync" and its "sync_acquire",
 700         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
 701         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
 702         regular/extended entries for original MIPS16 ISA revision
 703         instructions whose extended forms are subdecoded in the MIPS16e2
 704         ISA revision: "li", "sll" and "srl".
 705
 706 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
 707
 708         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
 709         reference in CP0 move operand decoding.
 710
 711 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 712
 713         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
 714         type to hexadecimal.
 715         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
 716
 717 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
 718
 719         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
 720         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
 721         "sync_rmb" and "sync_wmb" as aliases.
 722         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
 723         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
 724
 725 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
 726
 727         * arc-dis.c (parse_option): Update quarkse_em option..
 728         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
 729         QUARKSE1.
 730         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
 731
 732 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
 733
 734         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
 735
 736 2017-05-01  Michael Clark  <michaeljclark@mac.com>
 737
 738         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
 739         register.
 740
 741 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
 742
 743         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
 744         and branches and not synthetic data instructions.
 745
 746 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
 747
 748         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
 749
 750 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 751
 752         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
 753         * arc-opc.c (insert_r13el): New function.
 754         (R13_EL): Define.
 755         * arc-tbl.h: Add new enter/leave variants.
 756
 757 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 758
 759         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
 760
 761 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 762
 763         * mips-dis.c (print_mips_disassembler_options): Add
 764         `no-aliases'.
 765
 766 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
 767
 768         * mips16-opc.c (AL): New macro.
 769         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
 770         of "ld" and "lw" as aliases.
 771
 772 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
 773
 774         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
 775         arguments.
 776
 777 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
 778             Alan Modra  <amodra@gmail.com>
 779
 780         * ppc-opc.c (ELEV): Define.
 781         (vle_opcodes): Add se_rfgi and e_sc.
 782         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
 783         for E200Z4.
 784
 785 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 786
 787         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
 788
 789 2017-04-21  Nick Clifton  <nickc@redhat.com>
 790
 791         PR binutils/21380
 792         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
 793         LD3R and LD4R.
 794
 795 2017-04-13  Alan Modra  <amodra@gmail.com>
 796
 797         * epiphany-desc.c: Regenerate.
 798         * fr30-desc.c: Regenerate.
 799         * frv-desc.c: Regenerate.
 800         * ip2k-desc.c: Regenerate.
 801         * iq2000-desc.c: Regenerate.
 802         * lm32-desc.c: Regenerate.
 803         * m32c-desc.c: Regenerate.
 804         * m32r-desc.c: Regenerate.
 805         * mep-desc.c: Regenerate.
 806         * mt-desc.c: Regenerate.
 807         * or1k-desc.c: Regenerate.
 808         * xc16x-desc.c: Regenerate.
 809         * xstormy16-desc.c: Regenerate.
 810
 811 2017-04-11  Alan Modra  <amodra@gmail.com>
 812
 813         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
 814         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
 815         PPC_OPCODE_TMR for e6500.
 816         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
 817         (PPCVEC3): Define as PPC_OPCODE_POWER9.
 818         (PPCVSX2): Define as PPC_OPCODE_POWER8.
 819         (PPCVSX3): Define as PPC_OPCODE_POWER9.
 820         (PPCHTM): Define as PPC_OPCODE_POWER8.
 821         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
 822
 823 2017-04-10  Alan Modra  <amodra@gmail.com>
 824
 825         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
 826         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
 827         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
 828         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
 829
 830 2017-04-09  Pip Cet  <pipcet@gmail.com>
 831
 832         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
 833         appropriate floating-point precision directly.
 834
 835 2017-04-07  Alan Modra  <amodra@gmail.com>
 836
 837         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
 838         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
 839         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
 840         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
 841         vector instructions with E6500 not PPCVEC2.
 842
 843 2017-04-06  Pip Cet  <pipcet@gmail.com>
 844
 845         * Makefile.am: Add wasm32-dis.c.
 846         * configure.ac: Add wasm32-dis.c to wasm32 target.
 847         * disassemble.c: Add wasm32 disassembler code.
 848         * wasm32-dis.c: New file.
 849         * Makefile.in: Regenerate.
 850         * configure: Regenerate.
 851         * po/POTFILES.in: Regenerate.
 852         * po/opcodes.pot: Regenerate.
 853
 854 2017-04-05  Pedro Alves  <palves@redhat.com>
 855
 856         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
 857         * arm-dis.c (parse_arm_disassembler_options): Constify.
 858         * ppc-dis.c (powerpc_init_dialect): Constify local.
 859         * vax-dis.c (parse_disassembler_options): Constify.
 860
 861 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
 862
 863         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
 864         RISCV_GP_SYMBOL.
 865
 866 2017-03-30  Pip Cet  <pipcet@gmail.com>
 867
 868         * configure.ac: Add (empty) bfd_wasm32_arch target.
 869         * configure: Regenerate
 870         * po/opcodes.pot: Regenerate.
 871
 872 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
 873
 874         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
 875         OSA2015.
 876         * opcodes/sparc-opc.c (asi_table): New ASIs.
 877
 878 2017-03-29  Alan Modra  <amodra@gmail.com>
 879
 880         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
 881         "raw" option.
 882         (lookup_powerpc): Don't special case -1 dialect.  Handle
 883         PPC_OPCODE_RAW.
 884         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
 885         lookup_powerpc call, pass it on second.
 886
 887 2017-03-27  Alan Modra  <amodra@gmail.com>
 888
 889         PR 21303
 890         * ppc-dis.c (struct ppc_mopt): Comment.
 891         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 892
 893 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 894
 895         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 896         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 897         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 898         (insert_nps_misc_imm_offset): New function.
 899         (extract_nps_misc imm_offset): New function.
 900         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 901         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 902
 903 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 904
 905         * s390-mkopc.c (main): Remove vx2 check.
 906         * s390-opc.txt: Remove vx2 instruction flags.
 907
 908 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 909
 910         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 911         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 912         (insert_nps_imm_offset): New function.
 913         (extract_nps_imm_offset): New function.
 914         (insert_nps_imm_entry): New function.
 915         (extract_nps_imm_entry): New function.
 916
 917 2017-03-17  Alan Modra  <amodra@gmail.com>
 918
 919         PR 21248
 920         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 921         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 922         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 923
 924 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 925
 926         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 927         <c.andi>: Likewise.
 928         <c.addiw> Likewise.
 929
 930 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 931
 932         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 933
 934 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 935
 936         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 937         <srl> Likewise.
 938         <srai> Likewise.
 939         <sra> Likewise.
 940
 941 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 942
 943         * i386-gen.c (opcode_modifiers): Replace S with Load.
 944         * i386-opc.h (S): Removed.
 945         (Load): New.
 946         (i386_opcode_modifier): Replace s with load.
 947         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 948         and {evex}.  Replace S with Load.
 949         * i386-tbl.h: Regenerated.
 950
 951 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 952
 953         * i386-opc.tbl: Use CpuCET on rdsspq.
 954         * i386-tbl.h: Regenerated.
 955
 956 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 957
 958         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 959         <vsx>: Do not use PPC_OPCODE_VSX3;
 960
 961 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 962
 963         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 964
 965 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 966
 967         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 968         (MOD_0F1E_PREFIX_1): Likewise.
 969         (MOD_0F38F5_PREFIX_2): Likewise.
 970         (MOD_0F38F6_PREFIX_0): Likewise.
 971         (RM_0F1E_MOD_3_REG_7): Likewise.
 972         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 973         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 974         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 975         (PREFIX_0F1E): Likewise.
 976         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 977         (PREFIX_0F38F5): Likewise.
 978         (dis386_twobyte): Use PREFIX_0F1E.
 979         (reg_table): Add REG_0F1E_MOD_3.
 980         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 981         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 982         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 983         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 984         (three_byte_table): Use PREFIX_0F38F5.
 985         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 986         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 987         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 988         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 989         PREFIX_MOD_3_0F01_REG_5_RM_2.
 990         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 991         (cpu_flags): Add CpuCET.
 992         * i386-opc.h (CpuCET): New enum.
 993         (CpuUnused): Commented out.
 994         (i386_cpu_flags): Add cpucet.
 995         * i386-opc.tbl: Add Intel CET instructions.
 996         * i386-init.h: Regenerated.
 997         * i386-tbl.h: Likewise.
 998
 999 2017-03-06  Alan Modra  <amodra@gmail.com>
1000
1001         PR 21124
1002         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1003         (extract_raq, extract_ras, extract_rbx): New functions.
1004         (powerpc_operands): Use opposite corresponding insert function.
1005         (Q_MASK): Define.
1006         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1007         register restriction.
1008
1009 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1010
1011         * disassemble.c Include "safe-ctype.h".
1012         (disassemble_init_for_target): Handle s390 init.
1013         (remove_whitespace_and_extra_commas): New function.
1014         (disassembler_options_cmp): Likewise.
1015         * arm-dis.c: Include "libiberty.h".
1016         (NUM_ELEM): Delete.
1017         (regnames): Use long disassembler style names.
1018         Add force-thumb and no-force-thumb options.
1019         (NUM_ARM_REGNAMES): Rename from this...
1020         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1021         (get_arm_regname_num_options): Delete.
1022         (set_arm_regname_option): Likewise.
1023         (get_arm_regnames): Likewise.
1024         (parse_disassembler_options): Likewise.
1025         (parse_arm_disassembler_option): Rename from this...
1026         (parse_arm_disassembler_options): ...to this.  Make static.
1027         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1028         (print_insn): Use parse_arm_disassembler_options.
1029         (disassembler_options_arm): New function.
1030         (print_arm_disassembler_options): Handle updated regnames.
1031         * ppc-dis.c: Include "libiberty.h".
1032         (ppc_opts): Add "32" and "64" entries.
1033         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1034         (powerpc_init_dialect): Add break to switch statement.
1035         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1036         (disassembler_options_powerpc): New function.
1037         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1038         Remove printing of "32" and "64".
1039         * s390-dis.c: Include "libiberty.h".
1040         (init_flag): Remove unneeded variable.
1041         (struct s390_options_t): New structure type.
1042         (options): New structure.
1043         (init_disasm): Rename from this...
1044         (disassemble_init_s390): ...to this.  Add initializations for
1045         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1046         (print_insn_s390): Delete call to init_disasm.
1047         (disassembler_options_s390): New function.
1048         (print_s390_disassembler_options): Print using information from
1049         struct 'options'.
1050         * po/opcodes.pot: Regenerate.
1051
1052 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-dis.c (PCMPESTR_Fixup): New.
1055         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1056         (prefix_table): Use PCMPESTR_Fixup.
1057         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1058         PCMPESTR_Fixup.
1059         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1060         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1061         Split 64-bit and non-64-bit variants.
1062         * opcodes/i386-tbl.h: Re-generate.
1063
1064 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1065
1066         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1067         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1068         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1069         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1070         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1071         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1072         (OP_SVE_V_HSD): New macros.
1073         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1074         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1075         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1076         (aarch64_opcode_table): Add new SVE instructions.
1077         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1078         for rotation operands.  Add new SVE operands.
1079         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1080         (ins_sve_quad_index): Likewise.
1081         (ins_imm_rotate): Split into...
1082         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1083         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1084         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1085         functions.
1086         (aarch64_ins_sve_addr_ri_s4): New function.
1087         (aarch64_ins_sve_quad_index): Likewise.
1088         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1089         * aarch64-asm-2.c: Regenerate.
1090         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1091         (ext_sve_quad_index): Likewise.
1092         (ext_imm_rotate): Split into...
1093         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1094         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1095         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1096         functions.
1097         (aarch64_ext_sve_addr_ri_s4): New function.
1098         (aarch64_ext_sve_quad_index): Likewise.
1099         (aarch64_ext_sve_index): Allow quad indices.
1100         (do_misc_decoding): Likewise.
1101         * aarch64-dis-2.c: Regenerate.
1102         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1103         aarch64_field_kinds.
1104         (OPD_F_OD_MASK): Widen by one bit.
1105         (OPD_F_NO_ZR): Bump accordingly.
1106         (get_operand_field_width): New function.
1107         * aarch64-opc.c (fields): Add new SVE fields.
1108         (operand_general_constraint_met_p): Handle new SVE operands.
1109         (aarch64_print_operand): Likewise.
1110         * aarch64-opc-2.c: Regenerate.
1111
1112 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1113
1114         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1115         (aarch64_feature_compnum): ...this.
1116         (SIMD_V8_3): Replace with...
1117         (COMPNUM): ...this.
1118         (CNUM_INSN): New macro.
1119         (aarch64_opcode_table): Use it for the complex number instructions.
1120
1121 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1122
1123         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1124
1125 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1126
1127         Add support for associating SPARC ASIs with an architecture level.
1128         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1129         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1130         decoding of SPARC ASIs.
1131
1132 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1135         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1136
1137 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1138
1139         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1140         1 (instead of to itself). Correct typo.
1141
1142 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1143
1144         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1145         pseudoinstructions.
1146
1147 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1148
1149         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1150         (aarch64_sys_reg_supported_p): Handle them.
1151
1152 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1153
1154         * arc-opc.c (UIMM6_20R): Define.
1155         (SIMM12_20): Use above.
1156         (SIMM12_20R): Define.
1157         (SIMM3_5_S): Use above.
1158         (UIMM7_A32_11R_S): Define.
1159         (UIMM7_9_S): Use above.
1160         (UIMM3_13R_S): Define.
1161         (SIMM11_A32_7_S): Use above.
1162         (SIMM9_8R): Define.
1163         (UIMM10_A32_8_S): Use above.
1164         (UIMM8_8R_S): Define.
1165         (W6): Use above.
1166         (arc_relax_opcodes): Use all above defines.
1167
1168 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1169
1170         * arc-regs.h: Distinguish some of the registers different on
1171         ARC700 and HS38 cpus.
1172
1173 2017-02-14  Alan Modra  <amodra@gmail.com>
1174
1175         PR 21118
1176         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1177         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1178
1179 2017-02-11  Stafford Horne  <shorne@gmail.com>
1180             Alan Modra  <amodra@gmail.com>
1181
1182         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1183         Use insn_bytes_value and insn_int_value directly instead.  Don't
1184         free allocated memory until function exit.
1185
1186 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1187
1188         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1189
1190 2017-02-03  Nick Clifton  <nickc@redhat.com>
1191
1192         PR 21096
1193         * aarch64-opc.c (print_register_list): Ensure that the register
1194         list index will fir into the tb buffer.
1195         (print_register_offset_address): Likewise.
1196         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1197
1198 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1199
1200         PR 21056
1201         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1202         instructions when the previous fetch packet ends with a 32-bit
1203         instruction.
1204
1205 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1206
1207         * pru-opc.c: Remove vague reference to a future GDB port.
1208
1209 2017-01-20  Nick Clifton  <nickc@redhat.com>
1210
1211         * po/ga.po: Updated Irish translation.
1212
1213 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1214
1215         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1216
1217 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1218
1219         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1220         if FETCH_DATA returns 0.
1221         (m68k_scan_mask): Likewise.
1222         (print_insn_m68k): Update code to handle -1 return value.
1223
1224 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1225
1226         * m68k-dis.c (enum print_insn_arg_error): New.
1227         (NEXTBYTE): Replace -3 with
1228         PRINT_INSN_ARG_MEMORY_ERROR.
1229         (NEXTULONG): Likewise.
1230         (NEXTSINGLE): Likewise.
1231         (NEXTDOUBLE): Likewise.
1232         (NEXTDOUBLE): Likewise.
1233         (NEXTPACKED): Likewise.
1234         (FETCH_ARG): Likewise.
1235         (FETCH_DATA): Update comments.
1236         (print_insn_arg): Update comments. Replace magic numbers with
1237         enum.
1238         (match_insn_m68k): Likewise.
1239
1240 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1241
1242         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1243         * i386-dis-evex.h (evex_table): Updated.
1244         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1245         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1246         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1247         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1248         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1249         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1250         * i386-init.h: Regenerate.
1251         * i386-tbl.h: Ditto.
1252
1253 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1254
1255         * msp430-dis.c (msp430_singleoperand): Return -1 if
1256         msp430dis_opcode_signed returns false.
1257         (msp430_doubleoperand): Likewise.
1258         (msp430_branchinstr): Return -1 if
1259         msp430dis_opcode_unsigned returns false.
1260         (msp430x_calla_instr): Likewise.
1261         (print_insn_msp430): Likewise.
1262
1263 2017-01-05  Nick Clifton  <nickc@redhat.com>
1264
1265         PR 20946
1266         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1267         could not be matched.
1268         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1269         NULL.
1270
1271 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1272
1273         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1274         (aarch64_opcode_table): Use RCPC_INSN.
1275
1276 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1277
1278         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1279         extension.
1280         * riscv-opcodes/all-opcodes: Likewise.
1281
1282 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1283
1284         * riscv-dis.c (print_insn_args): Add fall through comment.
1285
1286 2017-01-03  Nick Clifton  <nickc@redhat.com>
1287
1288         * po/sr.po: New Serbian translation.
1289         * configure.ac (ALL_LINGUAS): Add sr.
1290         * configure: Regenerate.
1291
1292 2017-01-02  Alan Modra  <amodra@gmail.com>
1293
1294         * epiphany-desc.h: Regenerate.
1295         * epiphany-opc.h: Regenerate.
1296         * fr30-desc.h: Regenerate.
1297         * fr30-opc.h: Regenerate.
1298         * frv-desc.h: Regenerate.
1299         * frv-opc.h: Regenerate.
1300         * ip2k-desc.h: Regenerate.
1301         * ip2k-opc.h: Regenerate.
1302         * iq2000-desc.h: Regenerate.
1303         * iq2000-opc.h: Regenerate.
1304         * lm32-desc.h: Regenerate.
1305         * lm32-opc.h: Regenerate.
1306         * m32c-desc.h: Regenerate.
1307         * m32c-opc.h: Regenerate.
1308         * m32r-desc.h: Regenerate.
1309         * m32r-opc.h: Regenerate.
1310         * mep-desc.h: Regenerate.
1311         * mep-opc.h: Regenerate.
1312         * mt-desc.h: Regenerate.
1313         * mt-opc.h: Regenerate.
1314         * or1k-desc.h: Regenerate.
1315         * or1k-opc.h: Regenerate.
1316         * xc16x-desc.h: Regenerate.
1317         * xc16x-opc.h: Regenerate.
1318         * xstormy16-desc.h: Regenerate.
1319         * xstormy16-opc.h: Regenerate.
1320
1321 2017-01-02  Alan Modra  <amodra@gmail.com>
1322
1323         Update year range in copyright notice of all files.
1324
1325 For older changes see ChangeLog-2016
1326 \f
1327 Copyright (C) 2017 Free Software Foundation, Inc.
1328
1329 Copying and distribution of this file, with or without modification,
1330 are permitted in any medium without royalty provided the copyright
1331 notice and this notice are preserved.
1332
1333 Local Variables:
1334 mode: change-log
1335 left-margin: 8
1336 fill-column: 74
1337 version-control: never
1338 End: