opcodes/ChangeLog

   1 2013-05-09  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (extract_vlesi): Properly sign extend.
   4         (extract_vlensi): Likewise.  Comment reason for setting invalid.
   5
   6 2013-05-02  Nick Clifton  <nickc@redhat.com>
   7
   8         * msp430-dis.c: Add support for MSP430X instructions.
   9
  10 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
  11
  12         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
  13         to "eccinj".
  14
  15 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
  16
  17         PR binutils/15369
  18         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
  19         of CGEN_CPU_ENDIAN.
  20         (hash_insns_list): Likewise.
  21
  22 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
  23
  24         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
  25         warning workaround.
  26
  27 2013-04-08  Jan Beulich <jbeulich@suse.com>
  28
  29         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
  30         * i386-tbl.h: Re-generate.
  31
  32 2013-04-06  David S. Miller  <davem@davemloft.net>
  33
  34         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
  35         of an opcode, prefer the one with F_PREFERRED set.
  36         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
  37         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
  38         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
  39         mark existing mnenomics as aliases.  Add "cc" suffix to edge
  40         instructions generating condition codes, mark existing mnenomics
  41         as aliases.  Add "fp" prefix to VIS compare instructions, mark
  42         existing mnenomics as aliases.
  43
  44 2013-04-03  Nick Clifton  <nickc@redhat.com>
  45
  46         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
  47         destination address by subtracting the operand from the current
  48         address.
  49         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
  50         a positive value in the insn.
  51         (extract_u16_loop): Do not negate the returned value.
  52         (D16_LOOP): Add V850_INVERSE_PCREL flag.
  53
  54         (ceilf.sw): Remove duplicate entry.
  55         (cvtf.hs): New entry.
  56         (cvtf.sh): Likewise.
  57         (fmaf.s): Likewise.
  58         (fmsf.s): Likewise.
  59         (fnmaf.s): Likewise.
  60         (fnmsf.s): Likewise.
  61         (maddf.s): Restrict to E3V5 architectures.
  62         (msubf.s): Likewise.
  63         (nmaddf.s): Likewise.
  64         (nmsubf.s): Likewise.
  65
  66 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
  67
  68         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
  69         check address mode.
  70         (print_insn): Pass sizeflag to get_sib.
  71
  72 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  73
  74         PR binutils/15068
  75         * tic6x-dis.c: Add support for displaying 16-bit insns.
  76
  77 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  78
  79         PR gas/15095
  80         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
  81         individual msb and lsb halves in src1 & src2 fields.  Discard the
  82         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
  83         follow what Ti SDK does in that case as any value in the src1
  84         field yields the same output with SDK disassembler.
  85
  86 2013-03-12  Michael Eager <eager@eagercon.com>
  87
  88         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
  89
  90 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  91
  92         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
  93
  94 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  95
  96         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
  97
  98 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  99
 100         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 101
 102 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 103
 104         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 105         (thumb32_opcodes): Likewise.
 106         (print_insn_thumb32): Handle 'S' control char.
 107
 108 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 109
 110         * lm32-desc.c: Regenerate.
 111
 112 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * i386-reg.tbl (riz): Add RegRex64.
 115         * i386-tbl.h: Regenerated.
 116
 117 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 118
 119         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 120         (aarch64_feature_crc): New static.
 121         (CRC): New macro.
 122         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 123         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 124         * aarch64-asm-2.c: Re-generate.
 125         * aarch64-dis-2.c: Ditto.
 126         * aarch64-opc-2.c: Ditto.
 127
 128 2013-02-27  Alan Modra  <amodra@gmail.com>
 129
 130         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 131         * rl78-decode.c: Regenerate.
 132
 133 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 134
 135         * rl78-decode.opc: Fix encoding of DIVWU insn.
 136         * rl78-decode.c: Regenerate.
 137
 138 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 139
 140         PR gas/15159
 141         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 142
 143         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 144         (cpu_flags): Add CpuSMAP.
 145
 146         * i386-opc.h (CpuSMAP): New.
 147         (i386_cpu_flags): Add cpusmap.
 148
 149         * i386-opc.tbl: Add clac and stac.
 150
 151         * i386-init.h: Regenerated.
 152         * i386-tbl.h: Likewise.
 153
 154 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 155
 156         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 157         which also makes the disassembler output be in little
 158         endian like it should be.
 159
 160 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 161
 162         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 163         fields to NULL.
 164         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 165
 166 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 167
 168         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 169         section disassembled.
 170
 171 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 172
 173         * arm-dis.c: Update strht pattern.
 174
 175 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 176
 177         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 178         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 179         trunc.w.s macro for EE.
 180
 181 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 182             Andrew Jenner <andrew@codesourcery.com>
 183
 184         Based on patches from Altera Corporation.
 185
 186         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 187         nios2-opc.c.
 188         * Makefile.in: Regenerated.
 189         * configure.in: Add case for bfd_nios2_arch.
 190         * configure: Regenerated.
 191         * disassemble.c (ARCH_nios2): Define.
 192         (disassembler): Add case for bfd_arch_nios2.
 193         * nios2-dis.c: New file.
 194         * nios2-opc.c: New file.
 195
 196 2013-02-04  Alan Modra  <amodra@gmail.com>
 197
 198         * po/POTFILES.in: Regenerate.
 199         * rl78-decode.c: Regenerate.
 200         * rx-decode.c: Regenerate.
 201
 202 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 203
 204         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 205         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 206         * aarch64-asm.c (convert_xtl_to_shll): New function.
 207         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 208         calling convert_xtl_to_shll.
 209         * aarch64-dis.c (convert_shll_to_xtl): New function.
 210         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 211         calling convert_shll_to_xtl.
 212         * aarch64-gen.c: Update copyright year.
 213         * aarch64-asm-2.c: Re-generate.
 214         * aarch64-dis-2.c: Re-generate.
 215         * aarch64-opc-2.c: Re-generate.
 216
 217 2013-01-24  Nick Clifton  <nickc@redhat.com>
 218
 219         * v850-dis.c: Add support for e3v5 architecture.
 220         * v850-opc.c: Likewise.
 221
 222 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 223
 224         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 225         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 226         * aarch64-opc.c (operand_general_constraint_met_p): For
 227         AARCH64_MOD_LSL, move the range check on the shift amount before the
 228         alignment check; change to call set_sft_amount_out_of_range_error
 229         instead of set_imm_out_of_range_error.
 230         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 231         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 232         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 233         SIMD_IMM_SFT.
 234
 235 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 238
 239         * i386-init.h: Regenerated.
 240         * i386-tbl.h: Likewise.
 241
 242 2013-01-15  Nick Clifton  <nickc@redhat.com>
 243
 244         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 245         values.
 246         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 247
 248 2013-01-14  Will Newton <will.newton@imgtec.com>
 249
 250         * metag-dis.c (REG_WIDTH): Increase to 64.
 251
 252 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 253
 254         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 255         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 256         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 257         (SH6): Update.
 258         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 259         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 260         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 261         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 262
 263 2013-01-10  Will Newton <will.newton@imgtec.com>
 264
 265         * Makefile.am: Add Meta.
 266         * configure.in: Add Meta.
 267         * disassemble.c: Add Meta support.
 268         * metag-dis.c: New file.
 269         * Makefile.in: Regenerate.
 270         * configure: Regenerate.
 271
 272 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 273
 274         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 275         (match_opcode): Rename to cr16_match_opcode.
 276
 277 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 278
 279         * mips-dis.c: Add names for CP0 registers of r5900.
 280         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 281         instructions sq and lq.
 282         Add support for MIPS r5900 CPU.
 283         Add support for 128 bit MMI (Multimedia Instructions).
 284         Add support for EE instructions (Emotion Engine).
 285         Disable unsupported floating point instructions (64 bit and
 286         undefined compare operations).
 287         Enable instructions of MIPS ISA IV which are supported by r5900.
 288         Disable 64 bit co processor instructions.
 289         Disable 64 bit multiplication and division instructions.
 290         Disable instructions for co-processor 2 and 3, because these are
 291         not supported (preparation for later VU0 support (Vector Unit)).
 292         Disable cvt.w.s because this behaves like trunc.w.s and the
 293         correct execution can't be ensured on r5900.
 294         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 295         will confuse less developers and compilers.
 296
 297 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 298
 299         * aarch64-opc.c (aarch64_print_operand): Change to print
 300         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 301         in comment.
 302         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 303         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 304         OP_MOV_IMM_WIDE.
 305
 306 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 307
 308         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 309         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 310
 311 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 312
 313         * i386-gen.c (process_copyright): Update copyright year to 2013.
 314
 315 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 316
 317         * cr16-dis.c (match_opcode,make_instruction): Remove static
 318         declaration.
 319         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 320         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 321
 322 For older changes see ChangeLog-2012
 323 \f
 324 Copyright (C) 2013 Free Software Foundation, Inc.
 325
 326 Copying and distribution of this file, with or without modification,
 327 are permitted in any medium without royalty provided the copyright
 328 notice and this notice are preserved.
 329
 330 Local Variables:
 331 mode: change-log
 332 left-margin: 8
 333 fill-column: 74
 334 version-control: never
 335 End: