1 2011-11-16 Maciej W. Rozycki <macro@codesourcery.com>
3 * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
6 2011-11-02 Nick Clifton <nickc@redhat.com>
8 * po/it.po: New Italian translation.
9 * configure.in (ALL_LINGUAS): Add it.
10 * configure: Regenerate.
11 * po/opcodes.pot: Regenerate.
13 2011-11-01 DJ Delorie <dj@redhat.com>
15 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
17 (MAINTAINERCLEANFILES): Add rl78-decode.c.
18 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
19 * Makefile.in: Regenerate.
20 * configure.in: Add bfd_rl78_arch case.
21 * configure: Regenerate.
22 * disassemble.c: Define ARCH_rl78.
23 (disassembler): Add ARCH_rl78 case.
24 * rl78-decode.c: New file.
25 * rl78-decode.opc: New file.
26 * rl78-dis.c: New file.
28 2011-10-27 Peter Bergner <bergner@vnet.ibm.com>
30 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
31 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
32 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
35 2011-10-26 Nick Clifton <nickc@redhat.com>
38 * i386-dis.c (print_insn): Fix testing of array subscript.
40 2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
42 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
43 * epiphany-asm.c, epiphany-opc.h: Regenerate.
45 2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
47 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
48 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
49 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
50 (CLEANFILES): Add stamp-epiphany.
51 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
52 (stamp-epiphany): New rule.
53 * configure.in: Handle bfd_epiphany_arch.
54 * disassemble.c (ARCH_epiphany): Define.
55 (disassembler): Handle bfd_arch_epiphany.
56 * epiphany-asm.c: New file.
57 * epiphany-desc.c: New file.
58 * epiphany-desc.h: New file.
59 * epiphany-dis.c: New file.
60 * epiphany-ibld.c: New file.
61 * epiphany-opc.c: New file.
62 * epiphany-opc.h: New file.
63 * Makefile.in: Regenerate.
64 * configure: Regenerate.
65 * po/POTFILES.in: Regenerate.
66 * po/opcodes.pot: Regenerate.
68 2011-10-24 Julian Brown <julian@codesourcery.com>
70 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
72 2011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
74 * s390-opc.txt: Add CPUMF instructions.
76 2011-10-18 Jie Zhang <jie@codesourcery.com>
77 Julian Brown <julian@codesourcery.com>
79 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
81 2011-10-10 Nick Clifton <nickc@redhat.com>
83 * po/es.po: Updated Spanish translation.
84 * po/fi.po: Updated Finnish translation.
86 2011-09-28 Jan Beulich <jbeulich@suse.com>
88 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
90 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
91 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
92 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
93 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
94 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
95 on DFP quad instructions.
97 2011-09-27 David S. Miller <davem@davemloft.net>
99 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
100 to a float instead of an integer register.
102 2011-09-26 David S. Miller <davem@davemloft.net>
104 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
107 2011-09-21 David S. Miller <davem@davemloft.net>
109 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
110 bits. Fix "fchksm16" mnemonic.
112 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
114 The changes below bring 'mov' and 'ticc' instructions into line
115 with the V8 SPARC Architecture Manual.
116 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
117 * sparc-opc.c (sparc_opcodes): Add alias entries for
118 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
119 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
120 * sparc-opc.c (sparc_opcodes): Move/Change entries for
121 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
123 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
126 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
127 This has been reported as being accepted by the Sun assmebler.
129 2011-09-08 David S. Miller <davem@davemloft.net>
131 * sparc-opc.c (pdistn): Destination is integer not float register.
133 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
136 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
138 2011-08-26 Nick Clifton <nickc@redhat.com>
140 * po/es.po: Updated Spanish translation.
142 2011-08-22 Nick Clifton <nickc@redhat.com>
144 * Makefile.am (CPUDIR): Redfine to point to top level cpu
146 (stamp-frv): Use CPUDIR.
147 (stamp-iq2000): Likewise.
148 (stamp-lm32): Likewise.
149 (stamp-m32c): Likewise.
150 (stamp-mt): Likewise.
151 (stamp-xc16x): Likewise.
152 * Makefile.in: Regenerate.
154 2011-08-09 Chao-ying Fu <fu@mips.com>
155 Maciej W. Rozycki <macro@codesourcery.com>
157 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
159 (print_insn_args, print_insn_micromips): Handle MCU.
160 * micromips-opc.c (MC): New macro.
161 (micromips_opcodes): Add "aclr", "aset" and "iret".
162 * mips-opc.c (MC): New macro.
163 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
165 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
167 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
168 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
169 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
170 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
171 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
172 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
173 (WR_s): Update macro.
174 (micromips_opcodes): Update register use flags of: "addiu",
175 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
176 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
177 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
178 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
179 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
180 "swm" and "xor" instructions.
182 2011-08-05 David S. Miller <davem@davemloft.net>
184 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
186 (print_insn_sparc): Handle '4', '5', and '(' format codes.
187 Accept %asr numbers below 28.
188 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
191 2011-08-02 Quentin Neill <quentin.neill@amd.com>
193 * i386-dis.c (xop_table): Remove spurious bextr insn.
195 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
198 * i386-dis.c (print_insn): Optimize info->mach check.
200 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
203 * i386-opc.tbl: Add Disp32S to 64bit call.
204 * i386-tbl.h: Regenerated.
206 2011-07-24 Chao-ying Fu <fu@mips.com>
207 Maciej W. Rozycki <macro@codesourcery.com>
209 * micromips-opc.c: New file.
210 * mips-dis.c (micromips_to_32_reg_b_map): New array.
211 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
212 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
213 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
214 (micromips_to_32_reg_q_map): Likewise.
215 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
216 (micromips_ase): New variable.
217 (is_micromips): New function.
218 (set_default_mips_dis_options): Handle microMIPS ASE.
219 (print_insn_micromips): New function.
220 (is_compressed_mode_p): Likewise.
221 (_print_insn_mips): Handle microMIPS instructions.
222 * Makefile.am (CFILES): Add micromips-opc.c.
223 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
224 * Makefile.in: Regenerate.
225 * configure: Regenerate.
227 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
228 (micromips_to_32_reg_i_map): Likewise.
229 (micromips_to_32_reg_m_map): Likewise.
230 (micromips_to_32_reg_n_map): New macro.
232 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
234 * mips-opc.c (NODS): New macro.
235 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
236 (DSP_VOLA): Likewise.
237 (mips_builtin_opcodes): Add NODS annotation to "deret" and
238 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
239 place of TRAP for "wait", "waiti" and "yield".
240 * mips16-opc.c (NODS): New macro.
241 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
242 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
243 "restore" and "save".
245 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
247 * configure.in: Handle bfd_k1om_arch.
248 * configure: Regenerated.
250 * disassemble.c (disassembler): Handle bfd_k1om_arch.
252 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
253 bfd_mach_k1om_intel_syntax.
255 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
256 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
257 (cpu_flags): Add CpuK1OM.
259 * i386-opc.h (CpuK1OM): New.
260 (i386_cpu_flags): Add cpuk1om.
262 * i386-init.h: Regenerated.
263 * i386-tbl.h: Likewise.
265 2011-07-12 Nick Clifton <nickc@redhat.com>
267 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
270 2011-07-01 Nick Clifton <nickc@redhat.com>
273 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
274 insns using post-increment addressing.
276 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
278 * i386-dis.c (vex_len_table): Update rorxS.
280 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
282 AVX Programming Reference (June, 2011)
283 * i386-dis.c (vex_len_table): Correct rorxS.
285 * i386-opc.tbl: Correct rorx.
286 * i386-tbl.h: Regenerated.
288 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
290 * tilegx-opc.c (find_opcode): Replace "index" with "i".
291 * tilepro-opc.c (find_opcode): Likewise.
293 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
295 * mips16-opc.c (jalrc, jrc): Move earlier in file.
297 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
299 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
302 2011-06-17 Andreas Schwab <schwab@redhat.com>
304 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
305 (MOSTLYCLEANFILES): ... here.
306 * Makefile.in: Regenerate.
308 2011-06-14 Alan Modra <amodra@gmail.com>
310 * Makefile.in: Regenerate.
312 2011-06-13 Walter Lee <walt@tilera.com>
314 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
315 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
316 * Makefile.in: Regenerate.
317 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
318 * configure: Regenerate.
319 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
320 * po/POTFILES.in: Regenerate.
321 * tilegx-dis.c: New file.
322 * tilegx-opc.c: New file.
323 * tilepro-dis.c: New file.
324 * tilepro-opc.c: New file.
326 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
328 AVX Programming Reference (June, 2011)
329 * i386-dis.c (XMGatherQ): New.
330 * i386-dis.c (EXxmm_mb): New.
331 (EXxmm_mb): Likewise.
332 (EXxmm_mw): Likewise.
333 (EXxmm_md): Likewise.
334 (EXxmm_mq): Likewise.
337 (VexGatherQ): Likewise.
338 (MVexVSIBDWpX): Likewise.
339 (MVexVSIBQWpX): Likewise.
340 (xmm_mb_mode): Likewise.
341 (xmm_mw_mode): Likewise.
342 (xmm_md_mode): Likewise.
343 (xmm_mq_mode): Likewise.
344 (xmmdw_mode): Likewise.
345 (xmmqd_mode): Likewise.
346 (ymmxmm_mode): Likewise.
347 (vex_vsib_d_w_dq_mode): Likewise.
348 (vex_vsib_q_w_dq_mode): Likewise.
349 (MOD_VEX_0F385A_PREFIX_2): Likewise.
350 (MOD_VEX_0F388C_PREFIX_2): Likewise.
351 (MOD_VEX_0F388E_PREFIX_2): Likewise.
352 (PREFIX_0F3882): Likewise.
353 (PREFIX_VEX_0F3816): Likewise.
354 (PREFIX_VEX_0F3836): Likewise.
355 (PREFIX_VEX_0F3845): Likewise.
356 (PREFIX_VEX_0F3846): Likewise.
357 (PREFIX_VEX_0F3847): Likewise.
358 (PREFIX_VEX_0F3858): Likewise.
359 (PREFIX_VEX_0F3859): Likewise.
360 (PREFIX_VEX_0F385A): Likewise.
361 (PREFIX_VEX_0F3878): Likewise.
362 (PREFIX_VEX_0F3879): Likewise.
363 (PREFIX_VEX_0F388C): Likewise.
364 (PREFIX_VEX_0F388E): Likewise.
365 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
366 (PREFIX_VEX_0F38F5): Likewise.
367 (PREFIX_VEX_0F38F6): Likewise.
368 (PREFIX_VEX_0F3A00): Likewise.
369 (PREFIX_VEX_0F3A01): Likewise.
370 (PREFIX_VEX_0F3A02): Likewise.
371 (PREFIX_VEX_0F3A38): Likewise.
372 (PREFIX_VEX_0F3A39): Likewise.
373 (PREFIX_VEX_0F3A46): Likewise.
374 (PREFIX_VEX_0F3AF0): Likewise.
375 (VEX_LEN_0F3816_P_2): Likewise.
376 (VEX_LEN_0F3819_P_2): Likewise.
377 (VEX_LEN_0F3836_P_2): Likewise.
378 (VEX_LEN_0F385A_P_2_M_0): Likewise.
379 (VEX_LEN_0F38F5_P_0): Likewise.
380 (VEX_LEN_0F38F5_P_1): Likewise.
381 (VEX_LEN_0F38F5_P_3): Likewise.
382 (VEX_LEN_0F38F6_P_3): Likewise.
383 (VEX_LEN_0F38F7_P_1): Likewise.
384 (VEX_LEN_0F38F7_P_2): Likewise.
385 (VEX_LEN_0F38F7_P_3): Likewise.
386 (VEX_LEN_0F3A00_P_2): Likewise.
387 (VEX_LEN_0F3A01_P_2): Likewise.
388 (VEX_LEN_0F3A38_P_2): Likewise.
389 (VEX_LEN_0F3A39_P_2): Likewise.
390 (VEX_LEN_0F3A46_P_2): Likewise.
391 (VEX_LEN_0F3AF0_P_3): Likewise.
392 (VEX_W_0F3816_P_2): Likewise.
393 (VEX_W_0F3818_P_2): Likewise.
394 (VEX_W_0F3819_P_2): Likewise.
395 (VEX_W_0F3836_P_2): Likewise.
396 (VEX_W_0F3846_P_2): Likewise.
397 (VEX_W_0F3858_P_2): Likewise.
398 (VEX_W_0F3859_P_2): Likewise.
399 (VEX_W_0F385A_P_2_M_0): Likewise.
400 (VEX_W_0F3878_P_2): Likewise.
401 (VEX_W_0F3879_P_2): Likewise.
402 (VEX_W_0F3A00_P_2): Likewise.
403 (VEX_W_0F3A01_P_2): Likewise.
404 (VEX_W_0F3A02_P_2): Likewise.
405 (VEX_W_0F3A38_P_2): Likewise.
406 (VEX_W_0F3A39_P_2): Likewise.
407 (VEX_W_0F3A46_P_2): Likewise.
408 (MOD_VEX_0F3818_PREFIX_2): Removed.
409 (MOD_VEX_0F3819_PREFIX_2): Likewise.
410 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
411 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
412 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
413 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
414 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
415 (VEX_LEN_0F3A0E_P_2): Likewise.
416 (VEX_LEN_0F3A0F_P_2): Likewise.
417 (VEX_LEN_0F3A42_P_2): Likewise.
418 (VEX_LEN_0F3A4C_P_2): Likewise.
419 (VEX_W_0F3818_P_2_M_0): Likewise.
420 (VEX_W_0F3819_P_2_M_0): Likewise.
421 (prefix_table): Updated.
422 (three_byte_table): Likewise.
423 (vex_table): Likewise.
424 (vex_len_table): Likewise.
425 (vex_w_table): Likewise.
426 (mod_table): Likewise.
427 (putop): Handle "LW".
428 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
429 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
430 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
432 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
433 vex_vsib_q_w_dq_mode.
434 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
437 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
438 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
439 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
440 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
441 (opcode_modifiers): Add VecSIB.
443 * i386-opc.h (CpuAVX2): New.
445 (CpuLZCNT): Likewise.
446 (CpuINVPCID): Likewise.
447 (VecSIB128): Likewise.
448 (VecSIB256): Likewise.
450 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
451 (i386_opcode_modifier): Add vecsib.
453 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
454 * i386-init.h: Regenerated.
455 * i386-tbl.h: Likewise.
457 2011-06-03 Quentin Neill <quentin.neill@amd.com>
459 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
460 * i386-init.h: Regenerated.
462 2011-06-03 Nick Clifton <nickc@redhat.com>
465 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
466 computing address offsets.
467 (print_arm_address): Likewise.
468 (print_insn_arm): Likewise.
469 (print_insn_thumb16): Likewise.
470 (print_insn_thumb32): Likewise.
472 2011-06-02 Jie Zhang <jie@codesourcery.com>
473 Nathan Sidwell <nathan@codesourcery.com>
474 Maciej Rozycki <macro@codesourcery.com>
476 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
478 (print_arm_address): Likewise. Elide positive #0 appropriately.
479 (print_insn_arm): Likewise.
481 2011-06-02 Nick Clifton <nickc@redhat.com>
484 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
485 passed to print_address_func.
487 2011-06-02 Nick Clifton <nickc@redhat.com>
489 * arm-dis.c: Fix spelling mistakes.
490 * op/opcodes.pot: Regenerate.
492 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
494 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
495 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
496 * s390-opc.txt: Fix cxr instruction type.
498 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
500 * s390-opc.c: Add new instruction types marking register pair
502 * s390-opc.txt: Match instructions having register pair operands
503 to the new instruction types.
505 2011-05-19 Nick Clifton <nickc@redhat.com>
507 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
510 2011-05-10 Quentin Neill <quentin.neill@amd.com>
512 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
513 * i386-init.h: Regenerated.
515 2011-04-27 Nick Clifton <nickc@redhat.com>
517 * po/da.po: Updated Danish translation.
519 2011-04-26 Anton Blanchard <anton@samba.org>
521 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
523 2011-04-21 DJ Delorie <dj@redhat.com>
525 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
526 * rx-decode.c: Regenerate.
528 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-init.h: Regenerated.
532 2011-04-19 Quentin Neill <quentin.neill@amd.com>
534 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
537 2011-04-13 Nick Clifton <nickc@redhat.com>
539 * v850-dis.c (disassemble): Always print a closing square brace if
540 an opening square brace was printed.
542 2011-04-12 Nick Clifton <nickc@redhat.com>
545 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
547 (print_insn_thumb32): Handle %L.
549 2011-04-11 Julian Brown <julian@codesourcery.com>
551 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
552 (print_insn_thumb32): Add APSR bitmask support.
554 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
556 * arm-dis.c (print_insn): init vars moved into private_data structure.
558 2011-03-24 Mike Frysinger <vapier@gentoo.org>
560 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
562 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
564 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
565 post-increment to support LPM Z+ instruction. Add support for 'E'
566 constraint for DES instruction.
567 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
569 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
571 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
573 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
575 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
576 Use branch types instead.
577 (print_insn): Likewise.
579 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
581 * mips-opc.c (mips_builtin_opcodes): Correct register use
582 annotation of "alnv.ps".
584 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
586 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
588 2011-02-22 Mike Frysinger <vapier@gentoo.org>
590 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
592 2011-02-22 Mike Frysinger <vapier@gentoo.org>
594 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
596 2011-02-19 Mike Frysinger <vapier@gentoo.org>
598 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
599 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
600 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
601 exception, end_of_registers, msize, memory, bfd_mach.
602 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
603 LB0REG, LC1REG, LT1REG, LB1REG): Delete
604 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
605 (get_allreg): Change to new defines. Fallback to abort().
607 2011-02-14 Mike Frysinger <vapier@gentoo.org>
609 * bfin-dis.c: Add whitespace/parenthesis where needed.
611 2011-02-14 Mike Frysinger <vapier@gentoo.org>
613 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
616 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
618 * configure: Regenerate.
620 2011-02-13 Mike Frysinger <vapier@gentoo.org>
622 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
624 2011-02-13 Mike Frysinger <vapier@gentoo.org>
626 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
627 dregs only when P is set, and dregs_lo otherwise.
629 2011-02-13 Mike Frysinger <vapier@gentoo.org>
631 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
633 2011-02-12 Mike Frysinger <vapier@gentoo.org>
635 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
637 2011-02-12 Mike Frysinger <vapier@gentoo.org>
639 * bfin-dis.c (machine_registers): Delete REG_GP.
640 (reg_names): Delete "GP".
641 (decode_allregs): Change REG_GP to REG_LASTREG.
643 2011-02-12 Mike Frysinger <vapier@gentoo.org>
645 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
648 2011-02-11 Mike Frysinger <vapier@gentoo.org>
650 * bfin-dis.c (reg_names): Add const.
651 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
652 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
653 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
654 decode_counters, decode_allregs): Likewise.
656 2011-02-09 Michael Snyder <msnyder@vmware.com>
658 * i386-dis.c (OP_J): Parenthesize expression to prevent
660 (print_insn): Fix indentation off-by-one.
662 2011-02-01 Nick Clifton <nickc@redhat.com>
664 * po/da.po: Updated Danish translation.
666 2011-01-21 Dave Murphy <davem@devkitpro.org>
668 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
670 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
672 * i386-dis.c (sIbT): New.
673 (b_T_mode): Likewise.
674 (dis386): Replace sIb with sIbT on "pushT".
675 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
676 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
678 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
680 * i386-init.h: Regenerated.
681 * i386-tbl.h: Regenerated
683 2011-01-17 Quentin Neill <quentin.neill@amd.com>
685 * i386-dis.c (REG_XOP_TBM_01): New.
686 (REG_XOP_TBM_02): New.
687 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
688 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
689 entries, and add bextr instruction.
691 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
692 (cpu_flags): Add CpuTBM.
694 * i386-opc.h (CpuTBM) New.
695 (i386_cpu_flags): Add bit cputbm.
697 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
698 blcs, blsfill, blsic, t1mskc, and tzmsk.
700 2011-01-12 DJ Delorie <dj@redhat.com>
702 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
704 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
706 * mips-dis.c (print_insn_args): Adjust the value to print the real
707 offset for "+c" argument.
709 2011-01-10 Nick Clifton <nickc@redhat.com>
711 * po/da.po: Updated Danish translation.
713 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
715 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
717 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
719 * i386-dis.c (REG_VEX_38F3): New.
720 (PREFIX_0FBC): Likewise.
721 (PREFIX_VEX_38F2): Likewise.
722 (PREFIX_VEX_38F3_REG_1): Likewise.
723 (PREFIX_VEX_38F3_REG_2): Likewise.
724 (PREFIX_VEX_38F3_REG_3): Likewise.
725 (PREFIX_VEX_38F7): Likewise.
726 (VEX_LEN_38F2_P_0): Likewise.
727 (VEX_LEN_38F3_R_1_P_0): Likewise.
728 (VEX_LEN_38F3_R_2_P_0): Likewise.
729 (VEX_LEN_38F3_R_3_P_0): Likewise.
730 (VEX_LEN_38F7_P_0): Likewise.
731 (dis386_twobyte): Use PREFIX_0FBC.
732 (reg_table): Add REG_VEX_38F3.
733 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
734 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
735 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
736 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
738 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
739 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
742 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
743 (cpu_flags): Add CpuBMI.
745 * i386-opc.h (CpuBMI): New.
746 (i386_cpu_flags): Add cpubmi.
748 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
749 * i386-init.h: Regenerated.
750 * i386-tbl.h: Likewise.
752 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
754 * i386-dis.c (VexGdq): New.
755 (OP_VEX): Handle dq_mode.
757 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
759 * i386-gen.c (process_copyright): Update copyright to 2011.
761 For older changes see ChangeLog-2010
767 version-control: never