opcodes/ChangeLog

   1 2017-11-29  Stefan Stroe  <stroestefan@gmail.com>
   2
   3         * po/Make-in (datadir): Define as @datadir@.
   4         (localedir): Define as @localedir@.
   5         (gnulocaledir, gettextsrcdir): Use @datarootdir@.
   6
   7 2017-11-27  Nick Clifton  <nickc@redhat.com>
   8
   9         * po/zh_CN.po: Updated simplified Chinese translation.
  10
  11 2017-11-24  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
  14         "df" groups.
  15
  16 2017-11-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  17
  18         * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
  19         * i386-tbl.h: Regenerate.
  20
  21 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
  24         the 16-bit addressing case.
  25
  26 2017-11-23  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
  29         (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
  30         * i386-opc.tbl (ud1, ud2b): Add operands.
  31         (ud0): New.
  32         * i386-tbl.h: Re-generate.
  33
  34 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  35
  36         * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
  37         * i386-tbl.h: Regenerate.
  38
  39 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  40
  41         * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
  42         * i386-tbl.h: Regenerate.
  43
  44 2017-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
  45
  46         *arc-opc (insert_rhv2): Check h-regs range.
  47
  48 2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
  49
  50         * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
  51         * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
  52
  53 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  54
  55         * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
  56         and AARCH64_FEATURE_F16.
  57
  58 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
  59
  60         * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
  61         (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
  62         (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
  63         (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
  64         (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
  65         (ldapur, ldapursw, stlur): New.
  66         * aarch64-dis-2.c: Regenerate.
  67
  68 2017-11-16  Jan Beulich  <jbeulich@suse.com>
  69
  70         (get_valid_dis386): Never flag bad opcode when
  71         vex.register_specifier is beyond 7. Always store all four
  72         bits of it. Move 16-/32-bit override in EVEX handling after
  73         all to be overridden bits have been set.
  74         (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
  75         Use rex to determine GPR register set.
  76         (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
  77         OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
  78
  79 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
  82         determine GPR register set.
  83
  84 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
  87         (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
  88         (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
  89         pass.
  90         (OP_REG_VexI4): Drop low 4 bits check.
  91
  92 2017-11-15  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-reg.tbl (axl): Remove Acc and Byte.
  95         * i386-tbl.h: Re-generate.
  96
  97 2017-11-14  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
 100         (vex_len_table): Use VPCOM.
 101
 102 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
 105         (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
 106         * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
 107         vpcmpw): Move up.
 108         (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
 109         vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
 110         vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
 111         vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
 112         vpcmpnltuw): New.
 113         * i386-tbl.h: Re-generate.
 114
 115 2017-11-14  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
 118         smov, ssca, stos, ssto, xlat): Drop Disp*.
 119         * i386-tbl.h: Re-generate.
 120
 121 2017-11-13  Jan Beulich  <jbeulich@suse.com>
 122
 123         * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
 124         xsaveopt64): Add No_qSuf.
 125         * i386-tbl.h: Re-generate.
 126
 127 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 128
 129         * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
 130         dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
 131         cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
 132         sder32_el2, vncr_el2.
 133         (aarch64_sys_reg_supported_p): Likewise.
 134         (aarch64_pstatefields): Add dit register.
 135         (aarch64_pstatefield_supported_p): Likewise.
 136         (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
 137         vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
 138         vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
 139         rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
 140         rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
 141         ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
 142         rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
 143
 144 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 145
 146         * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
 147         (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
 148         (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
 149         (QL_STLW, QL_STLX): New.
 150
 151 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 152
 153         * aarch64-asm.h (ins_addr_offset): New.
 154         * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
 155         (aarch64_ins_addr_offset): New.
 156         * aarch64-asm-2.c: Regenerate.
 157         * aarch64-dis.h (ext_addr_offset): New.
 158         * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
 159         (aarch64_ext_addr_offset): New.
 160         * aarch64-dis-2.c: Regenerate.
 161         * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
 162         FLD_imm4_2 and FLD_SM3_imm2.
 163         * aarch64-opc.c (fields): Add FLD_imm6_2,
 164         FLD_imm4_2 and FLD_SM3_imm2.
 165         (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
 166         (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
 167         AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
 168         * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
 169         * aarch64-tbl.h
 170         (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 171
 172 2017-11-09 Tamar Christina  <tamar.christina@arm.com>
 173
 174         * aarch64-tbl.h
 175         (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
 176         (aarch64_feature_sm4, aarch64_feature_sha3): New.
 177         (aarch64_feature_fp_16_v8_2): New.
 178         (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
 179         (V8_4_INSN, CRYPTO_V8_2_INSN): New.
 180         (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 181
 182 2017-11-08  Tamar Christina  <tamar.christina@arm.com>
 183
 184         * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
 185         (aarch64_feature_sha2, aarch64_feature_aes): New.
 186         (SHA2, AES): New.
 187         (AES_INSN, SHA2_INSN): New.
 188         (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
 189         (sha1h, sha1su1, sha256su0, sha1c, sha1p,
 190          sha1m, sha1su0, sha256h, sha256h2, sha256su1):
 191         Change to SHA2_INS.
 192
 193 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
 194             Tamar Christina <tamar.christina@arm.com>
 195
 196         * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
 197         FP16 instructions, including vfmal.f16 and vfmsl.f16.
 198
 199 2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 200
 201         * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
 202
 203 2017-11-07  Alan Modra  <amodra@gmail.com>
 204
 205         * opintl.h: Formatting, comment fixes.
 206         (gettext, ngettext): Redefine when ENABLE_NLS.
 207         (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
 208         (_): Define using gettext.
 209         (textdomain, bindtextdomain): Use safer "do nothing".
 210
 211 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 212
 213         * arc-dis.c (print_hex): New variable.
 214         (parse_option): Check for hex option.
 215         (print_insn_arc): Use hexadecimal representation for short
 216         immediate values when requested.
 217         (print_arc_disassembler_options): Add hex option to the list.
 218
 219 2017-11-03  Claudiu Zissulescu  <claziss@synopsys.com>
 220
 221         * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
 222         (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
 223         (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
 224         (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
 225         (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
 226         (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
 227         (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
 228         (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
 229         (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
 230         (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
 231         (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
 232         (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
 233         (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
 234         (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
 235         (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
 236         (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
 237         (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
 238         (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
 239         (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
 240         Changed opcodes.
 241         (prealloc, prefetch*): Place them before ld instruction.
 242         * arc-opc.c (skip_this_opcode): Add ARITH class.
 243
 244 2017-10-25  Alan Modra  <amodra@gmail.com>
 245
 246         PR 22348
 247         * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
 248         (cr16_words, cr16_allWords, processing_argument_number): Likewise.
 249         (imm4flag, size_changed): Likewise.
 250         * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
 251         (words, allWords, processing_argument_number): Likewise.
 252         (cst4flag, size_changed): Likewise.
 253         * crx-opc.c (crx_cst4_map): Rename from cst4_map.
 254         (crx_cst4_maps): Rename from cst4_maps.
 255         (crx_no_op_insn): Rename from no_op_insn.
 256
 257 2017-10-24  Andrew Waterman  <andrew@sifive.com>
 258
 259         * riscv-opc.c (match_c_addi16sp) : New function.
 260         (match_c_addi4spn): New function.
 261         (match_c_lui): Don't allow 0-immediate encodings.
 262         (riscv_opcodes) <addi>: Use the above functions.
 263         <add>: Likewise.
 264         <c.addi4spn>: Likewise.
 265         <c.addi16sp>: Likewise.
 266
 267 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 268
 269         * i386-init.h: Regenerate
 270         * i386-tbl.h: Likewise
 271
 272 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 273
 274         * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
 275         (enum): Add EVEX_W_0F3854_P_2.
 276         * i386-dis-evex.h (evex_table): Updated.
 277         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
 278         CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 279         (cpu_flags): Add CpuAVX512_BITALG.
 280         * i386-opc.h (enum): Add CpuAVX512_BITALG.
 281         (i386_cpu_flags): Add cpuavx512_bitalg..
 282         * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
 283         * i386-init.h: Regenerate.
 284         * i386-tbl.h: Likewise.
 285
 286 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 287
 288         * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
 289         * i386-dis-evex.h (evex_table): Updated.
 290         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
 291         CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 292         (cpu_flags): Add CpuAVX512_VNNI.
 293         * i386-opc.h (enum): Add CpuAVX512_VNNI.
 294         (i386_cpu_flags): Add cpuavx512_vnni.
 295         * i386-opc.tbl Add Intel AVX512_VNNI instructions.
 296         * i386-init.h: Regenerate.
 297         * i386-tbl.h: Likewise.
 298
 299 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 300
 301         * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
 302         (enum): Remove VEX_LEN_0F3A44_P_2.
 303         (vex_len_table): Ditto.
 304         (enum): Remove VEX_W_0F3A44_P_2.
 305         (vew_w_table): Ditto.
 306         (prefix_table): Adjust instructions (see prefixes above).
 307         * i386-dis-evex.h (evex_table):
 308         Add new instructions (see prefixes above).
 309         * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
 310         (bitfield_cpu_flags): Ditto.
 311         * i386-opc.h (enum): Ditto.
 312         (i386_cpu_flags): Ditto.
 313         (CpuUnused): Comment out to avoid zero-width field problem.
 314         * i386-opc.tbl (vpclmulqdq): New instruction.
 315         * i386-init.h: Regenerate.
 316         * i386-tbl.h: Ditto.
 317
 318 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 319
 320         * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
 321         PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
 322         (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
 323         VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
 324         (vex_len_table): Ditto.
 325         (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
 326         VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
 327         (vew_w_table): Ditto.
 328         (prefix_table): Adjust instructions (see prefixes above).
 329         * i386-dis-evex.h (evex_table):
 330         Add new instructions (see prefixes above).
 331         * i386-gen.c (cpu_flag_init): Add VAES.
 332         (bitfield_cpu_flags): Ditto.
 333         * i386-opc.h (enum): Ditto.
 334         (i386_cpu_flags): Ditto.
 335         * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
 336         * i386-init.h: Regenerate.
 337         * i386-tbl.h: Ditto.
 338
 339 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 340
 341         * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
 342         PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
 343         PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
 344         (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
 345         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
 346         (prefix_table): Updated (see prefixes above).
 347         (three_byte_table): Likewise.
 348         (vex_w_table): Likewise.
 349         * i386-dis-evex.h: Likewise.
 350         * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
 351         (cpu_flags): Add CpuGFNI.
 352         * i386-opc.h (enum): Add CpuGFNI.
 353         (i386_cpu_flags): Add cpugfni.
 354         * i386-opc.tbl: Add Intel GFNI instructions.
 355         * i386-init.h: Regenerate.
 356         * i386-tbl.h: Likewise.
 357
 358 2017-10-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 359
 360         * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
 361         Define EXbScalar and EXwScalar for OP_EX.
 362         (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
 363         PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
 364         PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
 365         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
 366         (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
 367         EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
 368         EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
 369         EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
 370         (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
 371         (OP_E_memory): Likewise.
 372         * i386-dis-evex.h: Updated.
 373         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
 374         CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 375         (cpu_flags): Add CpuAVX512_VBMI2.
 376         * i386-opc.h (enum): Add CpuAVX512_VBMI2.
 377         (i386_cpu_flags): Add cpuavx512_vbmi2.
 378         * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
 379         * i386-init.h: Regenerate.
 380         * i386-tbl.h: Likewise.
 381
 382 2017-10-18  Eric Botcazou  <ebotcazou@adacore.com>
 383
 384         * visium-dis.c (disassem_class1) <case 0>: Print the operands.
 385
 386 2017-10-12  James Bowman  <james.bowman@ftdichip.com>
 387
 388         * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
 389         * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
 390         K15. Add jmpix pattern.
 391
 392 2017-10-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 393
 394         * s390-opc.txt (prno, tpei, irbm): New instructions added.
 395
 396 2017-10-09  Heiko Carstens  <heiko.carstens@de.ibm.com>
 397
 398         * s390-opc.c (INSTR_SI_RD): New macro.
 399         (INSTR_S_RD): Adjust example instruction.
 400         * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
 401         SI_RD.
 402
 403 2017-10-01  Alexander Fedotov  <alfedotov@gmail.com>
 404
 405         * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
 406         e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
 407         VLE multimple load/store instructions. Old e_ldm* variants are
 408         kept as aliases.
 409         Add missing e_lmvmcsrrw and e_stmvmcsrrw.
 410
 411 2017-09-27  Nick Clifton  <nickc@redhat.com>
 412
 413         PR 22179
 414         * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
 415         names for the fmv.x.s and fmv.s.x instructions respectively.
 416
 417 2017-09-26  do  <do@nerilex.org>
 418
 419         PR 22123
 420         * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
 421         be used on CPUs that have emacs support.
 422
 423 2017-09-21  Sergio Durigan Junior  <sergiodj@redhat.com>
 424
 425         * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
 426
 427 2017-09-09  Kamil Rytarowski  <n54@gmx.com>
 428
 429         * nds32-asm.c: Rename __BIT() to N32_BIT().
 430         * nds32-asm.h: Likewise.
 431         * nds32-dis.c: Likewise.
 432
 433 2017-09-09  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         * i386-dis.c (last_active_prefix): Removed.
 436         (ckprefix): Don't set last_active_prefix.
 437         (NOTRACK_Fixup): Don't check last_active_prefix.
 438
 439 2017-08-31  Nick Clifton  <nickc@redhat.com>
 440
 441         * po/fr.po: Updated French translation.
 442
 443 2017-08-31  James Bowman  <james.bowman@ftdichip.com>
 444
 445         * ft32-dis.c (print_insn_ft32): Correct display of non-address
 446         fields.
 447
 448 2017-08-23  Alexander Fedotov <alexander.fedotov@nxp.com>
 449             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 450
 451         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
 452         PPC_OPCODE_EFS2 flag to "e200z4" entry.
 453         New entries efs2 and spe2.
 454         Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
 455         (SPE2_OPCD_SEGS): New macro.
 456         (spe2_opcd_indices): New.
 457         (disassemble_init_powerpc): Handle SPE2 opcodes.
 458         (lookup_spe2): New function.
 459         (print_insn_powerpc): call lookup_spe2.
 460         * ppc-opc.c (insert_evuimm1_ex0): New function.
 461         (extract_evuimm1_ex0): Likewise.
 462         (insert_evuimm_lt8): Likewise.
 463         (extract_evuimm_lt8): Likewise.
 464         (insert_off_spe2): Likewise.
 465         (extract_off_spe2): Likewise.
 466         (insert_Ddd): Likewise.
 467         (extract_Ddd): Likewise.
 468         (DD): New operand.
 469         (EVUIMM_LT8): Likewise.
 470         (EVUIMM_LT16): Adjust.
 471         (MMMM): New operand.
 472         (EVUIMM_1): Likewise.
 473         (EVUIMM_1_EX0): Likewise.
 474         (EVUIMM_2): Adjust.
 475         (NNN): New operand.
 476         (VX_OFF_SPE2): Likewise.
 477         (BBB): Likewise.
 478         (DDD): Likewise.
 479         (VX_MASK_DDD): New mask.
 480         (HH): New operand.
 481         (VX_RA_CONST): New macro.
 482         (VX_RA_CONST_MASK): Likewise.
 483         (VX_RB_CONST): Likewise.
 484         (VX_RB_CONST_MASK): Likewise.
 485         (VX_OFF_SPE2_MASK): Likewise.
 486         (VX_SPE_CRFD): Likewise.
 487         (VX_SPE_CRFD_MASK VX): Likewise.
 488         (VX_SPE2_CLR): Likewise.
 489         (VX_SPE2_CLR_MASK): Likewise.
 490         (VX_SPE2_SPLATB): Likewise.
 491         (VX_SPE2_SPLATB_MASK): Likewise.
 492         (VX_SPE2_OCTET): Likewise.
 493         (VX_SPE2_OCTET_MASK): Likewise.
 494         (VX_SPE2_DDHH): Likewise.
 495         (VX_SPE2_DDHH_MASK): Likewise.
 496         (VX_SPE2_HH): Likewise.
 497         (VX_SPE2_HH_MASK): Likewise.
 498         (VX_SPE2_EVMAR): Likewise.
 499         (VX_SPE2_EVMAR_MASK): Likewise.
 500         (PPCSPE2): Likewise.
 501         (PPCEFS2): Likewise.
 502         (vle_opcodes): Add EFS2 and some missing SPE opcodes.
 503         (powerpc_macros): Map old SPE instructions have new names
 504         with the same opcodes. Add SPE2 instructions which just are
 505         mapped to SPE2.
 506         (spe2_opcodes): Add SPE2 opcodes.
 507
 508 2017-08-23  Alan Modra  <amodra@gmail.com>
 509
 510         * ppc-opc.c: Formatting and comment fixes.  Move insert and
 511         extract functions earlier, deleting forward declarations.
 512         (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
 513         RA_MASK.
 514
 515 2017-08-22  Palmer Dabbelt  <palmer@dabbelt.com>
 516
 517         * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
 518
 519 2017-08-21  Alexander Fedotov <alexander.fedotov@nxp.com>
 520             Edmar Wienskoski <edmar.wienskoski@nxp.com>
 521
 522         * ppc-opc.c (insert_evuimm2_ex0): New function.
 523         (extract_evuimm2_ex0): Likewise.
 524         (insert_evuimm4_ex0): Likewise.
 525         (extract_evuimm4_ex0): Likewise.
 526         (insert_evuimm8_ex0): Likewise.
 527         (extract_evuimm8_ex0): Likewise.
 528         (insert_evuimm_lt16): Likewise.
 529         (extract_evuimm_lt16): Likewise.
 530         (insert_rD_rS_even): Likewise.
 531         (extract_rD_rS_even): Likewise.
 532         (insert_off_lsp): Likewise.
 533         (extract_off_lsp): Likewise.
 534         (RD_EVEN): New operand.
 535         (RS_EVEN): Likewise.
 536         (RSQ): Adjust.
 537         (EVUIMM_LT16): New operand.
 538         (HTM_SI): Adjust.
 539         (EVUIMM_2_EX0): New operand.
 540         (EVUIMM_4): Adjust.
 541         (EVUIMM_4_EX0): New operand.
 542         (EVUIMM_8): Adjust.
 543         (EVUIMM_8_EX0): New operand.
 544         (WS): Adjust.
 545         (VX_OFF): New operand.
 546         (VX_LSP): New macro.
 547         (VX_LSP_MASK): Likewise.
 548         (VX_LSP_OFF_MASK): Likewise.
 549         (PPC_OPCODE_LSP): Likewise.
 550         (vle_opcodes): Add LSP opcodes.
 551         * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
 552
 553 2017-08-09  Jiong Wang  <jiong.wang@arm.com>
 554
 555         * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
 556         register operands in CRC instructions.
 557         (print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
 558         comments.
 559
 560 2017-08-07  H.J. Lu  <hongjiu.lu@intel.com>
 561
 562         * disassemble.c (disassembler): Mark big and mach with
 563         ATTRIBUTE_UNUSED.
 564
 565 2017-08-07  Maciej W. Rozycki  <macro@imgtec.com>
 566
 567         * disassemble.c (disassembler): Remove arch/mach/endian
 568         assertions.
 569
 570 2017-07-25  Nick Clifton  <nickc@redhat.com>
 571
 572         PR 21739
 573         * arc-opc.c (insert_rhv2): Use lower case first letter in error
 574         message.
 575         (insert_r0): Likewise.
 576         (insert_r1): Likewise.
 577         (insert_r2): Likewise.
 578         (insert_r3): Likewise.
 579         (insert_sp): Likewise.
 580         (insert_gp): Likewise.
 581         (insert_pcl): Likewise.
 582         (insert_blink): Likewise.
 583         (insert_ilink1): Likewise.
 584         (insert_ilink2): Likewise.
 585         (insert_ras): Likewise.
 586         (insert_rbs): Likewise.
 587         (insert_rcs): Likewise.
 588         (insert_simm3s): Likewise.
 589         (insert_rrange): Likewise.
 590         (insert_r13el): Likewise.
 591         (insert_fpel): Likewise.
 592         (insert_blinkel): Likewise.
 593         (insert_pclel): Likewise.
 594         (insert_nps_bitop_size_2b): Likewise.
 595         (insert_nps_imm_offset): Likewise.
 596         (insert_nps_imm_entry): Likewise.
 597         (insert_nps_size_16bit): Likewise.
 598         (insert_nps_##NAME##_pos): Likewise.
 599         (insert_nps_##NAME): Likewise.
 600         (insert_nps_bitop_ins_ext): Likewise.
 601         (insert_nps_##NAME): Likewise.
 602         (insert_nps_min_hofs): Likewise.
 603         (insert_nps_##NAME): Likewise.
 604         (insert_nps_rbdouble_64): Likewise.
 605         (insert_nps_misc_imm_offset): Likewise.
 606         * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
 607         option description.
 608
 609 2017-07-24  Laurent Desnogues  <laurent.desnogues@arm.com>
 610             Jiong Wang  <jiong.wang@arm.com>
 611
 612         * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
 613         correct the print.
 614         * aarch64-dis-2.c: Regenerated.
 615
 616 2017-07-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 617
 618         * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
 619         table.
 620
 621 2017-07-20  Nick Clifton  <nickc@redhat.com>
 622
 623         * po/de.po: Updated German translation.
 624
 625 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 626
 627         * arc-regs.h (sec_stat): New aux register.
 628         (aux_kernel_sp): Likewise.
 629         (aux_sec_u_sp): Likewise.
 630         (aux_sec_k_sp): Likewise.
 631         (sec_vecbase_build): Likewise.
 632         (nsc_table_top): Likewise.
 633         (nsc_table_base): Likewise.
 634         (ersec_stat): Likewise.
 635         (aux_sec_except): Likewise.
 636
 637 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 638
 639         * arc-opc.c (extract_uimm12_20): New function.
 640         (UIMM12_20): New operand.
 641         (SIMM3_5_S): Adjust.
 642         * arc-tbl.h (sjli): Add new instruction.
 643
 644 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 645             John Eric Martin  <John.Martin@emmicro-us.com>
 646
 647         * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
 648         (UIMM3_23): Adjust accordingly.
 649         * arc-regs.h: Add/correct jli_base register.
 650         * arc-tbl.h (jli_s): Likewise.
 651
 652 2017-07-18  Nick Clifton  <nickc@redhat.com>
 653
 654         PR 21775
 655         * aarch64-opc.c: Fix spelling typos.
 656         * i386-dis.c: Likewise.
 657
 658 2017-07-14  Ravi Bangoria  <ravi.bangoria@linux.vnet.ibm.com>
 659
 660         * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
 661         max_addr_offset and octets variables to size_t.
 662
 663 2017-07-12  Alan Modra  <amodra@gmail.com>
 664
 665         * po/da.po: Update from translationproject.org/latest/opcodes/.
 666         * po/de.po: Likewise.
 667         * po/es.po: Likewise.
 668         * po/fi.po: Likewise.
 669         * po/fr.po: Likewise.
 670         * po/id.po: Likewise.
 671         * po/it.po: Likewise.
 672         * po/nl.po: Likewise.
 673         * po/pt_BR.po: Likewise.
 674         * po/ro.po: Likewise.
 675         * po/sv.po: Likewise.
 676         * po/tr.po: Likewise.
 677         * po/uk.po: Likewise.
 678         * po/vi.po: Likewise.
 679         * po/zh_CN.po: Likewise.
 680
 681 2017-07-11  Yao Qi  <yao.qi@linaro.org>
 682             Alan Modra  <amodra@gmail.com>
 683
 684         * cgen.sh: Mark generated files read-only.
 685         * epiphany-asm.c: Regenerate.
 686         * epiphany-desc.c: Regenerate.
 687         * epiphany-desc.h: Regenerate.
 688         * epiphany-dis.c: Regenerate.
 689         * epiphany-ibld.c: Regenerate.
 690         * epiphany-opc.c: Regenerate.
 691         * epiphany-opc.h: Regenerate.
 692         * fr30-asm.c: Regenerate.
 693         * fr30-desc.c: Regenerate.
 694         * fr30-desc.h: Regenerate.
 695         * fr30-dis.c: Regenerate.
 696         * fr30-ibld.c: Regenerate.
 697         * fr30-opc.c: Regenerate.
 698         * fr30-opc.h: Regenerate.
 699         * frv-asm.c: Regenerate.
 700         * frv-desc.c: Regenerate.
 701         * frv-desc.h: Regenerate.
 702         * frv-dis.c: Regenerate.
 703         * frv-ibld.c: Regenerate.
 704         * frv-opc.c: Regenerate.
 705         * frv-opc.h: Regenerate.
 706         * ip2k-asm.c: Regenerate.
 707         * ip2k-desc.c: Regenerate.
 708         * ip2k-desc.h: Regenerate.
 709         * ip2k-dis.c: Regenerate.
 710         * ip2k-ibld.c: Regenerate.
 711         * ip2k-opc.c: Regenerate.
 712         * ip2k-opc.h: Regenerate.
 713         * iq2000-asm.c: Regenerate.
 714         * iq2000-desc.c: Regenerate.
 715         * iq2000-desc.h: Regenerate.
 716         * iq2000-dis.c: Regenerate.
 717         * iq2000-ibld.c: Regenerate.
 718         * iq2000-opc.c: Regenerate.
 719         * iq2000-opc.h: Regenerate.
 720         * lm32-asm.c: Regenerate.
 721         * lm32-desc.c: Regenerate.
 722         * lm32-desc.h: Regenerate.
 723         * lm32-dis.c: Regenerate.
 724         * lm32-ibld.c: Regenerate.
 725         * lm32-opc.c: Regenerate.
 726         * lm32-opc.h: Regenerate.
 727         * lm32-opinst.c: Regenerate.
 728         * m32c-asm.c: Regenerate.
 729         * m32c-desc.c: Regenerate.
 730         * m32c-desc.h: Regenerate.
 731         * m32c-dis.c: Regenerate.
 732         * m32c-ibld.c: Regenerate.
 733         * m32c-opc.c: Regenerate.
 734         * m32c-opc.h: Regenerate.
 735         * m32r-asm.c: Regenerate.
 736         * m32r-desc.c: Regenerate.
 737         * m32r-desc.h: Regenerate.
 738         * m32r-dis.c: Regenerate.
 739         * m32r-ibld.c: Regenerate.
 740         * m32r-opc.c: Regenerate.
 741         * m32r-opc.h: Regenerate.
 742         * m32r-opinst.c: Regenerate.
 743         * mep-asm.c: Regenerate.
 744         * mep-desc.c: Regenerate.
 745         * mep-desc.h: Regenerate.
 746         * mep-dis.c: Regenerate.
 747         * mep-ibld.c: Regenerate.
 748         * mep-opc.c: Regenerate.
 749         * mep-opc.h: Regenerate.
 750         * mt-asm.c: Regenerate.
 751         * mt-desc.c: Regenerate.
 752         * mt-desc.h: Regenerate.
 753         * mt-dis.c: Regenerate.
 754         * mt-ibld.c: Regenerate.
 755         * mt-opc.c: Regenerate.
 756         * mt-opc.h: Regenerate.
 757         * or1k-asm.c: Regenerate.
 758         * or1k-desc.c: Regenerate.
 759         * or1k-desc.h: Regenerate.
 760         * or1k-dis.c: Regenerate.
 761         * or1k-ibld.c: Regenerate.
 762         * or1k-opc.c: Regenerate.
 763         * or1k-opc.h: Regenerate.
 764         * or1k-opinst.c: Regenerate.
 765         * xc16x-asm.c: Regenerate.
 766         * xc16x-desc.c: Regenerate.
 767         * xc16x-desc.h: Regenerate.
 768         * xc16x-dis.c: Regenerate.
 769         * xc16x-ibld.c: Regenerate.
 770         * xc16x-opc.c: Regenerate.
 771         * xc16x-opc.h: Regenerate.
 772         * xstormy16-asm.c: Regenerate.
 773         * xstormy16-desc.c: Regenerate.
 774         * xstormy16-desc.h: Regenerate.
 775         * xstormy16-dis.c: Regenerate.
 776         * xstormy16-ibld.c: Regenerate.
 777         * xstormy16-opc.c: Regenerate.
 778         * xstormy16-opc.h: Regenerate.
 779
 780 2017-07-07  Alan Modra  <amodra@gmail.com>
 781
 782         * cgen-dis.in: Include disassemble.h, not dis-asm.h.
 783         * m32c-dis.c: Regenerate.
 784         * mep-dis.c: Regenerate.
 785
 786 2017-07-05  Borislav Petkov  <bp@suse.de>
 787
 788         * i386-dis.c: Enable ModRM.reg /6 aliases.
 789
 790 2017-07-04  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 791
 792         * opcodes/arm-dis.c: Support MVFR2 in disassembly
 793         with vmrs and vmsr.
 794
 795 2017-07-04  Tristan Gingold  <gingold@adacore.com>
 796
 797         * configure: Regenerate.
 798
 799 2017-07-03  Tristan Gingold  <gingold@adacore.com>
 800
 801         * po/opcodes.pot: Regenerate.
 802
 803 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 804
 805         * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
 806         entries to the MSA ASE instruction block.
 807
 808 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 809             Maciej W. Rozycki  <macro@imgtec.com>
 810
 811         * micromips-opc.c (XPA, XPAVZ): New macros.
 812         (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
 813         "mthgc0".
 814
 815 2017-06-30  Andrew Bennett  <andrew.bennett@imgtec.com>
 816             Maciej W. Rozycki  <macro@imgtec.com>
 817
 818         * micromips-opc.c (I36): New macro.
 819         (micromips_opcodes): Add "eretnc".
 820
 821 2017-06-30  Maciej W. Rozycki  <macro@imgtec.com>
 822             Andrew Bennett  <andrew.bennett@imgtec.com>
 823
 824         * mips-dis.c (mips_calculate_combination_ases): Handle the
 825         ASE_XPA_VIRT flag.
 826         (parse_mips_ase_option): New function.
 827         (parse_mips_dis_option): Factor out ASE option handling to the
 828         new function.  Call `mips_calculate_combination_ases'.
 829         * mips-opc.c (XPAVZ): New macro.
 830         (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
 831         "mfhgc0", "mthc0" and "mthgc0".
 832
 833 2017-06-29  Maciej W. Rozycki  <macro@imgtec.com>
 834
 835         * mips-dis.c (mips_calculate_combination_ases): New function.
 836         (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
 837         calculation to the new function.
 838         (set_default_mips_dis_options): Call the new function.
 839
 840 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 841
 842         * arc-dis.c (parse_disassembler_options): Use
 843         FOR_EACH_DISASSEMBLER_OPTION.
 844
 845 2017-06-29  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 846
 847         * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
 848         disassembler option strings.
 849         (parse_cpu_option): Likewise.
 850
 851 2017-06-28  Tamar Christina  <tamar.christina@arm.com>
 852
 853         * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
 854         * aarch64-dis.c (aarch64_ext_reglane): Likewise.
 855         * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
 856         (aarch64_feature_dotprod, DOT_INSN): New.
 857         (udot, sdot): New.
 858         * aarch64-dis-2.c: Regenerated.
 859
 860 2017-06-28  Jiong Wang  <jiong.wang@arm.com>
 861
 862         * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
 863
 864 2017-06-28  Maciej W. Rozycki  <macro@imgtec.com>
 865             Matthew Fortune  <matthew.fortune@imgtec.com>
 866             Andrew Bennett  <andrew.bennett@imgtec.com>
 867
 868         * mips-formats.h (INT_BIAS): New macro.
 869         (INT_ADJ): Redefine in INT_BIAS terms.
 870         * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
 871         (mips_print_save_restore): New function.
 872         (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
 873         (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
 874         call.
 875         (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
 876         (print_mips16_insn_arg): Call `mips_print_save_restore' for
 877         OP_SAVE_RESTORE_LIST handling, factored out from here.
 878         * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
 879         (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
 880         (mips_builtin_opcodes): Add "restore" and "save" entries.
 881         * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
 882         (IAMR2): New macro.
 883         (mips16_opcodes): Add "copyw" and "ucopyw" entries.
 884
 885 2017-06-23  Andrew Waterman  <andrew@sifive.com>
 886
 887         * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
 888         alias; do not mark SLTI instruction as an alias.
 889
 890 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 891
 892         * i386-dis.c (RM_0FAE_REG_5): Removed.
 893         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 894         (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
 895         (PREFIX_MOD_3_0FAE_REG_5): Likewise.
 896         (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
 897         PREFIX_MOD_3_0F01_REG_5_RM_0.
 898         (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
 899         PREFIX_MOD_3_0FAE_REG_5.
 900         (mod_table): Update MOD_0FAE_REG_5.
 901         (rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
 902         * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
 903         * i386-tbl.h: Regenerated.
 904
 905 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
 908         * i386-opc.tbl: Likewise.
 909         * i386-tbl.h: Regenerated.
 910
 911 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
 914         and "jmp{&|}".
 915         (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
 916         prefix.
 917
 918 2017-06-19  Nick Clifton  <nickc@redhat.com>
 919
 920         PR binutils/21614
 921         * score-dis.c (score_opcodes): Add sentinel.
 922
 923 2017-06-16  Alan Modra  <amodra@gmail.com>
 924
 925         * rx-decode.c: Regenerate.
 926
 927 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 928
 929         PR binutils/21594
 930         * i386-dis.c (OP_E_register): Check valid bnd register.
 931         (OP_G): Likewise.
 932
 933 2017-06-15  Nick Clifton  <nickc@redhat.com>
 934
 935         PR binutils/21595
 936         * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
 937         range value.
 938
 939 2017-06-15  Nick Clifton  <nickc@redhat.com>
 940
 941         PR binutils/21588
 942         * rl78-decode.opc (OP_BUF_LEN): Define.
 943         (GETBYTE): Check for the index exceeding OP_BUF_LEN.
 944         (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
 945         array.
 946         * rl78-decode.c: Regenerate.
 947
 948 2017-06-15  Nick Clifton  <nickc@redhat.com>
 949
 950         PR binutils/21586
 951         * bfin-dis.c (gregs): Clip index to prevent overflow.
 952         (regs): Likewise.
 953         (regs_lo): Likewise.
 954         (regs_hi): Likewise.
 955
 956 2017-06-14  Nick Clifton  <nickc@redhat.com>
 957
 958         PR binutils/21576
 959         * score7-dis.c (score_opcodes): Add sentinel.
 960
 961 2017-06-14  Yao Qi  <yao.qi@linaro.org>
 962
 963         * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
 964         * arm-dis.c: Likewise.
 965         * ia64-dis.c: Likewise.
 966         * mips-dis.c: Likewise.
 967         * spu-dis.c: Likewise.
 968         * disassemble.h (print_insn_aarch64): New declaration, moved from
 969         include/dis-asm.h.
 970         (print_insn_big_arm, print_insn_big_mips): Likewise.
 971         (print_insn_i386, print_insn_ia64): Likewise.
 972         (print_insn_little_arm, print_insn_little_mips): Likewise.
 973
 974 2017-06-14  Nick Clifton  <nickc@redhat.com>
 975
 976         PR binutils/21587
 977         * rx-decode.opc: Include libiberty.h
 978         (GET_SCALE): New macro - validates access to SCALE array.
 979         (GET_PSCALE): New macro - validates access to PSCALE array.
 980         (DIs, SIs, S2Is, rx_disp): Use new macros.
 981         * rx-decode.c: Regenerate.
 982
 983 2017-07-14  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 984
 985         * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
 986
 987 2017-05-30  Anton Kolesov  <anton.kolesov@synopsys.com>
 988
 989         * arc-dis.c (enforced_isa_mask): Declare.
 990         (cpu_types): Likewise.
 991         (parse_cpu_option): New function.
 992         (parse_disassembler_options): Use it.
 993         (print_insn_arc): Use enforced_isa_mask.
 994         (print_arc_disassembler_options): Document new options.
 995
 996 2017-05-24  Yao Qi  <yao.qi@linaro.org>
 997
 998         * alpha-dis.c: Include disassemble.h, don't include
 999         dis-asm.h.
1000         * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1001         * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1002         * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1003         * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1004         * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1005         * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1006         * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1007         * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1008         * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1009         * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1010         * moxie-dis.c, msp430-dis.c, mt-dis.c:
1011         * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1012         * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1013         * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1014         * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1015         * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1016         * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1017         * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1018         * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1019         * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1020         * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1021         * z80-dis.c, z8k-dis.c: Likewise.
1022         * disassemble.h: New file.
1023
1024 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1025
1026         * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1027         is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1028
1029 2017-05-24  Yao Qi  <yao.qi@linaro.org>
1030
1031         * disassemble.c (disassembler): Add arguments a, big and mach.
1032         Use them.
1033
1034 2017-05-22  H.J. Lu  <hongjiu.lu@intel.com>
1035
1036         * i386-dis.c (NOTRACK_Fixup): New.
1037         (NOTRACK): Likewise.
1038         (NOTRACK_PREFIX): Likewise.
1039         (last_active_prefix): Likewise.
1040         (reg_table): Use NOTRACK on indirect call and jmp.
1041         (ckprefix): Set last_active_prefix.
1042         (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1043         * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1044         * i386-opc.h (NoTrackPrefixOk): New.
1045         (i386_opcode_modifier): Add notrackprefixok.
1046         * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1047         Add notrack.
1048         * i386-tbl.h: Regenerated.
1049
1050 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1051
1052         * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1053         (X_IMM2): Define.
1054         (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1055         bfd_mach_sparc_v9m8.
1056         (print_insn_sparc): Handle new operand types.
1057         * sparc-opc.c (MASK_M8): Define.
1058         (v6): Add MASK_M8.
1059         (v6notlet): Likewise.
1060         (v7): Likewise.
1061         (v8): Likewise.
1062         (v9): Likewise.
1063         (v9a): Likewise.
1064         (v9b): Likewise.
1065         (v9c): Likewise.
1066         (v9d): Likewise.
1067         (v9e): Likewise.
1068         (v9v): Likewise.
1069         (v9m): Likewise.
1070         (v9andleon): Likewise.
1071         (m8): Define.
1072         (HWS_VM8): Define.
1073         (HWS2_VM8): Likewise.
1074         (sparc_opcode_archs): Add entry for "m8".
1075         (sparc_opcodes): Add OSA2017 and M8 instructions
1076         dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1077         fpx{ll,ra,rl}64x,
1078         ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1079         ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1080         revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1081         stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1082         (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1083         ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1084         ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1085         ASI_CORE_SELECT_COMMIT_NHT.
1086
1087 2017-05-18  Alan Modra  <amodra@gmail.com>
1088
1089         * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1090         * aarch64-dis.c: Likewise.
1091         * aarch64-gen.c: Likewise.
1092         * aarch64-opc.c: Likewise.
1093
1094 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1095             Matthew Fortune  <matthew.fortune@imgtec.com>
1096
1097         * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1098         ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1099         (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1100         (print_insn_arg) <OP_REG28>: Add handler.
1101         (validate_insn_args) <OP_REG28>: Handle.
1102         (print_mips16_insn_arg): Handle MIPS16 instructions that require
1103         32-bit encoding and 9-bit immediates.
1104         (print_insn_mips16): Handle MIPS16 instructions that require
1105         32-bit encoding and MFC0/MTC0 operand decoding.
1106         * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1107         <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1108         (RD_C0, WR_C0, E2, E2MT): New macros.
1109         (mips16_opcodes): Add entries for MIPS16e2 instructions:
1110         GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1111         "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1112         "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1113         "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1114         "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1115         instructions, "swl", "swr", "sync" and its "sync_acquire",
1116         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1117         "xori", "dmt", "dvpe", "emt" and "evpe".  Add split
1118         regular/extended entries for original MIPS16 ISA revision
1119         instructions whose extended forms are subdecoded in the MIPS16e2
1120         ISA revision: "li", "sll" and "srl".
1121
1122 2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
1123
1124         * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1125         reference in CP0 move operand decoding.
1126
1127 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
1128
1129         * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1130         type to hexadecimal.
1131         (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1132
1133 2017-05-11  Maciej W. Rozycki  <macro@imgtec.com>
1134
1135         * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1136         "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1137         "sync_rmb" and "sync_wmb" as aliases.
1138         * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1139         "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1140
1141 2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>
1142
1143         * arc-dis.c (parse_option): Update quarkse_em option..
1144         * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1145         QUARKSE1.
1146         (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1147
1148 2017-05-03  Kito Cheng  <kito.cheng@gmail.com>
1149
1150         * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1151
1152 2017-05-01  Michael Clark  <michaeljclark@mac.com>
1153
1154         * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1155         register.
1156
1157 2017-05-02  Maciej W. Rozycki  <macro@imgtec.com>
1158
1159         * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1160         and branches and not synthetic data instructions.
1161
1162 2017-05-02  Bernd Edlinger   <bernd.edlinger@hotmail.de>
1163
1164         * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1165
1166 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1167
1168         * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1169         * arc-opc.c (insert_r13el): New function.
1170         (R13_EL): Define.
1171         * arc-tbl.h: Add new enter/leave variants.
1172
1173 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
1174
1175         * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1176
1177 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1178
1179         * mips-dis.c (print_mips_disassembler_options): Add
1180         `no-aliases'.
1181
1182 2017-04-25  Maciej W. Rozycki  <macro@imgtec.com>
1183
1184         * mips16-opc.c (AL): New macro.
1185         (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1186         of "ld" and "lw" as aliases.
1187
1188 2017-04-24  Tamar Christina  <tamar.christina@arm.com>
1189
1190         * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1191         arguments.
1192
1193 2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
1194             Alan Modra  <amodra@gmail.com>
1195
1196         * ppc-opc.c (ELEV): Define.
1197         (vle_opcodes): Add se_rfgi and e_sc.
1198         (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1199         for E200Z4.
1200
1201 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
1202
1203         * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1204
1205 2017-04-21  Nick Clifton  <nickc@redhat.com>
1206
1207         PR binutils/21380
1208         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1209         LD3R and LD4R.
1210
1211 2017-04-13  Alan Modra  <amodra@gmail.com>
1212
1213         * epiphany-desc.c: Regenerate.
1214         * fr30-desc.c: Regenerate.
1215         * frv-desc.c: Regenerate.
1216         * ip2k-desc.c: Regenerate.
1217         * iq2000-desc.c: Regenerate.
1218         * lm32-desc.c: Regenerate.
1219         * m32c-desc.c: Regenerate.
1220         * m32r-desc.c: Regenerate.
1221         * mep-desc.c: Regenerate.
1222         * mt-desc.c: Regenerate.
1223         * or1k-desc.c: Regenerate.
1224         * xc16x-desc.c: Regenerate.
1225         * xstormy16-desc.c: Regenerate.
1226
1227 2017-04-11  Alan Modra  <amodra@gmail.com>
1228
1229         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1230         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
1231         PPC_OPCODE_TMR for e6500.
1232         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1233         (PPCVEC3): Define as PPC_OPCODE_POWER9.
1234         (PPCVSX2): Define as PPC_OPCODE_POWER8.
1235         (PPCVSX3): Define as PPC_OPCODE_POWER9.
1236         (PPCHTM): Define as PPC_OPCODE_POWER8.
1237         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1238
1239 2017-04-10  Alan Modra  <amodra@gmail.com>
1240
1241         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1242         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1243         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1244         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1245
1246 2017-04-09  Pip Cet  <pipcet@gmail.com>
1247
1248         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1249         appropriate floating-point precision directly.
1250
1251 2017-04-07  Alan Modra  <amodra@gmail.com>
1252
1253         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1254         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1255         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1256         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1257         vector instructions with E6500 not PPCVEC2.
1258
1259 2017-04-06  Pip Cet  <pipcet@gmail.com>
1260
1261         * Makefile.am: Add wasm32-dis.c.
1262         * configure.ac: Add wasm32-dis.c to wasm32 target.
1263         * disassemble.c: Add wasm32 disassembler code.
1264         * wasm32-dis.c: New file.
1265         * Makefile.in: Regenerate.
1266         * configure: Regenerate.
1267         * po/POTFILES.in: Regenerate.
1268         * po/opcodes.pot: Regenerate.
1269
1270 2017-04-05  Pedro Alves  <palves@redhat.com>
1271
1272         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1273         * arm-dis.c (parse_arm_disassembler_options): Constify.
1274         * ppc-dis.c (powerpc_init_dialect): Constify local.
1275         * vax-dis.c (parse_disassembler_options): Constify.
1276
1277 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
1278
1279         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1280         RISCV_GP_SYMBOL.
1281
1282 2017-03-30  Pip Cet  <pipcet@gmail.com>
1283
1284         * configure.ac: Add (empty) bfd_wasm32_arch target.
1285         * configure: Regenerate
1286         * po/opcodes.pot: Regenerate.
1287
1288 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
1289
1290         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1291         OSA2015.
1292         * opcodes/sparc-opc.c (asi_table): New ASIs.
1293
1294 2017-03-29  Alan Modra  <amodra@gmail.com>
1295
1296         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
1297         "raw" option.
1298         (lookup_powerpc): Don't special case -1 dialect.  Handle
1299         PPC_OPCODE_RAW.
1300         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1301         lookup_powerpc call, pass it on second.
1302
1303 2017-03-27  Alan Modra  <amodra@gmail.com>
1304
1305         PR 21303
1306         * ppc-dis.c (struct ppc_mopt): Comment.
1307         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1308
1309 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
1310
1311         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1312         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1313         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1314         (insert_nps_misc_imm_offset): New function.
1315         (extract_nps_misc imm_offset): New function.
1316         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1317         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1318
1319 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1320
1321         * s390-mkopc.c (main): Remove vx2 check.
1322         * s390-opc.txt: Remove vx2 instruction flags.
1323
1324 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
1325
1326         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1327         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1328         (insert_nps_imm_offset): New function.
1329         (extract_nps_imm_offset): New function.
1330         (insert_nps_imm_entry): New function.
1331         (extract_nps_imm_entry): New function.
1332
1333 2017-03-17  Alan Modra  <amodra@gmail.com>
1334
1335         PR 21248
1336         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1337         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
1338         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
1339
1340 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1341
1342         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1343         <c.andi>: Likewise.
1344         <c.addiw> Likewise.
1345
1346 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
1347
1348         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1349
1350 2017-03-13  Andrew Waterman  <andrew@sifive.com>
1351
1352         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1353         <srl> Likewise.
1354         <srai> Likewise.
1355         <sra> Likewise.
1356
1357 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1358
1359         * i386-gen.c (opcode_modifiers): Replace S with Load.
1360         * i386-opc.h (S): Removed.
1361         (Load): New.
1362         (i386_opcode_modifier): Replace s with load.
1363         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1364         and {evex}.  Replace S with Load.
1365         * i386-tbl.h: Regenerated.
1366
1367 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
1368
1369         * i386-opc.tbl: Use CpuCET on rdsspq.
1370         * i386-tbl.h: Regenerated.
1371
1372 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1373
1374         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1375         <vsx>: Do not use PPC_OPCODE_VSX3;
1376
1377 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
1378
1379         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1380
1381 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
1382
1383         * i386-dis.c (REG_0F1E_MOD_3): New enum.
1384         (MOD_0F1E_PREFIX_1): Likewise.
1385         (MOD_0F38F5_PREFIX_2): Likewise.
1386         (MOD_0F38F6_PREFIX_0): Likewise.
1387         (RM_0F1E_MOD_3_REG_7): Likewise.
1388         (PREFIX_MOD_0_0F01_REG_5): Likewise.
1389         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1390         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1391         (PREFIX_0F1E): Likewise.
1392         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1393         (PREFIX_0F38F5): Likewise.
1394         (dis386_twobyte): Use PREFIX_0F1E.
1395         (reg_table): Add REG_0F1E_MOD_3.
1396         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1397         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1398         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
1399         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1400         (three_byte_table): Use PREFIX_0F38F5.
1401         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1402         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1403         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1404         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1405         PREFIX_MOD_3_0F01_REG_5_RM_2.
1406         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1407         (cpu_flags): Add CpuCET.
1408         * i386-opc.h (CpuCET): New enum.
1409         (CpuUnused): Commented out.
1410         (i386_cpu_flags): Add cpucet.
1411         * i386-opc.tbl: Add Intel CET instructions.
1412         * i386-init.h: Regenerated.
1413         * i386-tbl.h: Likewise.
1414
1415 2017-03-06  Alan Modra  <amodra@gmail.com>
1416
1417         PR 21124
1418         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1419         (extract_raq, extract_ras, extract_rbx): New functions.
1420         (powerpc_operands): Use opposite corresponding insert function.
1421         (Q_MASK): Define.
1422         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1423         register restriction.
1424
1425 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
1426
1427         * disassemble.c Include "safe-ctype.h".
1428         (disassemble_init_for_target): Handle s390 init.
1429         (remove_whitespace_and_extra_commas): New function.
1430         (disassembler_options_cmp): Likewise.
1431         * arm-dis.c: Include "libiberty.h".
1432         (NUM_ELEM): Delete.
1433         (regnames): Use long disassembler style names.
1434         Add force-thumb and no-force-thumb options.
1435         (NUM_ARM_REGNAMES): Rename from this...
1436         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
1437         (get_arm_regname_num_options): Delete.
1438         (set_arm_regname_option): Likewise.
1439         (get_arm_regnames): Likewise.
1440         (parse_disassembler_options): Likewise.
1441         (parse_arm_disassembler_option): Rename from this...
1442         (parse_arm_disassembler_options): ...to this.  Make static.
1443         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1444         (print_insn): Use parse_arm_disassembler_options.
1445         (disassembler_options_arm): New function.
1446         (print_arm_disassembler_options): Handle updated regnames.
1447         * ppc-dis.c: Include "libiberty.h".
1448         (ppc_opts): Add "32" and "64" entries.
1449         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1450         (powerpc_init_dialect): Add break to switch statement.
1451         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1452         (disassembler_options_powerpc): New function.
1453         (print_ppc_disassembler_options): Use ARRAY_SIZE.
1454         Remove printing of "32" and "64".
1455         * s390-dis.c: Include "libiberty.h".
1456         (init_flag): Remove unneeded variable.
1457         (struct s390_options_t): New structure type.
1458         (options): New structure.
1459         (init_disasm): Rename from this...
1460         (disassemble_init_s390): ...to this.  Add initializations for
1461         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
1462         (print_insn_s390): Delete call to init_disasm.
1463         (disassembler_options_s390): New function.
1464         (print_s390_disassembler_options): Print using information from
1465         struct 'options'.
1466         * po/opcodes.pot: Regenerate.
1467
1468 2017-02-28  Jan Beulich  <jbeulich@suse.com>
1469
1470         * i386-dis.c (PCMPESTR_Fixup): New.
1471         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1472         (prefix_table): Use PCMPESTR_Fixup.
1473         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1474         PCMPESTR_Fixup.
1475         (vex_w_table): Delete VPCMPESTR{I,M} entries.
1476         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1477         Split 64-bit and non-64-bit variants.
1478         * opcodes/i386-tbl.h: Re-generate.
1479
1480 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1481
1482         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1483         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1484         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1485         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1486         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1487         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1488         (OP_SVE_V_HSD): New macros.
1489         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1490         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1491         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1492         (aarch64_opcode_table): Add new SVE instructions.
1493         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1494         for rotation operands.  Add new SVE operands.
1495         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1496         (ins_sve_quad_index): Likewise.
1497         (ins_imm_rotate): Split into...
1498         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1499         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1500         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1501         functions.
1502         (aarch64_ins_sve_addr_ri_s4): New function.
1503         (aarch64_ins_sve_quad_index): Likewise.
1504         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1505         * aarch64-asm-2.c: Regenerate.
1506         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1507         (ext_sve_quad_index): Likewise.
1508         (ext_imm_rotate): Split into...
1509         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1510         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1511         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1512         functions.
1513         (aarch64_ext_sve_addr_ri_s4): New function.
1514         (aarch64_ext_sve_quad_index): Likewise.
1515         (aarch64_ext_sve_index): Allow quad indices.
1516         (do_misc_decoding): Likewise.
1517         * aarch64-dis-2.c: Regenerate.
1518         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1519         aarch64_field_kinds.
1520         (OPD_F_OD_MASK): Widen by one bit.
1521         (OPD_F_NO_ZR): Bump accordingly.
1522         (get_operand_field_width): New function.
1523         * aarch64-opc.c (fields): Add new SVE fields.
1524         (operand_general_constraint_met_p): Handle new SVE operands.
1525         (aarch64_print_operand): Likewise.
1526         * aarch64-opc-2.c: Regenerate.
1527
1528 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
1529
1530         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1531         (aarch64_feature_compnum): ...this.
1532         (SIMD_V8_3): Replace with...
1533         (COMPNUM): ...this.
1534         (CNUM_INSN): New macro.
1535         (aarch64_opcode_table): Use it for the complex number instructions.
1536
1537 2017-02-24  Jan Beulich  <jbeulich@suse.com>
1538
1539         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1540
1541 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
1542
1543         Add support for associating SPARC ASIs with an architecture level.
1544         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1545         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1546         decoding of SPARC ASIs.
1547
1548 2017-02-23  Jan Beulich  <jbeulich@suse.com>
1549
1550         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1551         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1552
1553 2017-02-21  Jan Beulich  <jbeulich@suse.com>
1554
1555         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1556         1 (instead of to itself). Correct typo.
1557
1558 2017-02-14  Andrew Waterman  <andrew@sifive.com>
1559
1560         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1561         pseudoinstructions.
1562
1563 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
1564
1565         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1566         (aarch64_sys_reg_supported_p): Handle them.
1567
1568 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
1569
1570         * arc-opc.c (UIMM6_20R): Define.
1571         (SIMM12_20): Use above.
1572         (SIMM12_20R): Define.
1573         (SIMM3_5_S): Use above.
1574         (UIMM7_A32_11R_S): Define.
1575         (UIMM7_9_S): Use above.
1576         (UIMM3_13R_S): Define.
1577         (SIMM11_A32_7_S): Use above.
1578         (SIMM9_8R): Define.
1579         (UIMM10_A32_8_S): Use above.
1580         (UIMM8_8R_S): Define.
1581         (W6): Use above.
1582         (arc_relax_opcodes): Use all above defines.
1583
1584 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
1585
1586         * arc-regs.h: Distinguish some of the registers different on
1587         ARC700 and HS38 cpus.
1588
1589 2017-02-14  Alan Modra  <amodra@gmail.com>
1590
1591         PR 21118
1592         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1593         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
1594
1595 2017-02-11  Stafford Horne  <shorne@gmail.com>
1596             Alan Modra  <amodra@gmail.com>
1597
1598         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1599         Use insn_bytes_value and insn_int_value directly instead.  Don't
1600         free allocated memory until function exit.
1601
1602 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
1603
1604         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1605
1606 2017-02-03  Nick Clifton  <nickc@redhat.com>
1607
1608         PR 21096
1609         * aarch64-opc.c (print_register_list): Ensure that the register
1610         list index will fir into the tb buffer.
1611         (print_register_offset_address): Likewise.
1612         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1613
1614 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
1615
1616         PR 21056
1617         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1618         instructions when the previous fetch packet ends with a 32-bit
1619         instruction.
1620
1621 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
1622
1623         * pru-opc.c: Remove vague reference to a future GDB port.
1624
1625 2017-01-20  Nick Clifton  <nickc@redhat.com>
1626
1627         * po/ga.po: Updated Irish translation.
1628
1629 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1630
1631         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1632
1633 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1634
1635         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
1636         if FETCH_DATA returns 0.
1637         (m68k_scan_mask): Likewise.
1638         (print_insn_m68k): Update code to handle -1 return value.
1639
1640 2017-01-13  Yao Qi  <yao.qi@linaro.org>
1641
1642         * m68k-dis.c (enum print_insn_arg_error): New.
1643         (NEXTBYTE): Replace -3 with
1644         PRINT_INSN_ARG_MEMORY_ERROR.
1645         (NEXTULONG): Likewise.
1646         (NEXTSINGLE): Likewise.
1647         (NEXTDOUBLE): Likewise.
1648         (NEXTDOUBLE): Likewise.
1649         (NEXTPACKED): Likewise.
1650         (FETCH_ARG): Likewise.
1651         (FETCH_DATA): Update comments.
1652         (print_insn_arg): Update comments. Replace magic numbers with
1653         enum.
1654         (match_insn_m68k): Likewise.
1655
1656 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1657
1658         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1659         * i386-dis-evex.h (evex_table): Updated.
1660         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1661         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1662         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1663         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1664         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1665         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1666         * i386-init.h: Regenerate.
1667         * i386-tbl.h: Ditto.
1668
1669 2017-01-12  Yao Qi  <yao.qi@linaro.org>
1670
1671         * msp430-dis.c (msp430_singleoperand): Return -1 if
1672         msp430dis_opcode_signed returns false.
1673         (msp430_doubleoperand): Likewise.
1674         (msp430_branchinstr): Return -1 if
1675         msp430dis_opcode_unsigned returns false.
1676         (msp430x_calla_instr): Likewise.
1677         (print_insn_msp430): Likewise.
1678
1679 2017-01-05  Nick Clifton  <nickc@redhat.com>
1680
1681         PR 20946
1682         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1683         could not be matched.
1684         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1685         NULL.
1686
1687 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1688
1689         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1690         (aarch64_opcode_table): Use RCPC_INSN.
1691
1692 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
1693
1694         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1695         extension.
1696         * riscv-opcodes/all-opcodes: Likewise.
1697
1698 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
1699
1700         * riscv-dis.c (print_insn_args): Add fall through comment.
1701
1702 2017-01-03  Nick Clifton  <nickc@redhat.com>
1703
1704         * po/sr.po: New Serbian translation.
1705         * configure.ac (ALL_LINGUAS): Add sr.
1706         * configure: Regenerate.
1707
1708 2017-01-02  Alan Modra  <amodra@gmail.com>
1709
1710         * epiphany-desc.h: Regenerate.
1711         * epiphany-opc.h: Regenerate.
1712         * fr30-desc.h: Regenerate.
1713         * fr30-opc.h: Regenerate.
1714         * frv-desc.h: Regenerate.
1715         * frv-opc.h: Regenerate.
1716         * ip2k-desc.h: Regenerate.
1717         * ip2k-opc.h: Regenerate.
1718         * iq2000-desc.h: Regenerate.
1719         * iq2000-opc.h: Regenerate.
1720         * lm32-desc.h: Regenerate.
1721         * lm32-opc.h: Regenerate.
1722         * m32c-desc.h: Regenerate.
1723         * m32c-opc.h: Regenerate.
1724         * m32r-desc.h: Regenerate.
1725         * m32r-opc.h: Regenerate.
1726         * mep-desc.h: Regenerate.
1727         * mep-opc.h: Regenerate.
1728         * mt-desc.h: Regenerate.
1729         * mt-opc.h: Regenerate.
1730         * or1k-desc.h: Regenerate.
1731         * or1k-opc.h: Regenerate.
1732         * xc16x-desc.h: Regenerate.
1733         * xc16x-opc.h: Regenerate.
1734         * xstormy16-desc.h: Regenerate.
1735         * xstormy16-opc.h: Regenerate.
1736
1737 2017-01-02  Alan Modra  <amodra@gmail.com>
1738
1739         Update year range in copyright notice of all files.
1740
1741 For older changes see ChangeLog-2016
1742 \f
1743 Copyright (C) 2017 Free Software Foundation, Inc.
1744
1745 Copying and distribution of this file, with or without modification,
1746 are permitted in any medium without royalty provided the copyright
1747 notice and this notice are preserved.
1748
1749 Local Variables:
1750 mode: change-log
1751 left-margin: 8
1752 fill-column: 74
1753 version-control: never
1754 End: