opcodes/ChangeLog

   1 2015-11-16  Nick Clifton  <nickc@redhat.com>
   2
   3         * rx-dis.c (condition_names): Replace always and never with
   4         invalid, since the always/never conditions can never be legal.
   5
   6 2015-11-13  Tristan Gingold  <gingold@adacore.com>
   7
   8         * configure: Regenerate.
   9
  10 2015-11-11  Alan Modra  <amodra@gmail.com>
  11             Peter Bergner <bergner@vnet.ibm.com>
  12
  13         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
  14         Add PPC_OPCODE_VSX3 to the vsx entry.
  15         (powerpc_init_dialect): Set default dialect to power9.
  16         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
  17         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
  18         extract_l1 insert_xtq6, extract_xtq6): New static functions.
  19         (insert_esync): Test for illegal L operand value.
  20         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
  21         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
  22         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
  23         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
  24         PPCVSX3): New defines.
  25         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
  26         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
  27         <mcrxr>: Use XBFRARB_MASK.
  28         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
  29         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
  30         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
  31         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
  32         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
  33         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
  34         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
  35         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
  36         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
  37         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
  38         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
  39         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
  40         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
  41         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
  42         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
  43         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
  44         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
  45         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
  46         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
  47         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
  48         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
  49         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
  50         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
  51         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
  52         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
  53         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
  54         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
  55         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
  56         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
  57         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
  58         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
  59         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
  60
  61 2015-11-02  Nick Clifton  <nickc@redhat.com>
  62
  63         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
  64         instructions.
  65         * rx-decode.c: Regenerate.
  66
  67 2015-11-02  Nick Clifton  <nickc@redhat.com>
  68
  69         * rx-decode.opc (rx_disp): If the displacement is zero, set the
  70         type to RX_Operand_Zero_Indirect.
  71         * rx-decode.c: Regenerate.
  72         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
  73
  74 2015-10-28  Yao Qi  <yao.qi@linaro.org>
  75
  76         * aarch64-dis.c (aarch64_decode_insn): Add one argument
  77         noaliases_p.  Update comments.  Pass noaliases_p rather than
  78         no_aliases to aarch64_opcode_decode.
  79         (print_insn_aarch64_word): Pass no_aliases to
  80         aarch64_decode_insn.
  81
  82 2015-10-27  Vinay  <Vinay.G@kpit.com>
  83
  84         PR binutils/19159
  85         * rl78-decode.opc (MOV): Added offset to DE register in index
  86         addressing mode.
  87         * rl78-decode.c: Regenerate.
  88
  89 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
  90
  91         PR binutils/19158
  92         * rl78-decode.opc: Add 's' print operator to instructions that
  93         access system registers.
  94         * rl78-decode.c: Regenerate.
  95         * rl78-dis.c (print_insn_rl78_common): Decode all system
  96         registers.
  97
  98 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
  99
 100         PR binutils/19157
 101         * rl78-decode.opc: Add 'a' print operator to mov instructions
 102         using stack pointer plus index addressing.
 103         * rl78-decode.c: Regenerate.
 104
 105 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 106
 107         * s390-opc.c: Fix comment.
 108         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 109         trtt to RRF_U0RER since the second parameter does not need to be a
 110         register pair.
 111
 112 2015-10-08  Nick Clifton  <nickc@redhat.com>
 113
 114         * arc-dis.c (print_insn_arc): Initiallise insn array.
 115
 116 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 117
 118         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 119         'name' rather than 'template'.
 120         * aarch64-opc.c (aarch64_print_operand): Likewise.
 121
 122 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 123
 124         * arc-dis.c: Revamped file for ARC support
 125         * arc-dis.h: Likewise.
 126         * arc-ext.c: Likewise.
 127         * arc-ext.h: Likewise.
 128         * arc-opc.c: Likewise.
 129         * arc-fxi.h: New file.
 130         * arc-regs.h: Likewise.
 131         * arc-tbl.h: Likewise.
 132
 133 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 134
 135         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 136         argument insn type to aarch64_insn.  Rename to ...
 137         (aarch64_decode_insn): ... it.
 138         (print_insn_aarch64_word): Caller updated.
 139
 140 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 141
 142         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 143         (print_insn_aarch64_word): Caller updated.
 144
 145 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 146
 147         * s390-mkopc.c (main): Parse htm and vx flag.
 148         * s390-opc.txt: Mark instructions from the hardware transactional
 149         memory and vector facilities with the "htm"/"vx" flag.
 150
 151 2015-09-28  Nick Clifton  <nickc@redhat.com>
 152
 153         * po/de.po: Updated German translation.
 154
 155 2015-09-28  Tom Rix  <tom@bumblecow.com>
 156
 157         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 158
 159 2015-09-23  Nick Clifton  <nickc@redhat.com>
 160
 161         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 162         function.
 163         * tic30-dis.c (print_branch): Likewise.
 164         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 165         value before left shifting.
 166         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 167         * hppa-dis.c (print_insn_hppa): Likewise.
 168         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 169         array.
 170         * msp430-dis.c (msp430_singleoperand): Likewise.
 171         (msp430_doubleoperand): Likewise.
 172         (print_insn_msp430): Likewise.
 173         * nds32-asm.c (parse_operand): Likewise.
 174         * sh-opc.h (MASK): Likewise.
 175         * v850-dis.c (get_operand_value): Likewise.
 176
 177 2015-09-22  Nick Clifton  <nickc@redhat.com>
 178
 179         * rx-decode.opc (bwl): Use RX_Bad_Size.
 180         (sbwl): Likewise.
 181         (ubwl): Likewise.  Rename to ubw.
 182         (uBWL): Rename to uBW.
 183         Replace all references to uBWL with uBW.
 184         * rx-decode.c: Regenerate.
 185         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 186         (opsize_names): Likewise.
 187         (print_insn_rx): Detect and report RX_Bad_Size.
 188
 189 2015-09-22  Anton Blanchard  <anton@samba.org>
 190
 191         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 192
 193 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 194
 195         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 196         %pmcdper.
 197
 198 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 199
 200         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 201
 202 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 203
 204         PR binutils/18257
 205         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 206         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 207         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 208         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 209         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 210         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 211         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 212         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 213         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 214         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 215         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 216         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 217         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 218         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 219         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 220         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 221         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 222         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 223         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 224         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 225         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 226         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 227         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 228         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 229         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 230         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 231         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 232         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 233         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 234         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 235         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 236         (vex_w_table): Replace terminals with MOD_TABLE entries for
 237         most of mask instructions.
 238
 239 2015-08-17  Alan Modra  <amodra@gmail.com>
 240
 241         * cgen.sh: Trim trailing space from cgen output.
 242         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 243         (print_dis_table): Likewise.
 244         * opc2c.c (dump_lines): Likewise.
 245         (orig_filename): Warning fix.
 246         * ia64-asmtab.c: Regenerate.
 247
 248 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 249
 250         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 251         and higher with ARM instruction set will now mark the 26-bit
 252         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 253         (arm_opcodes): Fix for unpredictable nop being recognized as a
 254         teq.
 255
 256 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 257
 258         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 259         based on 'or' is first.
 260         * mips-opc.c (mips_builtin_opcodes): Ditto.
 261
 262 2015-08-11  Nick Clifton  <nickc@redhat.com>
 263
 264         PR 18800
 265         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 266         instruction.
 267
 268 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 269
 270         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 271
 272 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 273
 274         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 275         * i386-init.h: Regenerated.
 276
 277 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         PR binutils/13571
 280         * i386-dis.c (MOD_0FC3): New.
 281         (PREFIX_0FC3): Renamed to ...
 282         (PREFIX_MOD_0_0FC3): This.
 283         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 284         (prefix_table): Replace Ma with Ev on movntiS.
 285         (mod_table): Add MOD_0FC3.
 286
 287 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 288
 289         * configure: Regenerated.
 290
 291 2015-07-23  Alan Modra  <amodra@gmail.com>
 292
 293         PR 18708
 294         * i386-dis.c (get64): Avoid signed integer overflow.
 295
 296 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 297
 298         PR binutils/18631
 299         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 300         "EXEvexHalfBcstXmmq" for the second operand.
 301         (EVEX_W_0F79_P_2): Likewise.
 302         (EVEX_W_0F7A_P_2): Likewise.
 303         (EVEX_W_0F7B_P_2): Likewise.
 304
 305 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 306
 307         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 308         float bitfield format.
 309         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 310         quarter float bitfield format.
 311
 312 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * configure: Regenerated.
 315
 316 2015-07-03  Alan Modra  <amodra@gmail.com>
 317
 318         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 319         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 320         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 321
 322 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 323             Cesar Philippidis  <cesar@codesourcery.com>
 324
 325         * nios2-dis.c (nios2_extract_opcode): New.
 326         (nios2_disassembler_state): New.
 327         (nios2_find_opcode_hash): Use mach parameter to select correct
 328         disassembler state.
 329         (nios2_print_insn_arg): Extend to support new R2 argument letters
 330         and formats.
 331         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 332         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 333         (NIOS2_NUM_OPCODES): Rename to...
 334         (NIOS2_NUM_R1_OPCODES): This.
 335         (nios2_r2_opcodes): New.
 336         (NIOS2_NUM_R2_OPCODES): New.
 337         (nios2_num_r2_opcodes): New.
 338         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 339         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 340         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 341         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 342         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 343
 344 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 345
 346         * i386-dis.c (OP_Mwaitx): New.
 347         (rm_table): Add monitorx/mwaitx.
 348         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 349         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 350         (operand_type_init): Add CpuMWAITX.
 351         * i386-opc.h (CpuMWAITX): New.
 352         (i386_cpu_flags): Add cpumwaitx.
 353         * i386-opc.tbl: Add monitorx and mwaitx.
 354         * i386-init.h: Regenerated.
 355         * i386-tbl.h: Likewise.
 356
 357 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 358
 359         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 360         (insert_esync): New function.
 361         (LS, WC): Use insert_ls.
 362         (ESYNC): Use insert_esync.
 363
 364 2015-06-22  Nick Clifton  <nickc@redhat.com>
 365
 366         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 367         requested region lies beyond it.
 368         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 369         looking for 32-bit insns.
 370         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 371         data.
 372         * sh-dis.c (print_insn_sh): Likewise.
 373         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 374         blocks of instructions.
 375         * vax-dis.c (print_insn_vax): Check that the requested address
 376         does not clash with the stop_vma.
 377
 378 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 379
 380         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 381         * ppc-opc.c (FXM4): Add non-zero optional value.
 382         (TBR): Likewise.
 383         (SXL): Likewise.
 384         (insert_fxm): Handle new default operand value.
 385         (extract_fxm): Likewise.
 386         (insert_tbr): Likewise.
 387         (extract_tbr): Likewise.
 388
 389 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 390
 391         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 392
 393 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 394
 395         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 396
 397 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 398
 399         * ppc-opc.c: Add comment accidentally removed by old commit.
 400         (MTMSRD_L): Delete.
 401
 402 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 403
 404         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 405
 406 2015-06-04  Nick Clifton  <nickc@redhat.com>
 407
 408         PR 18474
 409         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 410
 411 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 412
 413         * arm-dis.c (arm_opcodes): Add "setpan".
 414         (thumb_opcodes): Add "setpan".
 415
 416 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 417
 418         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 419         macros.
 420
 421 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 422
 423         * aarch64-tbl.h (aarch64_feature_rdma): New.
 424         (RDMA): New.
 425         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 426         * aarch64-asm-2.c: Regenerate.
 427         * aarch64-dis-2.c: Regenerate.
 428         * aarch64-opc-2.c: Regenerate.
 429
 430 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 431
 432         * aarch64-tbl.h (aarch64_feature_lor): New.
 433         (LOR): New.
 434         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 435         "stllrb", "stllrh".
 436         * aarch64-asm-2.c: Regenerate.
 437         * aarch64-dis-2.c: Regenerate.
 438         * aarch64-opc-2.c: Regenerate.
 439
 440 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 441
 442         * aarch64-opc.c (F_ARCHEXT): New.
 443         (aarch64_sys_regs): Add "pan".
 444         (aarch64_sys_reg_supported_p): New.
 445         (aarch64_pstatefields): Add "pan".
 446         (aarch64_pstatefield_supported_p): New.
 447
 448 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-tbl.h: Regenerate.
 451
 452 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-dis.c (print_insn): Swap rounding mode specifier and
 455         general purpose register in Intel mode.
 456
 457 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 458
 459         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 460         * i386-tbl.h: Regenerate.
 461
 462 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 463
 464         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 465         * i386-init.h: Regenerated.
 466
 467 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         PR binutis/18386
 470         * i386-dis.c: Add comments for '@'.
 471         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 472         (enum x86_64_isa): New.
 473         (isa64): Likewise.
 474         (print_i386_disassembler_options): Add amd64 and intel64.
 475         (print_insn): Handle amd64 and intel64.
 476         (putop): Handle '@'.
 477         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 478         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 479         * i386-opc.h (AMD64): New.
 480         (CpuIntel64): Likewise.
 481         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 482         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 483         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 484         * i386-init.h: Regenerated.
 485         * i386-tbl.h: Likewise.
 486
 487 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 488
 489         * ppc-opc.c (IH) New define.
 490         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 491         <tlbie>: Add RS operand for POWER7.
 492         <slbia>: Add IH operand for POWER6.
 493
 494 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 497         direct branch.
 498         (jmp): Likewise.
 499         * i386-tbl.h: Regenerated.
 500
 501 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         * configure.ac: Support bfd_iamcu_arch.
 504         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 505         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 506         CPU_IAMCU_COMPAT_FLAGS.
 507         (cpu_flags): Add CpuIAMCU.
 508         * i386-opc.h (CpuIAMCU): New.
 509         (i386_cpu_flags): Add cpuiamcu.
 510         * configure: Regenerated.
 511         * i386-init.h: Likewise.
 512         * i386-tbl.h: Likewise.
 513
 514 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         PR binutis/18386
 517         * i386-dis.c (X86_64_E8): New.
 518         (X86_64_E9): Likewise.
 519         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 520         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 521         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 522         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 523         (putop): Handle '^'.
 524         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 525         REX_W.
 526
 527 2015-04-30  DJ Delorie  <dj@redhat.com>
 528
 529         * disassemble.c (disassembler): Choose suitable disassembler based
 530         on E_ABI.
 531         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 532         it to decode mul/div insns.
 533         * rl78-decode.c: Regenerate.
 534         * rl78-dis.c (print_insn_rl78): Rename to...
 535         (print_insn_rl78_common): ...this, take ISA parameter.
 536         (print_insn_rl78): New.
 537         (print_insn_rl78_g10): New.
 538         (print_insn_rl78_g13): New.
 539         (print_insn_rl78_g14): New.
 540         (rl78_get_disassembler): New.
 541
 542 2015-04-29  Nick Clifton  <nickc@redhat.com>
 543
 544         * po/fr.po: Updated French translation.
 545
 546 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 547
 548         * ppc-opc.c (DCBT_EO): New define.
 549         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 550         <lharx>: Likewise.
 551         <stbcx.>: Likewise.
 552         <sthcx.>: Likewise.
 553         <waitrsv>: Do not enable for POWER7 and later.
 554         <waitimpl>: Likewise.
 555         <dcbt>: Default to the two operand form of the instruction for all
 556         "old" cpus.  For "new" cpus, use the operand ordering that matches
 557         whether the cpu is server or embedded.
 558         <dcbtst>: Likewise.
 559
 560 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 561
 562         * s390-opc.c: New instruction type VV0UU2.
 563         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 564         and WFC.
 565
 566 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 569         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 570         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 571         (vfpclasspd, vfpclassps): Add %XZ.
 572
 573 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 576         (PREFIX_UD_REPZ): Likewise.
 577         (PREFIX_UD_REPNZ): Likewise.
 578         (PREFIX_UD_DATA): Likewise.
 579         (PREFIX_UD_ADDR): Likewise.
 580         (PREFIX_UD_LOCK): Likewise.
 581
 582 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 583
 584         * i386-dis.c (prefix_requirement): Removed.
 585         (print_insn): Don't set prefix_requirement.  Check
 586         dp->prefix_requirement instead of prefix_requirement.
 587
 588 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         PR binutils/17898
 591         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 592         (PREFIX_MOD_0_0FC7_REG_6): This.
 593         (PREFIX_MOD_3_0FC7_REG_6): New.
 594         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 595         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 596         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 597         PREFIX_MOD_3_0FC7_REG_7.
 598         (mod_table): Replace PREFIX_0FC7_REG_6 with
 599         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 600         PREFIX_MOD_3_0FC7_REG_7.
 601
 602 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 603
 604         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 605         (PREFIX_MANDATORY_REPNZ): Likewise.
 606         (PREFIX_MANDATORY_DATA): Likewise.
 607         (PREFIX_MANDATORY_ADDR): Likewise.
 608         (PREFIX_MANDATORY_LOCK): Likewise.
 609         (PREFIX_MANDATORY): Likewise.
 610         (PREFIX_UD_SHIFT): Set to 8
 611         (PREFIX_UD_REPZ): Updated.
 612         (PREFIX_UD_REPNZ): Likewise.
 613         (PREFIX_UD_DATA): Likewise.
 614         (PREFIX_UD_ADDR): Likewise.
 615         (PREFIX_UD_LOCK): Likewise.
 616         (PREFIX_IGNORED_SHIFT): New.
 617         (PREFIX_IGNORED_REPZ): Likewise.
 618         (PREFIX_IGNORED_REPNZ): Likewise.
 619         (PREFIX_IGNORED_DATA): Likewise.
 620         (PREFIX_IGNORED_ADDR): Likewise.
 621         (PREFIX_IGNORED_LOCK): Likewise.
 622         (PREFIX_OPCODE): Likewise.
 623         (PREFIX_IGNORED): Likewise.
 624         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 625         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 626         (three_byte_table): Likewise.
 627         (mod_table): Likewise.
 628         (mandatory_prefix): Renamed to ...
 629         (prefix_requirement): This.
 630         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 631         Update PREFIX_90 entry.
 632         (get_valid_dis386): Check prefix_requirement to see if a prefix
 633         should be ignored.
 634         (print_insn): Replace mandatory_prefix with prefix_requirement.
 635
 636 2015-04-15  Renlin Li  <renlin.li@arm.com>
 637
 638         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 639         use it for ssat and ssat16.
 640         (print_insn_thumb32): Add handle case for 'D' control code.
 641
 642 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 643             H.J. Lu  <hongjiu.lu@intel.com>
 644
 645         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 646         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 647         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 648         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 649         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 650         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 651         Fill prefix_requirement field.
 652         (struct dis386): Add prefix_requirement field.
 653         (dis386): Fill prefix_requirement field.
 654         (dis386_twobyte): Ditto.
 655         (twobyte_has_mandatory_prefix_: Remove.
 656         (reg_table): Fill prefix_requirement field.
 657         (prefix_table): Ditto.
 658         (x86_64_table): Ditto.
 659         (three_byte_table): Ditto.
 660         (xop_table): Ditto.
 661         (vex_table): Ditto.
 662         (vex_len_table): Ditto.
 663         (vex_w_table): Ditto.
 664         (mod_table): Ditto.
 665         (bad_opcode): Ditto.
 666         (print_insn): Use prefix_requirement.
 667         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 668         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 669         (float_reg): Ditto.
 670
 671 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 672
 673         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 674
 675 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 676
 677         * Makefile.in: Regenerated.
 678
 679 2015-03-25  Anton Blanchard  <anton@samba.org>
 680
 681         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 682         powerpc_opcd_indices and vle_opcd_indices once.
 683
 684 2015-03-25  Anton Blanchard  <anton@samba.org>
 685
 686         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 687
 688 2015-03-24  Terry Guo  <terry.guo@arm.com>
 689
 690         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 691         (opcode16): Likewise.
 692         (coprocessor_opcodes): Replace bit with feature struct.
 693         (neon_opcodes): Likewise.
 694         (arm_opcodes): Likewise.
 695         (thumb_opcodes): Likewise.
 696         (thumb32_opcodes): Likewise.
 697         (print_insn_coprocessor): Likewise.
 698         (print_insn_arm): Likewise.
 699         (select_arm_features): Follow new feature struct.
 700
 701 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 702
 703         * i386-dis.c (rm_table): Add clzero.
 704         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 705         Add CPU_CLZERO_FLAGS.
 706         (cpu_flags): Add CpuCLZERO.
 707         * i386-opc.h: Add CpuCLZERO.
 708         * i386-opc.tbl: Add clzero.
 709         * i386-init.h: Re-generated.
 710         * i386-tbl.h: Re-generated.
 711
 712 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 713
 714         * mips-opc.c (decode_mips_operand): Fix constraint issues
 715         with u and y operands.
 716
 717 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 718
 719         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 720
 721 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 722
 723         * s390-opc.c: Add new IBM z13 instructions.
 724         * s390-opc.txt: Likewise.
 725
 726 2015-03-10  Renlin Li  <renlin.li@arm.com>
 727
 728         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 729         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 730         related alias.
 731         * aarch64-asm-2.c: Regenerate.
 732         * aarch64-dis-2.c: Likewise.
 733         * aarch64-opc-2.c: Likewise.
 734
 735 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 736
 737         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 738
 739 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 740
 741         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 742         arch_sh_up.
 743         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 744         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 745
 746 2015-02-23  Vinay  <Vinay.G@kpit.com>
 747
 748         * rl78-decode.opc (MOV): Added space between two operands for
 749         'mov' instruction in index addressing mode.
 750         * rl78-decode.c: Regenerate.
 751
 752 2015-02-19  Pedro Alves  <palves@redhat.com>
 753
 754         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 755
 756 2015-02-10  Pedro Alves  <palves@redhat.com>
 757             Tom Tromey  <tromey@redhat.com>
 758
 759         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 760         microblaze_and, microblaze_xor.
 761         * microblaze-opc.h (opcodes): Adjust.
 762
 763 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 764
 765         * Makefile.am: Add FT32 files.
 766         * configure.ac: Handle FT32.
 767         * disassemble.c (disassembler): Call print_insn_ft32.
 768         * ft32-dis.c: New file.
 769         * ft32-opc.c: New file.
 770         * Makefile.in: Regenerate.
 771         * configure: Regenerate.
 772         * po/POTFILES.in: Regenerate.
 773
 774 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 775
 776         * nds32-asm.c (keyword_sr): Add new system registers.
 777
 778 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 779
 780         * s390-dis.c (s390_extract_operand): Support vector register
 781         operands.
 782         (s390_print_insn_with_opcode): Support new operands types and add
 783         new handling of optional operands.
 784         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 785         and include opcode/s390.h instead.
 786         (struct op_struct): New field `flags'.
 787         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 788         (dumpTable): Dump flags.
 789         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 790         string.
 791         * s390-opc.c: Add new operands types, instruction formats, and
 792         instruction masks.
 793         (s390_opformats): Add new formats for .insn.
 794         * s390-opc.txt: Add new instructions.
 795
 796 2015-01-01  Alan Modra  <amodra@gmail.com>
 797
 798         Update year range in copyright notice of all files.
 799
 800 For older changes see ChangeLog-2014
 801 \f
 802 Copyright (C) 2015 Free Software Foundation, Inc.
 803
 804 Copying and distribution of this file, with or without modification,
 805 are permitted in any medium without royalty provided the copyright
 806 notice and this notice are preserved.
 807
 808 Local Variables:
 809 mode: change-log
 810 left-margin: 8
 811 fill-column: 74
 812 version-control: never
 813 End: