1 2017-10-12 James Bowman <james.bowman@ftdichip.com>
3 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
4 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
5 K15. Add jmpix pattern.
7 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
9 * s390-opc.txt (prno, tpei, irbm): New instructions added.
11 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
13 * s390-opc.c (INSTR_SI_RD): New macro.
14 (INSTR_S_RD): Adjust example instruction.
15 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
18 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
20 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
21 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
22 VLE multimple load/store instructions. Old e_ldm* variants are
24 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
26 2017-09-27 Nick Clifton <nickc@redhat.com>
29 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
30 names for the fmv.x.s and fmv.s.x instructions respectively.
32 2017-09-26 do <do@nerilex.org>
35 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
36 be used on CPUs that have emacs support.
38 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
40 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
42 2017-09-09 Kamil Rytarowski <n54@gmx.com>
44 * nds32-asm.c: Rename __BIT() to N32_BIT().
45 * nds32-asm.h: Likewise.
46 * nds32-dis.c: Likewise.
48 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
50 * i386-dis.c (last_active_prefix): Removed.
51 (ckprefix): Don't set last_active_prefix.
52 (NOTRACK_Fixup): Don't check last_active_prefix.
54 2017-08-31 Nick Clifton <nickc@redhat.com>
56 * po/fr.po: Updated French translation.
58 2017-08-31 James Bowman <james.bowman@ftdichip.com>
60 * ft32-dis.c (print_insn_ft32): Correct display of non-address
63 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
64 Edmar Wienskoski <edmar.wienskoski@nxp.com>
66 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
67 PPC_OPCODE_EFS2 flag to "e200z4" entry.
68 New entries efs2 and spe2.
69 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
70 (SPE2_OPCD_SEGS): New macro.
71 (spe2_opcd_indices): New.
72 (disassemble_init_powerpc): Handle SPE2 opcodes.
73 (lookup_spe2): New function.
74 (print_insn_powerpc): call lookup_spe2.
75 * ppc-opc.c (insert_evuimm1_ex0): New function.
76 (extract_evuimm1_ex0): Likewise.
77 (insert_evuimm_lt8): Likewise.
78 (extract_evuimm_lt8): Likewise.
79 (insert_off_spe2): Likewise.
80 (extract_off_spe2): Likewise.
81 (insert_Ddd): Likewise.
82 (extract_Ddd): Likewise.
84 (EVUIMM_LT8): Likewise.
85 (EVUIMM_LT16): Adjust.
88 (EVUIMM_1_EX0): Likewise.
91 (VX_OFF_SPE2): Likewise.
94 (VX_MASK_DDD): New mask.
96 (VX_RA_CONST): New macro.
97 (VX_RA_CONST_MASK): Likewise.
98 (VX_RB_CONST): Likewise.
99 (VX_RB_CONST_MASK): Likewise.
100 (VX_OFF_SPE2_MASK): Likewise.
101 (VX_SPE_CRFD): Likewise.
102 (VX_SPE_CRFD_MASK VX): Likewise.
103 (VX_SPE2_CLR): Likewise.
104 (VX_SPE2_CLR_MASK): Likewise.
105 (VX_SPE2_SPLATB): Likewise.
106 (VX_SPE2_SPLATB_MASK): Likewise.
107 (VX_SPE2_OCTET): Likewise.
108 (VX_SPE2_OCTET_MASK): Likewise.
109 (VX_SPE2_DDHH): Likewise.
110 (VX_SPE2_DDHH_MASK): Likewise.
111 (VX_SPE2_HH): Likewise.
112 (VX_SPE2_HH_MASK): Likewise.
113 (VX_SPE2_EVMAR): Likewise.
114 (VX_SPE2_EVMAR_MASK): Likewise.
117 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
118 (powerpc_macros): Map old SPE instructions have new names
119 with the same opcodes. Add SPE2 instructions which just are
121 (spe2_opcodes): Add SPE2 opcodes.
123 2017-08-23 Alan Modra <amodra@gmail.com>
125 * ppc-opc.c: Formatting and comment fixes. Move insert and
126 extract functions earlier, deleting forward declarations.
127 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
130 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
132 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
134 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
135 Edmar Wienskoski <edmar.wienskoski@nxp.com>
137 * ppc-opc.c (insert_evuimm2_ex0): New function.
138 (extract_evuimm2_ex0): Likewise.
139 (insert_evuimm4_ex0): Likewise.
140 (extract_evuimm4_ex0): Likewise.
141 (insert_evuimm8_ex0): Likewise.
142 (extract_evuimm8_ex0): Likewise.
143 (insert_evuimm_lt16): Likewise.
144 (extract_evuimm_lt16): Likewise.
145 (insert_rD_rS_even): Likewise.
146 (extract_rD_rS_even): Likewise.
147 (insert_off_lsp): Likewise.
148 (extract_off_lsp): Likewise.
149 (RD_EVEN): New operand.
152 (EVUIMM_LT16): New operand.
154 (EVUIMM_2_EX0): New operand.
156 (EVUIMM_4_EX0): New operand.
158 (EVUIMM_8_EX0): New operand.
160 (VX_OFF): New operand.
162 (VX_LSP_MASK): Likewise.
163 (VX_LSP_OFF_MASK): Likewise.
164 (PPC_OPCODE_LSP): Likewise.
165 (vle_opcodes): Add LSP opcodes.
166 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
168 2017-08-09 Jiong Wang <jiong.wang@arm.com>
170 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
171 register operands in CRC instructions.
172 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
175 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
177 * disassemble.c (disassembler): Mark big and mach with
180 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
182 * disassemble.c (disassembler): Remove arch/mach/endian
185 2017-07-25 Nick Clifton <nickc@redhat.com>
188 * arc-opc.c (insert_rhv2): Use lower case first letter in error
190 (insert_r0): Likewise.
191 (insert_r1): Likewise.
192 (insert_r2): Likewise.
193 (insert_r3): Likewise.
194 (insert_sp): Likewise.
195 (insert_gp): Likewise.
196 (insert_pcl): Likewise.
197 (insert_blink): Likewise.
198 (insert_ilink1): Likewise.
199 (insert_ilink2): Likewise.
200 (insert_ras): Likewise.
201 (insert_rbs): Likewise.
202 (insert_rcs): Likewise.
203 (insert_simm3s): Likewise.
204 (insert_rrange): Likewise.
205 (insert_r13el): Likewise.
206 (insert_fpel): Likewise.
207 (insert_blinkel): Likewise.
208 (insert_pclel): Likewise.
209 (insert_nps_bitop_size_2b): Likewise.
210 (insert_nps_imm_offset): Likewise.
211 (insert_nps_imm_entry): Likewise.
212 (insert_nps_size_16bit): Likewise.
213 (insert_nps_##NAME##_pos): Likewise.
214 (insert_nps_##NAME): Likewise.
215 (insert_nps_bitop_ins_ext): Likewise.
216 (insert_nps_##NAME): Likewise.
217 (insert_nps_min_hofs): Likewise.
218 (insert_nps_##NAME): Likewise.
219 (insert_nps_rbdouble_64): Likewise.
220 (insert_nps_misc_imm_offset): Likewise.
221 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
224 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
225 Jiong Wang <jiong.wang@arm.com>
227 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
229 * aarch64-dis-2.c: Regenerated.
231 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
233 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
236 2017-07-20 Nick Clifton <nickc@redhat.com>
238 * po/de.po: Updated German translation.
240 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
242 * arc-regs.h (sec_stat): New aux register.
243 (aux_kernel_sp): Likewise.
244 (aux_sec_u_sp): Likewise.
245 (aux_sec_k_sp): Likewise.
246 (sec_vecbase_build): Likewise.
247 (nsc_table_top): Likewise.
248 (nsc_table_base): Likewise.
249 (ersec_stat): Likewise.
250 (aux_sec_except): Likewise.
252 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
254 * arc-opc.c (extract_uimm12_20): New function.
255 (UIMM12_20): New operand.
257 * arc-tbl.h (sjli): Add new instruction.
259 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
260 John Eric Martin <John.Martin@emmicro-us.com>
262 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
263 (UIMM3_23): Adjust accordingly.
264 * arc-regs.h: Add/correct jli_base register.
265 * arc-tbl.h (jli_s): Likewise.
267 2017-07-18 Nick Clifton <nickc@redhat.com>
270 * aarch64-opc.c: Fix spelling typos.
271 * i386-dis.c: Likewise.
273 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
275 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
276 max_addr_offset and octets variables to size_t.
278 2017-07-12 Alan Modra <amodra@gmail.com>
280 * po/da.po: Update from translationproject.org/latest/opcodes/.
281 * po/de.po: Likewise.
282 * po/es.po: Likewise.
283 * po/fi.po: Likewise.
284 * po/fr.po: Likewise.
285 * po/id.po: Likewise.
286 * po/it.po: Likewise.
287 * po/nl.po: Likewise.
288 * po/pt_BR.po: Likewise.
289 * po/ro.po: Likewise.
290 * po/sv.po: Likewise.
291 * po/tr.po: Likewise.
292 * po/uk.po: Likewise.
293 * po/vi.po: Likewise.
294 * po/zh_CN.po: Likewise.
296 2017-07-11 Yao Qi <yao.qi@linaro.org>
297 Alan Modra <amodra@gmail.com>
299 * cgen.sh: Mark generated files read-only.
300 * epiphany-asm.c: Regenerate.
301 * epiphany-desc.c: Regenerate.
302 * epiphany-desc.h: Regenerate.
303 * epiphany-dis.c: Regenerate.
304 * epiphany-ibld.c: Regenerate.
305 * epiphany-opc.c: Regenerate.
306 * epiphany-opc.h: Regenerate.
307 * fr30-asm.c: Regenerate.
308 * fr30-desc.c: Regenerate.
309 * fr30-desc.h: Regenerate.
310 * fr30-dis.c: Regenerate.
311 * fr30-ibld.c: Regenerate.
312 * fr30-opc.c: Regenerate.
313 * fr30-opc.h: Regenerate.
314 * frv-asm.c: Regenerate.
315 * frv-desc.c: Regenerate.
316 * frv-desc.h: Regenerate.
317 * frv-dis.c: Regenerate.
318 * frv-ibld.c: Regenerate.
319 * frv-opc.c: Regenerate.
320 * frv-opc.h: Regenerate.
321 * ip2k-asm.c: Regenerate.
322 * ip2k-desc.c: Regenerate.
323 * ip2k-desc.h: Regenerate.
324 * ip2k-dis.c: Regenerate.
325 * ip2k-ibld.c: Regenerate.
326 * ip2k-opc.c: Regenerate.
327 * ip2k-opc.h: Regenerate.
328 * iq2000-asm.c: Regenerate.
329 * iq2000-desc.c: Regenerate.
330 * iq2000-desc.h: Regenerate.
331 * iq2000-dis.c: Regenerate.
332 * iq2000-ibld.c: Regenerate.
333 * iq2000-opc.c: Regenerate.
334 * iq2000-opc.h: Regenerate.
335 * lm32-asm.c: Regenerate.
336 * lm32-desc.c: Regenerate.
337 * lm32-desc.h: Regenerate.
338 * lm32-dis.c: Regenerate.
339 * lm32-ibld.c: Regenerate.
340 * lm32-opc.c: Regenerate.
341 * lm32-opc.h: Regenerate.
342 * lm32-opinst.c: Regenerate.
343 * m32c-asm.c: Regenerate.
344 * m32c-desc.c: Regenerate.
345 * m32c-desc.h: Regenerate.
346 * m32c-dis.c: Regenerate.
347 * m32c-ibld.c: Regenerate.
348 * m32c-opc.c: Regenerate.
349 * m32c-opc.h: Regenerate.
350 * m32r-asm.c: Regenerate.
351 * m32r-desc.c: Regenerate.
352 * m32r-desc.h: Regenerate.
353 * m32r-dis.c: Regenerate.
354 * m32r-ibld.c: Regenerate.
355 * m32r-opc.c: Regenerate.
356 * m32r-opc.h: Regenerate.
357 * m32r-opinst.c: Regenerate.
358 * mep-asm.c: Regenerate.
359 * mep-desc.c: Regenerate.
360 * mep-desc.h: Regenerate.
361 * mep-dis.c: Regenerate.
362 * mep-ibld.c: Regenerate.
363 * mep-opc.c: Regenerate.
364 * mep-opc.h: Regenerate.
365 * mt-asm.c: Regenerate.
366 * mt-desc.c: Regenerate.
367 * mt-desc.h: Regenerate.
368 * mt-dis.c: Regenerate.
369 * mt-ibld.c: Regenerate.
370 * mt-opc.c: Regenerate.
371 * mt-opc.h: Regenerate.
372 * or1k-asm.c: Regenerate.
373 * or1k-desc.c: Regenerate.
374 * or1k-desc.h: Regenerate.
375 * or1k-dis.c: Regenerate.
376 * or1k-ibld.c: Regenerate.
377 * or1k-opc.c: Regenerate.
378 * or1k-opc.h: Regenerate.
379 * or1k-opinst.c: Regenerate.
380 * xc16x-asm.c: Regenerate.
381 * xc16x-desc.c: Regenerate.
382 * xc16x-desc.h: Regenerate.
383 * xc16x-dis.c: Regenerate.
384 * xc16x-ibld.c: Regenerate.
385 * xc16x-opc.c: Regenerate.
386 * xc16x-opc.h: Regenerate.
387 * xstormy16-asm.c: Regenerate.
388 * xstormy16-desc.c: Regenerate.
389 * xstormy16-desc.h: Regenerate.
390 * xstormy16-dis.c: Regenerate.
391 * xstormy16-ibld.c: Regenerate.
392 * xstormy16-opc.c: Regenerate.
393 * xstormy16-opc.h: Regenerate.
395 2017-07-07 Alan Modra <amodra@gmail.com>
397 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
398 * m32c-dis.c: Regenerate.
399 * mep-dis.c: Regenerate.
401 2017-07-05 Borislav Petkov <bp@suse.de>
403 * i386-dis.c: Enable ModRM.reg /6 aliases.
405 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
407 * opcodes/arm-dis.c: Support MVFR2 in disassembly
410 2017-07-04 Tristan Gingold <gingold@adacore.com>
412 * configure: Regenerate.
414 2017-07-03 Tristan Gingold <gingold@adacore.com>
416 * po/opcodes.pot: Regenerate.
418 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
420 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
421 entries to the MSA ASE instruction block.
423 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
424 Maciej W. Rozycki <macro@imgtec.com>
426 * micromips-opc.c (XPA, XPAVZ): New macros.
427 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
430 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
431 Maciej W. Rozycki <macro@imgtec.com>
433 * micromips-opc.c (I36): New macro.
434 (micromips_opcodes): Add "eretnc".
436 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
437 Andrew Bennett <andrew.bennett@imgtec.com>
439 * mips-dis.c (mips_calculate_combination_ases): Handle the
441 (parse_mips_ase_option): New function.
442 (parse_mips_dis_option): Factor out ASE option handling to the
443 new function. Call `mips_calculate_combination_ases'.
444 * mips-opc.c (XPAVZ): New macro.
445 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
446 "mfhgc0", "mthc0" and "mthgc0".
448 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
450 * mips-dis.c (mips_calculate_combination_ases): New function.
451 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
452 calculation to the new function.
453 (set_default_mips_dis_options): Call the new function.
455 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
457 * arc-dis.c (parse_disassembler_options): Use
458 FOR_EACH_DISASSEMBLER_OPTION.
460 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
462 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
463 disassembler option strings.
464 (parse_cpu_option): Likewise.
466 2017-06-28 Tamar Christina <tamar.christina@arm.com>
468 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
469 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
470 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
471 (aarch64_feature_dotprod, DOT_INSN): New.
473 * aarch64-dis-2.c: Regenerated.
475 2017-06-28 Jiong Wang <jiong.wang@arm.com>
477 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
479 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
480 Matthew Fortune <matthew.fortune@imgtec.com>
481 Andrew Bennett <andrew.bennett@imgtec.com>
483 * mips-formats.h (INT_BIAS): New macro.
484 (INT_ADJ): Redefine in INT_BIAS terms.
485 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
486 (mips_print_save_restore): New function.
487 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
488 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
490 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
491 (print_mips16_insn_arg): Call `mips_print_save_restore' for
492 OP_SAVE_RESTORE_LIST handling, factored out from here.
493 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
494 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
495 (mips_builtin_opcodes): Add "restore" and "save" entries.
496 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
498 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
500 2017-06-23 Andrew Waterman <andrew@sifive.com>
502 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
503 alias; do not mark SLTI instruction as an alias.
505 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
507 * i386-dis.c (RM_0FAE_REG_5): Removed.
508 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
509 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
510 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
511 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
512 PREFIX_MOD_3_0F01_REG_5_RM_0.
513 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
514 PREFIX_MOD_3_0FAE_REG_5.
515 (mod_table): Update MOD_0FAE_REG_5.
516 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
517 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
518 * i386-tbl.h: Regenerated.
520 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
522 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
523 * i386-opc.tbl: Likewise.
524 * i386-tbl.h: Regenerated.
526 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
528 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
530 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
533 2017-06-19 Nick Clifton <nickc@redhat.com>
536 * score-dis.c (score_opcodes): Add sentinel.
538 2017-06-16 Alan Modra <amodra@gmail.com>
540 * rx-decode.c: Regenerate.
542 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
545 * i386-dis.c (OP_E_register): Check valid bnd register.
548 2017-06-15 Nick Clifton <nickc@redhat.com>
551 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
554 2017-06-15 Nick Clifton <nickc@redhat.com>
557 * rl78-decode.opc (OP_BUF_LEN): Define.
558 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
559 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
561 * rl78-decode.c: Regenerate.
563 2017-06-15 Nick Clifton <nickc@redhat.com>
566 * bfin-dis.c (gregs): Clip index to prevent overflow.
571 2017-06-14 Nick Clifton <nickc@redhat.com>
574 * score7-dis.c (score_opcodes): Add sentinel.
576 2017-06-14 Yao Qi <yao.qi@linaro.org>
578 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
579 * arm-dis.c: Likewise.
580 * ia64-dis.c: Likewise.
581 * mips-dis.c: Likewise.
582 * spu-dis.c: Likewise.
583 * disassemble.h (print_insn_aarch64): New declaration, moved from
585 (print_insn_big_arm, print_insn_big_mips): Likewise.
586 (print_insn_i386, print_insn_ia64): Likewise.
587 (print_insn_little_arm, print_insn_little_mips): Likewise.
589 2017-06-14 Nick Clifton <nickc@redhat.com>
592 * rx-decode.opc: Include libiberty.h
593 (GET_SCALE): New macro - validates access to SCALE array.
594 (GET_PSCALE): New macro - validates access to PSCALE array.
595 (DIs, SIs, S2Is, rx_disp): Use new macros.
596 * rx-decode.c: Regenerate.
598 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
600 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
602 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
604 * arc-dis.c (enforced_isa_mask): Declare.
605 (cpu_types): Likewise.
606 (parse_cpu_option): New function.
607 (parse_disassembler_options): Use it.
608 (print_insn_arc): Use enforced_isa_mask.
609 (print_arc_disassembler_options): Document new options.
611 2017-05-24 Yao Qi <yao.qi@linaro.org>
613 * alpha-dis.c: Include disassemble.h, don't include
615 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
616 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
617 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
618 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
619 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
620 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
621 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
622 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
623 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
624 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
625 * moxie-dis.c, msp430-dis.c, mt-dis.c:
626 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
627 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
628 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
629 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
630 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
631 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
632 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
633 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
634 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
635 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
636 * z80-dis.c, z8k-dis.c: Likewise.
637 * disassemble.h: New file.
639 2017-05-24 Yao Qi <yao.qi@linaro.org>
641 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
642 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
644 2017-05-24 Yao Qi <yao.qi@linaro.org>
646 * disassemble.c (disassembler): Add arguments a, big and mach.
649 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
651 * i386-dis.c (NOTRACK_Fixup): New.
653 (NOTRACK_PREFIX): Likewise.
654 (last_active_prefix): Likewise.
655 (reg_table): Use NOTRACK on indirect call and jmp.
656 (ckprefix): Set last_active_prefix.
657 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
658 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
659 * i386-opc.h (NoTrackPrefixOk): New.
660 (i386_opcode_modifier): Add notrackprefixok.
661 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
663 * i386-tbl.h: Regenerated.
665 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
667 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
669 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
671 (print_insn_sparc): Handle new operand types.
672 * sparc-opc.c (MASK_M8): Define.
674 (v6notlet): Likewise.
685 (v9andleon): Likewise.
688 (HWS2_VM8): Likewise.
689 (sparc_opcode_archs): Add entry for "m8".
690 (sparc_opcodes): Add OSA2017 and M8 instructions
691 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
693 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
694 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
695 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
696 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
697 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
698 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
699 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
700 ASI_CORE_SELECT_COMMIT_NHT.
702 2017-05-18 Alan Modra <amodra@gmail.com>
704 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
705 * aarch64-dis.c: Likewise.
706 * aarch64-gen.c: Likewise.
707 * aarch64-opc.c: Likewise.
709 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
710 Matthew Fortune <matthew.fortune@imgtec.com>
712 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
713 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
714 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
715 (print_insn_arg) <OP_REG28>: Add handler.
716 (validate_insn_args) <OP_REG28>: Handle.
717 (print_mips16_insn_arg): Handle MIPS16 instructions that require
718 32-bit encoding and 9-bit immediates.
719 (print_insn_mips16): Handle MIPS16 instructions that require
720 32-bit encoding and MFC0/MTC0 operand decoding.
721 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
722 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
723 (RD_C0, WR_C0, E2, E2MT): New macros.
724 (mips16_opcodes): Add entries for MIPS16e2 instructions:
725 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
726 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
727 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
728 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
729 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
730 instructions, "swl", "swr", "sync" and its "sync_acquire",
731 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
732 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
733 regular/extended entries for original MIPS16 ISA revision
734 instructions whose extended forms are subdecoded in the MIPS16e2
735 ISA revision: "li", "sll" and "srl".
737 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
739 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
740 reference in CP0 move operand decoding.
742 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
744 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
746 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
748 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
750 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
751 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
752 "sync_rmb" and "sync_wmb" as aliases.
753 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
754 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
756 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
758 * arc-dis.c (parse_option): Update quarkse_em option..
759 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
761 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
763 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
765 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
767 2017-05-01 Michael Clark <michaeljclark@mac.com>
769 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
772 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
774 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
775 and branches and not synthetic data instructions.
777 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
779 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
781 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
783 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
784 * arc-opc.c (insert_r13el): New function.
786 * arc-tbl.h: Add new enter/leave variants.
788 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
790 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
792 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
794 * mips-dis.c (print_mips_disassembler_options): Add
797 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
799 * mips16-opc.c (AL): New macro.
800 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
801 of "ld" and "lw" as aliases.
803 2017-04-24 Tamar Christina <tamar.christina@arm.com>
805 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
808 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
809 Alan Modra <amodra@gmail.com>
811 * ppc-opc.c (ELEV): Define.
812 (vle_opcodes): Add se_rfgi and e_sc.
813 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
816 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
818 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
820 2017-04-21 Nick Clifton <nickc@redhat.com>
823 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
826 2017-04-13 Alan Modra <amodra@gmail.com>
828 * epiphany-desc.c: Regenerate.
829 * fr30-desc.c: Regenerate.
830 * frv-desc.c: Regenerate.
831 * ip2k-desc.c: Regenerate.
832 * iq2000-desc.c: Regenerate.
833 * lm32-desc.c: Regenerate.
834 * m32c-desc.c: Regenerate.
835 * m32r-desc.c: Regenerate.
836 * mep-desc.c: Regenerate.
837 * mt-desc.c: Regenerate.
838 * or1k-desc.c: Regenerate.
839 * xc16x-desc.c: Regenerate.
840 * xstormy16-desc.c: Regenerate.
842 2017-04-11 Alan Modra <amodra@gmail.com>
844 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
845 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
846 PPC_OPCODE_TMR for e6500.
847 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
848 (PPCVEC3): Define as PPC_OPCODE_POWER9.
849 (PPCVSX2): Define as PPC_OPCODE_POWER8.
850 (PPCVSX3): Define as PPC_OPCODE_POWER9.
851 (PPCHTM): Define as PPC_OPCODE_POWER8.
852 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
854 2017-04-10 Alan Modra <amodra@gmail.com>
856 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
857 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
858 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
859 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
861 2017-04-09 Pip Cet <pipcet@gmail.com>
863 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
864 appropriate floating-point precision directly.
866 2017-04-07 Alan Modra <amodra@gmail.com>
868 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
869 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
870 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
871 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
872 vector instructions with E6500 not PPCVEC2.
874 2017-04-06 Pip Cet <pipcet@gmail.com>
876 * Makefile.am: Add wasm32-dis.c.
877 * configure.ac: Add wasm32-dis.c to wasm32 target.
878 * disassemble.c: Add wasm32 disassembler code.
879 * wasm32-dis.c: New file.
880 * Makefile.in: Regenerate.
881 * configure: Regenerate.
882 * po/POTFILES.in: Regenerate.
883 * po/opcodes.pot: Regenerate.
885 2017-04-05 Pedro Alves <palves@redhat.com>
887 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
888 * arm-dis.c (parse_arm_disassembler_options): Constify.
889 * ppc-dis.c (powerpc_init_dialect): Constify local.
890 * vax-dis.c (parse_disassembler_options): Constify.
892 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
894 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
897 2017-03-30 Pip Cet <pipcet@gmail.com>
899 * configure.ac: Add (empty) bfd_wasm32_arch target.
900 * configure: Regenerate
901 * po/opcodes.pot: Regenerate.
903 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
905 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
907 * opcodes/sparc-opc.c (asi_table): New ASIs.
909 2017-03-29 Alan Modra <amodra@gmail.com>
911 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
913 (lookup_powerpc): Don't special case -1 dialect. Handle
915 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
916 lookup_powerpc call, pass it on second.
918 2017-03-27 Alan Modra <amodra@gmail.com>
921 * ppc-dis.c (struct ppc_mopt): Comment.
922 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
924 2017-03-27 Rinat Zelig <rinat@mellanox.com>
926 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
927 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
928 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
929 (insert_nps_misc_imm_offset): New function.
930 (extract_nps_misc imm_offset): New function.
931 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
932 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
934 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
936 * s390-mkopc.c (main): Remove vx2 check.
937 * s390-opc.txt: Remove vx2 instruction flags.
939 2017-03-21 Rinat Zelig <rinat@mellanox.com>
941 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
942 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
943 (insert_nps_imm_offset): New function.
944 (extract_nps_imm_offset): New function.
945 (insert_nps_imm_entry): New function.
946 (extract_nps_imm_entry): New function.
948 2017-03-17 Alan Modra <amodra@gmail.com>
951 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
952 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
953 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
955 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
957 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
961 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
963 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
965 2017-03-13 Andrew Waterman <andrew@sifive.com>
967 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
972 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
974 * i386-gen.c (opcode_modifiers): Replace S with Load.
975 * i386-opc.h (S): Removed.
977 (i386_opcode_modifier): Replace s with load.
978 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
979 and {evex}. Replace S with Load.
980 * i386-tbl.h: Regenerated.
982 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
984 * i386-opc.tbl: Use CpuCET on rdsspq.
985 * i386-tbl.h: Regenerated.
987 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
989 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
990 <vsx>: Do not use PPC_OPCODE_VSX3;
992 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
994 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
996 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
998 * i386-dis.c (REG_0F1E_MOD_3): New enum.
999 (MOD_0F1E_PREFIX_1): Likewise.
1000 (MOD_0F38F5_PREFIX_2): Likewise.
1001 (MOD_0F38F6_PREFIX_0): Likewise.
1002 (RM_0F1E_MOD_3_REG_7): Likewise.
1003 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1004 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1005 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1006 (PREFIX_0F1E): Likewise.
1007 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1008 (PREFIX_0F38F5): Likewise.
1009 (dis386_twobyte): Use PREFIX_0F1E.
1010 (reg_table): Add REG_0F1E_MOD_3.
1011 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1012 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1013 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1014 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1015 (three_byte_table): Use PREFIX_0F38F5.
1016 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1017 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1018 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1019 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1020 PREFIX_MOD_3_0F01_REG_5_RM_2.
1021 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1022 (cpu_flags): Add CpuCET.
1023 * i386-opc.h (CpuCET): New enum.
1024 (CpuUnused): Commented out.
1025 (i386_cpu_flags): Add cpucet.
1026 * i386-opc.tbl: Add Intel CET instructions.
1027 * i386-init.h: Regenerated.
1028 * i386-tbl.h: Likewise.
1030 2017-03-06 Alan Modra <amodra@gmail.com>
1033 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1034 (extract_raq, extract_ras, extract_rbx): New functions.
1035 (powerpc_operands): Use opposite corresponding insert function.
1037 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1038 register restriction.
1040 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1042 * disassemble.c Include "safe-ctype.h".
1043 (disassemble_init_for_target): Handle s390 init.
1044 (remove_whitespace_and_extra_commas): New function.
1045 (disassembler_options_cmp): Likewise.
1046 * arm-dis.c: Include "libiberty.h".
1048 (regnames): Use long disassembler style names.
1049 Add force-thumb and no-force-thumb options.
1050 (NUM_ARM_REGNAMES): Rename from this...
1051 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1052 (get_arm_regname_num_options): Delete.
1053 (set_arm_regname_option): Likewise.
1054 (get_arm_regnames): Likewise.
1055 (parse_disassembler_options): Likewise.
1056 (parse_arm_disassembler_option): Rename from this...
1057 (parse_arm_disassembler_options): ...to this. Make static.
1058 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1059 (print_insn): Use parse_arm_disassembler_options.
1060 (disassembler_options_arm): New function.
1061 (print_arm_disassembler_options): Handle updated regnames.
1062 * ppc-dis.c: Include "libiberty.h".
1063 (ppc_opts): Add "32" and "64" entries.
1064 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1065 (powerpc_init_dialect): Add break to switch statement.
1066 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1067 (disassembler_options_powerpc): New function.
1068 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1069 Remove printing of "32" and "64".
1070 * s390-dis.c: Include "libiberty.h".
1071 (init_flag): Remove unneeded variable.
1072 (struct s390_options_t): New structure type.
1073 (options): New structure.
1074 (init_disasm): Rename from this...
1075 (disassemble_init_s390): ...to this. Add initializations for
1076 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1077 (print_insn_s390): Delete call to init_disasm.
1078 (disassembler_options_s390): New function.
1079 (print_s390_disassembler_options): Print using information from
1081 * po/opcodes.pot: Regenerate.
1083 2017-02-28 Jan Beulich <jbeulich@suse.com>
1085 * i386-dis.c (PCMPESTR_Fixup): New.
1086 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1087 (prefix_table): Use PCMPESTR_Fixup.
1088 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1090 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1091 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1092 Split 64-bit and non-64-bit variants.
1093 * opcodes/i386-tbl.h: Re-generate.
1095 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1097 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1098 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1099 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1100 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1101 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1102 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1103 (OP_SVE_V_HSD): New macros.
1104 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1105 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1106 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1107 (aarch64_opcode_table): Add new SVE instructions.
1108 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1109 for rotation operands. Add new SVE operands.
1110 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1111 (ins_sve_quad_index): Likewise.
1112 (ins_imm_rotate): Split into...
1113 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1114 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1115 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1117 (aarch64_ins_sve_addr_ri_s4): New function.
1118 (aarch64_ins_sve_quad_index): Likewise.
1119 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1120 * aarch64-asm-2.c: Regenerate.
1121 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1122 (ext_sve_quad_index): Likewise.
1123 (ext_imm_rotate): Split into...
1124 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1125 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1126 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1128 (aarch64_ext_sve_addr_ri_s4): New function.
1129 (aarch64_ext_sve_quad_index): Likewise.
1130 (aarch64_ext_sve_index): Allow quad indices.
1131 (do_misc_decoding): Likewise.
1132 * aarch64-dis-2.c: Regenerate.
1133 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1134 aarch64_field_kinds.
1135 (OPD_F_OD_MASK): Widen by one bit.
1136 (OPD_F_NO_ZR): Bump accordingly.
1137 (get_operand_field_width): New function.
1138 * aarch64-opc.c (fields): Add new SVE fields.
1139 (operand_general_constraint_met_p): Handle new SVE operands.
1140 (aarch64_print_operand): Likewise.
1141 * aarch64-opc-2.c: Regenerate.
1143 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1145 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1146 (aarch64_feature_compnum): ...this.
1147 (SIMD_V8_3): Replace with...
1149 (CNUM_INSN): New macro.
1150 (aarch64_opcode_table): Use it for the complex number instructions.
1152 2017-02-24 Jan Beulich <jbeulich@suse.com>
1154 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1156 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1158 Add support for associating SPARC ASIs with an architecture level.
1159 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1160 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1161 decoding of SPARC ASIs.
1163 2017-02-23 Jan Beulich <jbeulich@suse.com>
1165 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1166 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1168 2017-02-21 Jan Beulich <jbeulich@suse.com>
1170 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1171 1 (instead of to itself). Correct typo.
1173 2017-02-14 Andrew Waterman <andrew@sifive.com>
1175 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1178 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1180 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1181 (aarch64_sys_reg_supported_p): Handle them.
1183 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1185 * arc-opc.c (UIMM6_20R): Define.
1186 (SIMM12_20): Use above.
1187 (SIMM12_20R): Define.
1188 (SIMM3_5_S): Use above.
1189 (UIMM7_A32_11R_S): Define.
1190 (UIMM7_9_S): Use above.
1191 (UIMM3_13R_S): Define.
1192 (SIMM11_A32_7_S): Use above.
1194 (UIMM10_A32_8_S): Use above.
1195 (UIMM8_8R_S): Define.
1197 (arc_relax_opcodes): Use all above defines.
1199 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1201 * arc-regs.h: Distinguish some of the registers different on
1202 ARC700 and HS38 cpus.
1204 2017-02-14 Alan Modra <amodra@gmail.com>
1207 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1208 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1210 2017-02-11 Stafford Horne <shorne@gmail.com>
1211 Alan Modra <amodra@gmail.com>
1213 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1214 Use insn_bytes_value and insn_int_value directly instead. Don't
1215 free allocated memory until function exit.
1217 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1219 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1221 2017-02-03 Nick Clifton <nickc@redhat.com>
1224 * aarch64-opc.c (print_register_list): Ensure that the register
1225 list index will fir into the tb buffer.
1226 (print_register_offset_address): Likewise.
1227 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1229 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1232 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1233 instructions when the previous fetch packet ends with a 32-bit
1236 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1238 * pru-opc.c: Remove vague reference to a future GDB port.
1240 2017-01-20 Nick Clifton <nickc@redhat.com>
1242 * po/ga.po: Updated Irish translation.
1244 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1246 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1248 2017-01-13 Yao Qi <yao.qi@linaro.org>
1250 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1251 if FETCH_DATA returns 0.
1252 (m68k_scan_mask): Likewise.
1253 (print_insn_m68k): Update code to handle -1 return value.
1255 2017-01-13 Yao Qi <yao.qi@linaro.org>
1257 * m68k-dis.c (enum print_insn_arg_error): New.
1258 (NEXTBYTE): Replace -3 with
1259 PRINT_INSN_ARG_MEMORY_ERROR.
1260 (NEXTULONG): Likewise.
1261 (NEXTSINGLE): Likewise.
1262 (NEXTDOUBLE): Likewise.
1263 (NEXTDOUBLE): Likewise.
1264 (NEXTPACKED): Likewise.
1265 (FETCH_ARG): Likewise.
1266 (FETCH_DATA): Update comments.
1267 (print_insn_arg): Update comments. Replace magic numbers with
1269 (match_insn_m68k): Likewise.
1271 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1273 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1274 * i386-dis-evex.h (evex_table): Updated.
1275 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1276 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1277 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1278 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1279 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1280 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1281 * i386-init.h: Regenerate.
1282 * i386-tbl.h: Ditto.
1284 2017-01-12 Yao Qi <yao.qi@linaro.org>
1286 * msp430-dis.c (msp430_singleoperand): Return -1 if
1287 msp430dis_opcode_signed returns false.
1288 (msp430_doubleoperand): Likewise.
1289 (msp430_branchinstr): Return -1 if
1290 msp430dis_opcode_unsigned returns false.
1291 (msp430x_calla_instr): Likewise.
1292 (print_insn_msp430): Likewise.
1294 2017-01-05 Nick Clifton <nickc@redhat.com>
1297 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1298 could not be matched.
1299 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1302 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1304 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1305 (aarch64_opcode_table): Use RCPC_INSN.
1307 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1309 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1311 * riscv-opcodes/all-opcodes: Likewise.
1313 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1315 * riscv-dis.c (print_insn_args): Add fall through comment.
1317 2017-01-03 Nick Clifton <nickc@redhat.com>
1319 * po/sr.po: New Serbian translation.
1320 * configure.ac (ALL_LINGUAS): Add sr.
1321 * configure: Regenerate.
1323 2017-01-02 Alan Modra <amodra@gmail.com>
1325 * epiphany-desc.h: Regenerate.
1326 * epiphany-opc.h: Regenerate.
1327 * fr30-desc.h: Regenerate.
1328 * fr30-opc.h: Regenerate.
1329 * frv-desc.h: Regenerate.
1330 * frv-opc.h: Regenerate.
1331 * ip2k-desc.h: Regenerate.
1332 * ip2k-opc.h: Regenerate.
1333 * iq2000-desc.h: Regenerate.
1334 * iq2000-opc.h: Regenerate.
1335 * lm32-desc.h: Regenerate.
1336 * lm32-opc.h: Regenerate.
1337 * m32c-desc.h: Regenerate.
1338 * m32c-opc.h: Regenerate.
1339 * m32r-desc.h: Regenerate.
1340 * m32r-opc.h: Regenerate.
1341 * mep-desc.h: Regenerate.
1342 * mep-opc.h: Regenerate.
1343 * mt-desc.h: Regenerate.
1344 * mt-opc.h: Regenerate.
1345 * or1k-desc.h: Regenerate.
1346 * or1k-opc.h: Regenerate.
1347 * xc16x-desc.h: Regenerate.
1348 * xc16x-opc.h: Regenerate.
1349 * xstormy16-desc.h: Regenerate.
1350 * xstormy16-opc.h: Regenerate.
1352 2017-01-02 Alan Modra <amodra@gmail.com>
1354 Update year range in copyright notice of all files.
1356 For older changes see ChangeLog-2016
1358 Copyright (C) 2017 Free Software Foundation, Inc.
1360 Copying and distribution of this file, with or without modification,
1361 are permitted in any medium without royalty provided the copyright
1362 notice and this notice are preserved.
1368 version-control: never