opcodes/ChangeLog

   1 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
   2 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
   3
   4         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
   5         in reglane special case.
   6         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
   7         aarch64_find_next_opcode): Account for new instructions.
   8         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
   9         in reglane special case.
  10         * aarch64-opc.c (struct operand_qualifier_data): Add data for
  11         new AARCH64_OPND_QLF_S_2H qualifier.
  12         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
  13         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
  14         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
  15         sets.
  16         (BFLOAT_SVE, BFLOAT): New feature set macros.
  17         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
  18         instructions.
  19         (aarch64_opcode_table): Define new instructions bfdot,
  20         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
  21         bfcvtn2, bfcvt.
  22
  23 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  24 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  25
  26         * aarch64-tbl.h (ARMV8_6): New macro.
  27
  28 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-dis.c (prefix_table): Add mcommit.
  31         (rm_table): Add rdpru.
  32         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
  33         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
  34         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
  35         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
  36         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
  37         * i386-opc.tbl (mcommit, rdpru): New.
  38         * i386-init.h, i386-tbl.h: Re-generate.
  39
  40 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-dis.c (OP_Mwait): Drop local variable "names", use
  43         "names32" instead.
  44         (OP_Monitor): Drop local variable "op1_names", re-purpose
  45         "names" for it instead, and replace former "names" uses by
  46         "names32" ones.
  47
  48 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  49
  50         PR/gas 25167
  51         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
  52         operand-less forms.
  53         * opcodes/i386-tbl.h: Re-generate.
  54
  55 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-dis.c (OP_Mwaitx): Delete.
  58         (prefix_table): Use OP_Mwait for mwaitx entry.
  59         (OP_Mwait): Also handle mwaitx.
  60
  61 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
  64         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
  65         (prefix_table): Add respective entries.
  66         (rm_table): Link to those entries.
  67
  68 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  69
  70         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
  71         (REG_0F1C_P_0_MOD_0): ... this.
  72         (REG_0F1E_MOD_3): Rename to ...
  73         (REG_0F1E_P_1_MOD_3): ... this.
  74         (RM_0F01_REG_5): Rename to ...
  75         (RM_0F01_REG_5_MOD_3): ... this.
  76         (RM_0F01_REG_7): Rename to ...
  77         (RM_0F01_REG_7_MOD_3): ... this.
  78         (RM_0F1E_MOD_3_REG_7): Rename to ...
  79         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
  80         (RM_0FAE_REG_6): Rename to ...
  81         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
  82         (RM_0FAE_REG_7): Rename to ...
  83         (RM_0FAE_REG_7_MOD_3): ... this.
  84         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
  85         (PREFIX_0F01_REG_5_MOD_0): ... this.
  86         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
  87         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
  88         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
  89         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
  90         (PREFIX_0FAE_REG_0): Rename to ...
  91         (PREFIX_0FAE_REG_0_MOD_3): ... this.
  92         (PREFIX_0FAE_REG_1): Rename to ...
  93         (PREFIX_0FAE_REG_1_MOD_3): ... this.
  94         (PREFIX_0FAE_REG_2): Rename to ...
  95         (PREFIX_0FAE_REG_2_MOD_3): ... this.
  96         (PREFIX_0FAE_REG_3): Rename to ...
  97         (PREFIX_0FAE_REG_3_MOD_3): ... this.
  98         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
  99         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 100         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 101         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 102         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 103         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 104         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 105         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 106         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 107         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 108         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 109         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 110         (PREFIX_0FAE_REG_7): Rename to ...
 111         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 112         (PREFIX_MOD_0_0FC3): Rename to ...
 113         (PREFIX_0FC3_MOD_0): ... this.
 114         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 115         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 116         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 117         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 118         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 119         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 120         (reg_table, prefix_table, mod_table, rm_table): Adjust
 121         accordingly.
 122
 123 2019-11-04  Nick Clifton  <nickc@redhat.com>
 124
 125         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 126         of a v850 system register.  Move the v850_sreg_names array into
 127         this function.
 128         (get_v850_reg_name): Likewise for ordinary register names.
 129         (get_v850_vreg_name): Likewise for vector register names.
 130         (get_v850_cc_name): Likewise for condition codes.
 131         * get_v850_float_cc_name): Likewise for floating point condition
 132         codes.
 133         (get_v850_cacheop_name): Likewise for cache-ops.
 134         (get_v850_prefop_name): Likewise for pref-ops.
 135         (disassemble): Use the new accessor functions.
 136
 137 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 138
 139         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 140         immediate for the writeback form of ldraa/ldrab if it is 0.
 141         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 142         * aarch64-opc-2.c: Regenerated.
 143
 144 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 145
 146         * i386-gen.c (operand_type_shorthands): Delete.
 147         (operand_type_init): Expand previous shorthands.
 148         (set_bitfield_from_shorthand): Rename back to ...
 149         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 150         of operand_type_init[].
 151         (set_bitfield): Adjust call to the above function.
 152         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 153         RegXMM, RegYMM, RegZMM): Define.
 154         * i386-reg.tbl: Expand prior shorthands.
 155
 156 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-gen.c (output_i386_opcode): Change order of fields
 159         emitted to output.
 160         * i386-opc.h (struct insn_template): Move operands field.
 161         Convert extension_opcode field to unsigned short.
 162         * i386-tbl.h: Re-generate.
 163
 164 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 167         of W.
 168         * i386-opc.h (W): Extend comment.
 169         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 170         general purpose variants not allowing for byte operands.
 171         * i386-tbl.h: Re-generate.
 172
 173 2019-10-29  Nick Clifton  <nickc@redhat.com>
 174
 175         * tic30-dis.c (print_branch): Correct size of operand array.
 176
 177 2019-10-29  Nick Clifton  <nickc@redhat.com>
 178
 179         * d30v-dis.c (print_insn): Check that operand index is valid
 180         before attempting to access the operands array.
 181
 182 2019-10-29  Nick Clifton  <nickc@redhat.com>
 183
 184         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 185         locating the bit to be tested.
 186
 187 2019-10-29  Nick Clifton  <nickc@redhat.com>
 188
 189         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 190         values.
 191         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 192         (print_insn_s12z):  Check for illegal size values.
 193
 194 2019-10-28  Nick Clifton  <nickc@redhat.com>
 195
 196         * csky-dis.c (csky_chars_to_number): Check for a negative
 197         count. Use an unsigned integer to construct the return value.
 198
 199 2019-10-28  Nick Clifton  <nickc@redhat.com>
 200
 201         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 202         operand buffer.  Set value to 15 not 13.
 203         (get_register_operand): Use OPERAND_BUFFER_LEN.
 204         (get_indirect_operand): Likewise.
 205         (print_two_operand): Likewise.
 206         (print_three_operand): Likewise.
 207         (print_oar_insn): Likewise.
 208
 209 2019-10-28  Nick Clifton  <nickc@redhat.com>
 210
 211         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 212         (bit_extract_simple): Likewise.
 213         (bit_copy): Likewise.
 214         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 215         index_offset array are not accessed.
 216
 217 2019-10-28  Nick Clifton  <nickc@redhat.com>
 218
 219         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 220         operand.
 221
 222 2019-10-25  Nick Clifton  <nickc@redhat.com>
 223
 224         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 225         access to opcodes.op array element.
 226
 227 2019-10-23  Nick Clifton  <nickc@redhat.com>
 228
 229         * rx-dis.c (get_register_name): Fix spelling typo in error
 230         message.
 231         (get_condition_name, get_flag_name, get_double_register_name)
 232         (get_double_register_high_name, get_double_register_low_name)
 233         (get_double_control_register_name, get_double_condition_name)
 234         (get_opsize_name, get_size_name): Likewise.
 235
 236 2019-10-22  Nick Clifton  <nickc@redhat.com>
 237
 238         * rx-dis.c (get_size_name): New function.  Provides safe
 239         access to name array.
 240         (get_opsize_name): Likewise.
 241         (print_insn_rx): Use the accessor functions.
 242
 243 2019-10-16  Nick Clifton  <nickc@redhat.com>
 244
 245         * rx-dis.c (get_register_name): New function.  Provides safe
 246         access to name array.
 247         (get_condition_name, get_flag_name, get_double_register_name)
 248         (get_double_register_high_name, get_double_register_low_name)
 249         (get_double_control_register_name, get_double_condition_name):
 250         Likewise.
 251         (print_insn_rx): Use the accessor functions.
 252
 253 2019-10-09  Nick Clifton  <nickc@redhat.com>
 254
 255         PR 25041
 256         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 257         instructions.
 258
 259 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 260
 261         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 262         (cmpsd): Likewise. Move EsSeg to other operand.
 263         * opcodes/i386-tbl.h: Re-generate.
 264
 265 2019-09-23  Alan Modra  <amodra@gmail.com>
 266
 267         * m68k-dis.c: Include cpu-m68k.h
 268
 269 2019-09-23  Alan Modra  <amodra@gmail.com>
 270
 271         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 272         "elf/mips.h" earlier.
 273
 274 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 275
 276         PR gas/25012
 277         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 278         with SReg operand.
 279         * i386-tbl.h: Re-generate.
 280
 281 2019-09-18  Alan Modra  <amodra@gmail.com>
 282
 283         * arc-ext.c: Update throughout for bfd section macro changes.
 284
 285 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 286
 287         * Makefile.in: Re-generate.
 288         * configure: Re-generate.
 289
 290 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 291
 292         * riscv-opc.c (riscv_opcodes): Change subset field
 293         to insn_class field for all instructions.
 294         (riscv_insn_types): Likewise.
 295
 296 2019-09-16  Phil Blundell  <pb@pbcl.net>
 297
 298         * configure: Regenerated.
 299
 300 2019-09-10  Miod Vallat  <miod@online.fr>
 301
 302         PR 24982
 303         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 304
 305 2019-09-09  Phil Blundell  <pb@pbcl.net>
 306
 307         binutils 2.33 branch created.
 308
 309 2019-09-03  Nick Clifton  <nickc@redhat.com>
 310
 311         PR 24961
 312         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 313         greater than zero before indexing via (bufcnt -1).
 314
 315 2019-09-03  Nick Clifton  <nickc@redhat.com>
 316
 317         PR 24958
 318         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 319         (MAX_SPEC_REG_NAME_LEN): Define.
 320         (struct mmix_dis_info): Use defined constants for array lengths.
 321         (get_reg_name): New function.
 322         (get_sprec_reg_name): New function.
 323         (print_insn_mmix): Use new functions.
 324
 325 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 326
 327         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 328         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 329         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 330
 331 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 332
 333         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 334         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 335         (aarch64_sys_reg_supported_p): Update checks for the above.
 336
 337 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 338
 339         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 340         cases MVE_SQRSHRL and MVE_UQRSHLL.
 341         (print_insn_mve): Add case for specifier 'k' to check
 342         specific bit of the instruction.
 343
 344 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 345
 346         PR 24854
 347         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 348         encountering an unknown machine type.
 349         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 350         cases return -1 rather than calling abort.
 351
 352 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 355         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 356         IgnoreSize.
 357         * i386-tbl.h: Re-generate.
 358
 359 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 360
 361         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 362         instructions.
 363
 364 2019-07-30  Mel Chen <mel.chen@sifive.com>
 365
 366         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 367         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 368
 369         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 370         fscsr.
 371
 372 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 373
 374         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 375         and MPY class instructions.
 376         (parse_option): Add nps400 option.
 377         (print_arc_disassembler_options): Add nps400 info.
 378
 379 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 380
 381         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 382         (bspop): Likewise.
 383         (modapp): Likewise.
 384         * arc-opc.c (RAD_CHK): Add.
 385         * arc-tbl.h: Regenerate.
 386
 387 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 388
 389         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 390         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 391
 392 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 393
 394         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 395         instructions as UNPREDICTABLE.
 396
 397 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 398
 399         * bpf-desc.c: Regenerated.
 400
 401 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 402
 403         * i386-gen.c (static_assert): Define.
 404         (main): Use it.
 405         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 406         (Opcode_Modifier_Num): ... this.
 407         (Mem): Delete.
 408
 409 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-gen.c (operand_types): Move RegMem ...
 412         (opcode_modifiers): ... here.
 413         * i386-opc.h (RegMem): Move to opcode modifer enum.
 414         (union i386_operand_type): Move regmem field ...
 415         (struct i386_opcode_modifier): ... here.
 416         * i386-opc.tbl (RegMem): Define.
 417         (mov, movq): Move RegMem on segment, control, debug, and test
 418         register flavors.
 419         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 420         to non-SSE2AVX flavor.
 421         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 422         Move RegMem on register only flavors. Drop IgnoreSize from
 423         legacy encoding flavors.
 424         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 425         flavors.
 426         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 427         register only flavors.
 428         (vmovd): Move RegMem and drop IgnoreSize on register only
 429         flavor. Change opcode and operand order to store form.
 430         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 431
 432 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 435         entries.
 436         * i386-opc.h (SReg2, SReg3): Replace by ...
 437         (SReg): ... this.
 438         (union i386_operand_type): Replace sreg fields.
 439         * i386-opc.tbl (mov, ): Use SReg.
 440         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 441         register flavors.
 442         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 443         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 444
 445 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 446
 447         * bpf-desc.c: Regenerate.
 448         * bpf-opc.c: Likewise.
 449         * bpf-opc.h: Likewise.
 450
 451 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 452
 453         * bpf-desc.c: Regenerate.
 454         * bpf-opc.c: Likewise.
 455
 456 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 457
 458         * arm-dis.c (print_insn_coprocessor): Rename index to
 459         index_operand.
 460
 461 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 462
 463         * riscv-opc.c (riscv_insn_types): Add r4 type.
 464
 465         * riscv-opc.c (riscv_insn_types): Add b and j type.
 466
 467         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 468         format for sb type and correct s type.
 469
 470 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 471
 472         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 473         SVE FMOV alias of FCPY.
 474
 475 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 476
 477         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 478         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 479
 480 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 481
 482         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 483         registers in an instruction prefixed by MOVPRFX.
 484
 485 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 486
 487         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 488         sve_size_13 icode to account for variant behaviour of
 489         pmull{t,b}.
 490         * aarch64-dis-2.c: Regenerate.
 491         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 492         sve_size_13 icode to account for variant behaviour of
 493         pmull{t,b}.
 494         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 495         (OP_SVE_VVV_Q_D): Add new qualifier.
 496         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 497         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 498         AES and those not.
 499
 500 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 501
 502         * opcodes/i386-gen.c (operand_type_init): Remove
 503         OPERAND_TYPE_VEC_IMM4 entry.
 504         (operand_types): Remove Vec_Imm4.
 505         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 506         (union i386_operand_type): Remove vec_imm4.
 507         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 508         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 509
 510 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 513         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 514         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 515         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 516         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 517         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 518         * i386-tbl.h: Re-generate.
 519
 520 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 521
 522         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 523         register operands.
 524         * i386-tbl.h: Re-generate.
 525
 526 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-opc.tbl (C): New.
 529         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 530         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 531         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 532         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 533         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 534         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 535         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 536         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 537         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 538         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 539         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 540         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 541         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 542         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 543         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 544         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 545         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 546         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 547         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 548         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 549         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 550         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 551         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 552         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 553         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 554         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 555         flavors.
 556         * i386-tbl.h: Re-generate.
 557
 558 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 559
 560         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 561         register operands.
 562         * i386-tbl.h: Re-generate.
 563
 564 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 565
 566         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 567         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 568         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 569         * i386-tbl.h: Re-generate.
 570
 571 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 574         Disp8MemShift from register only templates.
 575         * i386-tbl.h: Re-generate.
 576
 577 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 580         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 581         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 582         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 583         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 584         EVEX_W_0F11_P_3_M_1): Delete.
 585         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 586         EVEX_W_0F11_P_3): New.
 587         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 588         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 589         MOD_EVEX_0F11_PREFIX_3 table entries.
 590         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 591         PREFIX_EVEX_0F11 table entries.
 592         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 593         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 594         EVEX_W_0F11_P_3_M_{0,1} table entries.
 595
 596 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 599         Delete.
 600
 601 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 602
 603         PR binutils/24719
 604         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 605         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 606         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 607         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 608         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 609         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 610         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 611         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 612         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 613         PREFIX_EVEX_0F38C6_REG_6 entries.
 614         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 615         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 616         EVEX_W_0F38C7_R_6_P_2 entries.
 617         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 618         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 619         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 620         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 621         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 622         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 623         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 624
 625 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 628         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 629         VEX_LEN_0F2D_P_3): Delete.
 630         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 631         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 632         (prefix_table): ... here.
 633
 634 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 635
 636         * i386-dis.c (Iq): Delete.
 637         (Id): New.
 638         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 639         TBM insns.
 640         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 641         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 642         (OP_E_memory): Also honor needindex when deciding whether an
 643         address size prefix needs printing.
 644         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 645
 646 2019-06-26  Jim Wilson  <jimw@sifive.com>
 647
 648         PR binutils/24739
 649         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 650         Set info->display_endian to info->endian_code.
 651
 652 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 655         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 656         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 657         OPERAND_TYPE_ACC64 entries.
 658         * i386-init.h: Re-generate.
 659
 660 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 663         Delete.
 664         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 665         of dqa_mode.
 666         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 667         entries here.
 668         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 669         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 670
 671 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 674         variables.
 675
 676 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 679         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 680         movnti.
 681         * i386-opc.tbl (movnti): Add IgnoreSize.
 682         * i386-tbl.h: Re-generate.
 683
 684 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 687         * i386-tbl.h: Re-generate.
 688
 689 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 690
 691         * i386-dis-evex.h: Break into ...
 692         * i386-dis-evex-len.h: New file.
 693         * i386-dis-evex-mod.h: Likewise.
 694         * i386-dis-evex-prefix.h: Likewise.
 695         * i386-dis-evex-reg.h: Likewise.
 696         * i386-dis-evex-w.h: Likewise.
 697         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 698         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 699         i386-dis-evex-mod.h.
 700
 701 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         PR binutils/24700
 704         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 705         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 706         EVEX_W_0F385B_P_2.
 707         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 708         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 709         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 710         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 711         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 712         EVEX_LEN_0F385B_P_2_W_1.
 713         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 714         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 715         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 716         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 717         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 718         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 719         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 720         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 721         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 722         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 723
 724 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 725
 726         PR binutils/24691
 727         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 728         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 729         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 730         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 731         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 732         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 733         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 734         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 735         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 736         EVEX_LEN_0F3A43_P_2_W_1.
 737         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 738         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 739         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 740         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 741         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 742         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 743         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 744         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 745         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 746         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 747         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 748         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 749
 750 2019-06-14  Nick Clifton  <nickc@redhat.com>
 751
 752         * po/fr.po; Updated French translation.
 753
 754 2019-06-13  Stafford Horne  <shorne@gmail.com>
 755
 756         * or1k-asm.c: Regenerated.
 757         * or1k-desc.c: Regenerated.
 758         * or1k-desc.h: Regenerated.
 759         * or1k-dis.c: Regenerated.
 760         * or1k-ibld.c: Regenerated.
 761         * or1k-opc.c: Regenerated.
 762         * or1k-opc.h: Regenerated.
 763         * or1k-opinst.c: Regenerated.
 764
 765 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 766
 767         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 768
 769 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 770
 771         PR binutils/24633
 772         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 773         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 774         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 775         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 776         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 777         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 778         EVEX_LEN_0F3A1B_P_2_W_1.
 779         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 780         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 781         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 782         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 783         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 784         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 785         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 786         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 787
 788 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 789
 790         PR binutils/24626
 791         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 792         EVEX.vvvv when disassembling VEX and EVEX instructions.
 793         (OP_VEX): Set vex.register_specifier to 0 after readding
 794         vex.register_specifier.
 795         (OP_Vex_2src_1): Likewise.
 796         (OP_Vex_2src_2): Likewise.
 797         (OP_LWP_E): Likewise.
 798         (OP_EX_Vex): Don't check vex.register_specifier.
 799         (OP_XMM_Vex): Likewise.
 800
 801 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 802             Lili Cui  <lili.cui@intel.com>
 803
 804         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 805         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 806         instructions.
 807         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 808         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 809         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 810         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 811         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 812         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 813         * i386-init.h: Regenerated.
 814         * i386-tbl.h: Likewise.
 815
 816 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 817             Lili Cui  <lili.cui@intel.com>
 818
 819         * doc/c-i386.texi: Document enqcmd.
 820         * testsuite/gas/i386/enqcmd-intel.d: New file.
 821         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 822         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 823         * testsuite/gas/i386/enqcmd.d: Likewise.
 824         * testsuite/gas/i386/enqcmd.s: Likewise.
 825         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 826         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 827         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 828         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 829         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 830         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 831         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 832         and x86-64-enqcmd.
 833
 834 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 835
 836         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 837
 838 2019-06-03  Alan Modra  <amodra@gmail.com>
 839
 840         * ppc-dis.c (prefix_opcd_indices): Correct size.
 841
 842 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 843
 844         PR gas/24625
 845         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 846         Disp8ShiftVL.
 847         * i386-tbl.h: Regenerated.
 848
 849 2019-05-24  Alan Modra  <amodra@gmail.com>
 850
 851         * po/POTFILES.in: Regenerate.
 852
 853 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 854             Alan Modra  <amodra@gmail.com>
 855
 856         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 857         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 858         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 859         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 860         XTOP>): Define and add entries.
 861         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 862         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 863         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 864         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 865
 866 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 867             Alan Modra  <amodra@gmail.com>
 868
 869         * ppc-dis.c (ppc_opts): Add "future" entry.
 870         (PREFIX_OPCD_SEGS): Define.
 871         (prefix_opcd_indices): New array.
 872         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 873         (lookup_prefix): New function.
 874         (print_insn_powerpc): Handle 64-bit prefix instructions.
 875         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 876         (PMRR, POWERXX): Define.
 877         (prefix_opcodes): New instruction table.
 878         (prefix_num_opcodes): New constant.
 879
 880 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 881
 882         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 883         * configure: Regenerated.
 884         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 885         and cpu/bpf.opc.
 886         (HFILES): Add bpf-desc.h and bpf-opc.h.
 887         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 888         bpf-ibld.c and bpf-opc.c.
 889         (BPF_DEPS): Define.
 890         * Makefile.in: Regenerated.
 891         * disassemble.c (ARCH_bpf): Define.
 892         (disassembler): Add case for bfd_arch_bpf.
 893         (disassemble_init_for_target): Likewise.
 894         (enum epbf_isa_attr): Define.
 895         * disassemble.h: extern print_insn_bpf.
 896         * bpf-asm.c: Generated.
 897         * bpf-opc.h: Likewise.
 898         * bpf-opc.c: Likewise.
 899         * bpf-ibld.c: Likewise.
 900         * bpf-dis.c: Likewise.
 901         * bpf-desc.h: Likewise.
 902         * bpf-desc.c: Likewise.
 903
 904 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 905
 906         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 907         and VMSR with the new operands.
 908
 909 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 910
 911         * arm-dis.c (enum mve_instructions): New enum
 912         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 913         and cneg.
 914         (mve_opcodes): New instructions as above.
 915         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 916         csneg and csel.
 917         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 918
 919 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 920
 921         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 922         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 923         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 924         uqshl, urshrl and urshr.
 925         (is_mve_okay_in_it): Add new instructions to TRUE list.
 926         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 927         (print_insn_mve): Updated to accept new %j,
 928         %<bitfield>m and %<bitfield>n patterns.
 929
 930 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 931
 932         * mips-opc.c (mips_builtin_opcodes): Change source register
 933         constraint for DAUI.
 934
 935 2019-05-20  Nick Clifton  <nickc@redhat.com>
 936
 937         * po/fr.po: Updated French translation.
 938
 939 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 940             Michael Collison <michael.collison@arm.com>
 941
 942         * arm-dis.c (thumb32_opcodes): Add new instructions.
 943         (enum mve_instructions): Likewise.
 944         (enum mve_undefined): Add new reasons.
 945         (is_mve_encoding_conflict): Handle new instructions.
 946         (is_mve_undefined): Likewise.
 947         (is_mve_unpredictable): Likewise.
 948         (print_mve_undefined): Likewise.
 949         (print_mve_size): Likewise.
 950
 951 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 952             Michael Collison <michael.collison@arm.com>
 953
 954         * arm-dis.c (thumb32_opcodes): Add new instructions.
 955         (enum mve_instructions): Likewise.
 956         (is_mve_encoding_conflict): Handle new instructions.
 957         (is_mve_undefined): Likewise.
 958         (is_mve_unpredictable): Likewise.
 959         (print_mve_size): Likewise.
 960
 961 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 962             Michael Collison <michael.collison@arm.com>
 963
 964         * arm-dis.c (thumb32_opcodes): Add new instructions.
 965         (enum mve_instructions): Likewise.
 966         (is_mve_encoding_conflict): Likewise.
 967         (is_mve_unpredictable): Likewise.
 968         (print_mve_size): Likewise.
 969
 970 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 971             Michael Collison <michael.collison@arm.com>
 972
 973         * arm-dis.c (thumb32_opcodes): Add new instructions.
 974         (enum mve_instructions): Likewise.
 975         (is_mve_encoding_conflict): Handle new instructions.
 976         (is_mve_undefined): Likewise.
 977         (is_mve_unpredictable): Likewise.
 978         (print_mve_size): Likewise.
 979
 980 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 981             Michael Collison <michael.collison@arm.com>
 982
 983         * arm-dis.c (thumb32_opcodes): Add new instructions.
 984         (enum mve_instructions): Likewise.
 985         (is_mve_encoding_conflict): Handle new instructions.
 986         (is_mve_undefined): Likewise.
 987         (is_mve_unpredictable): Likewise.
 988         (print_mve_size): Likewise.
 989         (print_insn_mve): Likewise.
 990
 991 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 992             Michael Collison <michael.collison@arm.com>
 993
 994         * arm-dis.c (thumb32_opcodes): Add new instructions.
 995         (print_insn_thumb32): Handle new instructions.
 996
 997 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 998             Michael Collison <michael.collison@arm.com>
 999
1000         * arm-dis.c (enum mve_instructions): Add new instructions.
1001         (enum mve_undefined): Add new reasons.
1002         (is_mve_encoding_conflict): Handle new instructions.
1003         (is_mve_undefined): Likewise.
1004         (is_mve_unpredictable): Likewise.
1005         (print_mve_undefined): Likewise.
1006         (print_mve_size): Likewise.
1007         (print_mve_shift_n): Likewise.
1008         (print_insn_mve): Likewise.
1009
1010 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1011             Michael Collison <michael.collison@arm.com>
1012
1013         * arm-dis.c (enum mve_instructions): Add new instructions.
1014         (is_mve_encoding_conflict): Handle new instructions.
1015         (is_mve_unpredictable): Likewise.
1016         (print_mve_rotate): Likewise.
1017         (print_mve_size): Likewise.
1018         (print_insn_mve): Likewise.
1019
1020 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1021             Michael Collison <michael.collison@arm.com>
1022
1023         * arm-dis.c (enum mve_instructions): Add new instructions.
1024         (is_mve_encoding_conflict): Handle new instructions.
1025         (is_mve_unpredictable): Likewise.
1026         (print_mve_size): Likewise.
1027         (print_insn_mve): Likewise.
1028
1029 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1030             Michael Collison <michael.collison@arm.com>
1031
1032         * arm-dis.c (enum mve_instructions): Add new instructions.
1033         (enum mve_undefined): Add new reasons.
1034         (is_mve_encoding_conflict): Handle new instructions.
1035         (is_mve_undefined): Likewise.
1036         (is_mve_unpredictable): Likewise.
1037         (print_mve_undefined): Likewise.
1038         (print_mve_size): Likewise.
1039         (print_insn_mve): Likewise.
1040
1041 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1042             Michael Collison <michael.collison@arm.com>
1043
1044         * arm-dis.c (enum mve_instructions): Add new instructions.
1045         (is_mve_encoding_conflict): Handle new instructions.
1046         (is_mve_undefined): Likewise.
1047         (is_mve_unpredictable): Likewise.
1048         (print_mve_size): Likewise.
1049         (print_insn_mve): Likewise.
1050
1051 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1052             Michael Collison <michael.collison@arm.com>
1053
1054         * arm-dis.c (enum mve_instructions): Add new instructions.
1055         (enum mve_unpredictable): Add new reasons.
1056         (enum mve_undefined): Likewise.
1057         (is_mve_okay_in_it): Handle new isntructions.
1058         (is_mve_encoding_conflict): Likewise.
1059         (is_mve_undefined): Likewise.
1060         (is_mve_unpredictable): Likewise.
1061         (print_mve_vmov_index): Likewise.
1062         (print_simd_imm8): Likewise.
1063         (print_mve_undefined): Likewise.
1064         (print_mve_unpredictable): Likewise.
1065         (print_mve_size): Likewise.
1066         (print_insn_mve): Likewise.
1067
1068 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1069             Michael Collison <michael.collison@arm.com>
1070
1071         * arm-dis.c (enum mve_instructions): Add new instructions.
1072         (enum mve_unpredictable): Add new reasons.
1073         (enum mve_undefined): Likewise.
1074         (is_mve_encoding_conflict): Handle new instructions.
1075         (is_mve_undefined): Likewise.
1076         (is_mve_unpredictable): Likewise.
1077         (print_mve_undefined): Likewise.
1078         (print_mve_unpredictable): Likewise.
1079         (print_mve_rounding_mode): Likewise.
1080         (print_mve_vcvt_size): Likewise.
1081         (print_mve_size): Likewise.
1082         (print_insn_mve): Likewise.
1083
1084 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1085             Michael Collison <michael.collison@arm.com>
1086
1087         * arm-dis.c (enum mve_instructions): Add new instructions.
1088         (enum mve_unpredictable): Add new reasons.
1089         (enum mve_undefined): Likewise.
1090         (is_mve_undefined): Handle new instructions.
1091         (is_mve_unpredictable): Likewise.
1092         (print_mve_undefined): Likewise.
1093         (print_mve_unpredictable): Likewise.
1094         (print_mve_size): Likewise.
1095         (print_insn_mve): Likewise.
1096
1097 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1098             Michael Collison <michael.collison@arm.com>
1099
1100         * arm-dis.c (enum mve_instructions): Add new instructions.
1101         (enum mve_undefined): Add new reasons.
1102         (insns): Add new instructions.
1103         (is_mve_encoding_conflict):
1104         (print_mve_vld_str_addr): New print function.
1105         (is_mve_undefined): Handle new instructions.
1106         (is_mve_unpredictable): Likewise.
1107         (print_mve_undefined): Likewise.
1108         (print_mve_size): Likewise.
1109         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1110         (print_insn_mve):  Handle new operands.
1111
1112 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1113             Michael Collison <michael.collison@arm.com>
1114
1115         * arm-dis.c (enum mve_instructions): Add new instructions.
1116         (enum mve_unpredictable): Add new reasons.
1117         (is_mve_encoding_conflict): Handle new instructions.
1118         (is_mve_unpredictable): Likewise.
1119         (mve_opcodes): Add new instructions.
1120         (print_mve_unpredictable): Handle new reasons.
1121         (print_mve_register_blocks): New print function.
1122         (print_mve_size): Handle new instructions.
1123         (print_insn_mve): Likewise.
1124
1125 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1126             Michael Collison <michael.collison@arm.com>
1127
1128         * arm-dis.c (enum mve_instructions): Add new instructions.
1129         (enum mve_unpredictable): Add new reasons.
1130         (enum mve_undefined): Likewise.
1131         (is_mve_encoding_conflict): Handle new instructions.
1132         (is_mve_undefined): Likewise.
1133         (is_mve_unpredictable): Likewise.
1134         (coprocessor_opcodes): Move NEON VDUP from here...
1135         (neon_opcodes): ... to here.
1136         (mve_opcodes): Add new instructions.
1137         (print_mve_undefined):  Handle new reasons.
1138         (print_mve_unpredictable): Likewise.
1139         (print_mve_size): Handle new instructions.
1140         (print_insn_neon): Handle vdup.
1141         (print_insn_mve): Handle new operands.
1142
1143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1144             Michael Collison <michael.collison@arm.com>
1145
1146         * arm-dis.c (enum mve_instructions): Add new instructions.
1147         (enum mve_unpredictable): Add new values.
1148         (mve_opcodes): Add new instructions.
1149         (vec_condnames): New array with vector conditions.
1150         (mve_predicatenames): New array with predicate suffixes.
1151         (mve_vec_sizename): New array with vector sizes.
1152         (enum vpt_pred_state): New enum with vector predication states.
1153         (struct vpt_block): New struct type for vpt blocks.
1154         (vpt_block_state): Global struct to keep track of state.
1155         (mve_extract_pred_mask): New helper function.
1156         (num_instructions_vpt_block): Likewise.
1157         (mark_outside_vpt_block): Likewise.
1158         (mark_inside_vpt_block): Likewise.
1159         (invert_next_predicate_state): Likewise.
1160         (update_next_predicate_state): Likewise.
1161         (update_vpt_block_state): Likewise.
1162         (is_vpt_instruction): Likewise.
1163         (is_mve_encoding_conflict): Add entries for new instructions.
1164         (is_mve_unpredictable): Likewise.
1165         (print_mve_unpredictable): Handle new cases.
1166         (print_instruction_predicate): Likewise.
1167         (print_mve_size): New function.
1168         (print_vec_condition): New function.
1169         (print_insn_mve): Handle vpt blocks and new print operands.
1170
1171 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1172
1173         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1174         8, 14 and 15 for Armv8.1-M Mainline.
1175
1176 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1177             Michael Collison <michael.collison@arm.com>
1178
1179         * arm-dis.c (enum mve_instructions): New enum.
1180         (enum mve_unpredictable): Likewise.
1181         (enum mve_undefined): Likewise.
1182         (struct mopcode32): New struct.
1183         (is_mve_okay_in_it): New function.
1184         (is_mve_architecture): Likewise.
1185         (arm_decode_field): Likewise.
1186         (arm_decode_field_multiple): Likewise.
1187         (is_mve_encoding_conflict): Likewise.
1188         (is_mve_undefined): Likewise.
1189         (is_mve_unpredictable): Likewise.
1190         (print_mve_undefined): Likewise.
1191         (print_mve_unpredictable): Likewise.
1192         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1193         (print_insn_mve): New function.
1194         (print_insn_thumb32): Handle MVE architecture.
1195         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1196
1197 2019-05-10  Nick Clifton  <nickc@redhat.com>
1198
1199         PR 24538
1200         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1201         end of the table prematurely.
1202
1203 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1204
1205         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1206         macros for R6.
1207
1208 2019-05-11  Alan Modra  <amodra@gmail.com>
1209
1210         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1211         when -Mraw is in effect.
1212
1213 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1214
1215         * aarch64-dis-2.c: Regenerate.
1216         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1217         (OP_SVE_BBB): New variant set.
1218         (OP_SVE_DDDD): New variant set.
1219         (OP_SVE_HHH): New variant set.
1220         (OP_SVE_HHHU): New variant set.
1221         (OP_SVE_SSS): New variant set.
1222         (OP_SVE_SSSU): New variant set.
1223         (OP_SVE_SHH): New variant set.
1224         (OP_SVE_SBBU): New variant set.
1225         (OP_SVE_DSS): New variant set.
1226         (OP_SVE_DHHU): New variant set.
1227         (OP_SVE_VMV_HSD_BHS): New variant set.
1228         (OP_SVE_VVU_HSD_BHS): New variant set.
1229         (OP_SVE_VVVU_SD_BH): New variant set.
1230         (OP_SVE_VVVU_BHSD): New variant set.
1231         (OP_SVE_VVV_QHD_DBS): New variant set.
1232         (OP_SVE_VVV_HSD_BHS): New variant set.
1233         (OP_SVE_VVV_HSD_BHS2): New variant set.
1234         (OP_SVE_VVV_BHS_HSD): New variant set.
1235         (OP_SVE_VV_BHS_HSD): New variant set.
1236         (OP_SVE_VVV_SD): New variant set.
1237         (OP_SVE_VVU_BHS_HSD): New variant set.
1238         (OP_SVE_VZVV_SD): New variant set.
1239         (OP_SVE_VZVV_BH): New variant set.
1240         (OP_SVE_VZV_SD): New variant set.
1241         (aarch64_opcode_table): Add sve2 instructions.
1242
1243 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1244
1245         * aarch64-asm-2.c: Regenerated.
1246         * aarch64-dis-2.c: Regenerated.
1247         * aarch64-opc-2.c: Regenerated.
1248         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1249         for SVE_SHLIMM_UNPRED_22.
1250         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1251         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1252         operand.
1253
1254 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1255
1256         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1257         sve_size_tsz_bhs iclass encode.
1258         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1259         sve_size_tsz_bhs iclass decode.
1260
1261 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1262
1263         * aarch64-asm-2.c: Regenerated.
1264         * aarch64-dis-2.c: Regenerated.
1265         * aarch64-opc-2.c: Regenerated.
1266         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1267         for SVE_Zm4_11_INDEX.
1268         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1269         (fields): Handle SVE_i2h field.
1270         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1271         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1272
1273 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1274
1275         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1276         sve_shift_tsz_bhsd iclass encode.
1277         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1278         sve_shift_tsz_bhsd iclass decode.
1279
1280 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1281
1282         * aarch64-asm-2.c: Regenerated.
1283         * aarch64-dis-2.c: Regenerated.
1284         * aarch64-opc-2.c: Regenerated.
1285         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1286         (aarch64_encode_variant_using_iclass): Handle
1287         sve_shift_tsz_hsd iclass encode.
1288         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1289         sve_shift_tsz_hsd iclass decode.
1290         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1291         for SVE_SHRIMM_UNPRED_22.
1292         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1293         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1294         operand.
1295
1296 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1297
1298         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1299         sve_size_013 iclass encode.
1300         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1301         sve_size_013 iclass decode.
1302
1303 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1304
1305         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1306         sve_size_bh iclass encode.
1307         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1308         sve_size_bh iclass decode.
1309
1310 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1311
1312         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1313         sve_size_sd2 iclass encode.
1314         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1315         sve_size_sd2 iclass decode.
1316         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1317         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1318
1319 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1320
1321         * aarch64-asm-2.c: Regenerated.
1322         * aarch64-dis-2.c: Regenerated.
1323         * aarch64-opc-2.c: Regenerated.
1324         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1325         for SVE_ADDR_ZX.
1326         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1327         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1328
1329 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1330
1331         * aarch64-asm-2.c: Regenerated.
1332         * aarch64-dis-2.c: Regenerated.
1333         * aarch64-opc-2.c: Regenerated.
1334         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1335         for SVE_Zm3_11_INDEX.
1336         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1337         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1338         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1339         fields.
1340         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1341
1342 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1343
1344         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1345         sve_size_hsd2 iclass encode.
1346         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1347         sve_size_hsd2 iclass decode.
1348         * aarch64-opc.c (fields): Handle SVE_size field.
1349         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1350
1351 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1352
1353         * aarch64-asm-2.c: Regenerated.
1354         * aarch64-dis-2.c: Regenerated.
1355         * aarch64-opc-2.c: Regenerated.
1356         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1357         for SVE_IMM_ROT3.
1358         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1359         (fields): Handle SVE_rot3 field.
1360         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1361         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1362
1363 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1364
1365         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1366         instructions.
1367
1368 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1369
1370         * aarch64-tbl.h
1371         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1372         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1373         aarch64_feature_sve2bitperm): New feature sets.
1374         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1375         for feature set addresses.
1376         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1377         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1378
1379 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1380             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1381
1382         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1383         argument and set ASE_EVA_R6 appropriately.
1384         (set_default_mips_dis_options): Pass ISA to above.
1385         (parse_mips_dis_option): Likewise.
1386         * mips-opc.c (EVAR6): New macro.
1387         (mips_builtin_opcodes): Add llwpe, scwpe.
1388
1389 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1390
1391         * aarch64-asm-2.c: Regenerated.
1392         * aarch64-dis-2.c: Regenerated.
1393         * aarch64-opc-2.c: Regenerated.
1394         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1395         AARCH64_OPND_TME_UIMM16.
1396         (aarch64_print_operand): Likewise.
1397         * aarch64-tbl.h (QL_IMM_NIL): New.
1398         (TME): New.
1399         (_TME_INSN): New.
1400         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1401
1402 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1403
1404         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1405
1406 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1407             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1408
1409         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1410
1411 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1412
1413         * s12z-opc.h: Add extern "C" bracketing to help
1414         users who wish to use this interface in c++ code.
1415
1416 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1417
1418         * s12z-opc.c (bm_decode): Handle bit map operations with the
1419         "reserved0" mode.
1420
1421 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1422
1423         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1424         specifier.  Add entries for VLDR and VSTR of system registers.
1425         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1426         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1427         of %J and %K format specifier.
1428
1429 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1430
1431         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1432         Add new entries for VSCCLRM instruction.
1433         (print_insn_coprocessor): Handle new %C format control code.
1434
1435 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1436
1437         * arm-dis.c (enum isa): New enum.
1438         (struct sopcode32): New structure.
1439         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1440         set isa field of all current entries to ANY.
1441         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1442         Only match an entry if its isa field allows the current mode.
1443
1444 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1445
1446         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1447         CLRM.
1448         (print_insn_thumb32): Add logic to print %n CLRM register list.
1449
1450 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1451
1452         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1453         and %Q patterns.
1454
1455 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1456
1457         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1458         (print_insn_thumb32): Edit the switch case for %Z.
1459
1460 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1461
1462         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1463
1464 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1465
1466         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1467
1468 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1469
1470         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1471
1472 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1473
1474         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1475         Arm register with r13 and r15 unpredictable.
1476         (thumb32_opcodes): New instructions for bfx and bflx.
1477
1478 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1479
1480         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1481
1482 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1483
1484         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1485
1486 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1487
1488         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1489
1490 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1491
1492         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1493
1494 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1495
1496         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1497         "optr". ("operator" is a reserved word in c++).
1498
1499 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1500
1501         * aarch64-opc.c (aarch64_print_operand): Add case for
1502         AARCH64_OPND_Rt_SP.
1503         (verify_constraints): Likewise.
1504         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1505         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1506         to accept Rt|SP as first operand.
1507         (AARCH64_OPERANDS): Add new Rt_SP.
1508         * aarch64-asm-2.c: Regenerated.
1509         * aarch64-dis-2.c: Regenerated.
1510         * aarch64-opc-2.c: Regenerated.
1511
1512 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1513
1514         * aarch64-asm-2.c: Regenerated.
1515         * aarch64-dis-2.c: Likewise.
1516         * aarch64-opc-2.c: Likewise.
1517         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1518
1519 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1520
1521         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1522
1523 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1524
1525         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1526         * i386-init.h: Regenerated.
1527
1528 2019-04-07  Alan Modra  <amodra@gmail.com>
1529
1530         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1531         op_separator to control printing of spaces, comma and parens
1532         rather than need_comma, need_paren and spaces vars.
1533
1534 2019-04-07  Alan Modra  <amodra@gmail.com>
1535
1536         PR 24421
1537         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1538         (print_insn_neon, print_insn_arm): Likewise.
1539
1540 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1541
1542         * i386-dis-evex.h (evex_table): Updated to support BF16
1543         instructions.
1544         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1545         and EVEX_W_0F3872_P_3.
1546         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1547         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1548         * i386-opc.h (enum): Add CpuAVX512_BF16.
1549         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1550         * i386-opc.tbl: Add AVX512 BF16 instructions.
1551         * i386-init.h: Regenerated.
1552         * i386-tbl.h: Likewise.
1553
1554 2019-04-05  Alan Modra  <amodra@gmail.com>
1555
1556         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1557         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1558         to favour printing of "-" branch hint when using the "y" bit.
1559         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1560
1561 2019-04-05  Alan Modra  <amodra@gmail.com>
1562
1563         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1564         opcode until first operand is output.
1565
1566 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1567
1568         PR gas/24349
1569         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1570         (valid_bo_post_v2): Add support for 'at' branch hints.
1571         (insert_bo): Only error on branch on ctr.
1572         (get_bo_hint_mask): New function.
1573         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1574         for inserting 'at' branch hints.
1575         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1576         for extracting 'at' branch hints.
1577         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1578         (BOE): Delete operand.
1579         (BOM, BOP): New operands.
1580         (RM): Update value.
1581         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1582         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1583         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1584         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1585         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1586         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1587         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1588         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1589         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1590         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1591         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1592         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1593         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1594         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1595         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1596         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1597         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1598         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1599         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1600         bttarl+>: New extended mnemonics.
1601
1602 2019-03-28  Alan Modra  <amodra@gmail.com>
1603
1604         PR 24390
1605         * ppc-opc.c (BTF): Define.
1606         (powerpc_opcodes): Use for mtfsb*.
1607         * ppc-dis.c (print_insn_powerpc): Print fields with both
1608         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1609
1610 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1611
1612         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1613         (mapping_symbol_for_insn): Implement new algorithm.
1614         (print_insn): Remove duplicate code.
1615
1616 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1617
1618         * aarch64-dis.c (print_insn_aarch64):
1619         Implement override.
1620
1621 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1622
1623         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1624         order.
1625
1626 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1627
1628         * aarch64-dis.c (last_stop_offset): New.
1629         (print_insn_aarch64): Use stop_offset.
1630
1631 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1632
1633         PR gas/24359
1634         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1635         CPU_ANY_AVX2_FLAGS.
1636         * i386-init.h: Regenerated.
1637
1638 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1639
1640         PR gas/24348
1641         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1642         vmovdqu16, vmovdqu32 and vmovdqu64.
1643         * i386-tbl.h: Regenerated.
1644
1645 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1646
1647         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1648         from vstrszb, vstrszh, and vstrszf.
1649
1650 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1651
1652         * s390-opc.txt: Add instruction descriptions.
1653
1654 2019-02-08  Jim Wilson  <jimw@sifive.com>
1655
1656         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1657         <bne>: Likewise.
1658
1659 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1660
1661         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1662
1663 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1664
1665         PR binutils/23212
1666         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1667         * aarch64-opc.c (verify_elem_sd): New.
1668         (fields): Add FLD_sz entr.
1669         * aarch64-tbl.h (_SIMD_INSN): New.
1670         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1671         fmulx scalar and vector by element isns.
1672
1673 2019-02-07  Nick Clifton  <nickc@redhat.com>
1674
1675         * po/sv.po: Updated Swedish translation.
1676
1677 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1678
1679         * s390-mkopc.c (main): Accept arch13 as cpu string.
1680         * s390-opc.c: Add new instruction formats and instruction opcode
1681         masks.
1682         * s390-opc.txt: Add new arch13 instructions.
1683
1684 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1685
1686         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1687         (aarch64_opcode): Change encoding for stg, stzg
1688         st2g and st2zg.
1689         * aarch64-asm-2.c: Regenerated.
1690         * aarch64-dis-2.c: Regenerated.
1691         * aarch64-opc-2.c: Regenerated.
1692
1693 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1694
1695         * aarch64-asm-2.c: Regenerated.
1696         * aarch64-dis-2.c: Likewise.
1697         * aarch64-opc-2.c: Likewise.
1698         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1699
1700 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1701             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1702
1703         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1704         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1705         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1706         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1707         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1708         case for ldstgv_indexed.
1709         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1710         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1711         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1712         * aarch64-asm-2.c: Regenerated.
1713         * aarch64-dis-2.c: Regenerated.
1714         * aarch64-opc-2.c: Regenerated.
1715
1716 2019-01-23  Nick Clifton  <nickc@redhat.com>
1717
1718         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1719
1720 2019-01-21  Nick Clifton  <nickc@redhat.com>
1721
1722         * po/de.po: Updated German translation.
1723         * po/uk.po: Updated Ukranian translation.
1724
1725 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1726         * mips-dis.c (mips_arch_choices): Fix typo in
1727         gs464, gs464e and gs264e descriptors.
1728
1729 2019-01-19  Nick Clifton  <nickc@redhat.com>
1730
1731         * configure: Regenerate.
1732         * po/opcodes.pot: Regenerate.
1733
1734 2018-06-24  Nick Clifton  <nickc@redhat.com>
1735
1736         2.32 branch created.
1737
1738 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1739
1740         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1741         if it is null.
1742         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1743         zero.
1744
1745 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1746
1747         * configure: Regenerate.
1748
1749 2019-01-07  Alan Modra  <amodra@gmail.com>
1750
1751         * configure: Regenerate.
1752         * po/POTFILES.in: Regenerate.
1753
1754 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1755
1756         * s12z-opc.c: New file.
1757         * s12z-opc.h: New file.
1758         * s12z-dis.c: Removed all code not directly related to display
1759         of instructions.  Used the interface provided by the new files
1760         instead.
1761         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1762         * Makefile.in: Regenerate.
1763         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1764         * configure: Regenerate.
1765
1766 2019-01-01  Alan Modra  <amodra@gmail.com>
1767
1768         Update year range in copyright notice of all files.
1769
1770 For older changes see ChangeLog-2018
1771 \f
1772 Copyright (C) 2019 Free Software Foundation, Inc.
1773
1774 Copying and distribution of this file, with or without modification,
1775 are permitted in any medium without royalty provided the copyright
1776 notice and this notice are preserved.
1777
1778 Local Variables:
1779 mode: change-log
1780 left-margin: 8
1781 fill-column: 74
1782 version-control: never
1783 End: