opcodes/ChangeLog

   1 2020-06-06  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
   4
   5 2020-06-05  Alan Modra  <amodra@gmail.com>
   6
   7         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
   8         size is large enough.
   9
  10 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
  11
  12         * disassemble.c (disassemble_init_for_target): Set endian_code for
  13         bpf targets.
  14         * bpf-desc.c: Regenerate.
  15         * bpf-opc.c: Likewise.
  16         * bpf-dis.c: Likewise.
  17
  18 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
  19
  20         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
  21         (cgen_put_insn_value): Likewise.
  22         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
  23         * cgen-dis.in (print_insn): Likewise.
  24         * cgen-ibld.in (insert_1): Likewise.
  25         (insert_1): Likewise.
  26         (insert_insn_normal): Likewise.
  27         (extract_1): Likewise.
  28         * bpf-dis.c: Regenerate.
  29         * bpf-ibld.c: Likewise.
  30         * bpf-ibld.c: Likewise.
  31         * cgen-dis.in: Likewise.
  32         * cgen-ibld.in: Likewise.
  33         * cgen-opc.c: Likewise.
  34         * epiphany-dis.c: Likewise.
  35         * epiphany-ibld.c: Likewise.
  36         * fr30-dis.c: Likewise.
  37         * fr30-ibld.c: Likewise.
  38         * frv-dis.c: Likewise.
  39         * frv-ibld.c: Likewise.
  40         * ip2k-dis.c: Likewise.
  41         * ip2k-ibld.c: Likewise.
  42         * iq2000-dis.c: Likewise.
  43         * iq2000-ibld.c: Likewise.
  44         * lm32-dis.c: Likewise.
  45         * lm32-ibld.c: Likewise.
  46         * m32c-dis.c: Likewise.
  47         * m32c-ibld.c: Likewise.
  48         * m32r-dis.c: Likewise.
  49         * m32r-ibld.c: Likewise.
  50         * mep-dis.c: Likewise.
  51         * mep-ibld.c: Likewise.
  52         * mt-dis.c: Likewise.
  53         * mt-ibld.c: Likewise.
  54         * or1k-dis.c: Likewise.
  55         * or1k-ibld.c: Likewise.
  56         * xc16x-dis.c: Likewise.
  57         * xc16x-ibld.c: Likewise.
  58         * xstormy16-dis.c: Likewise.
  59         * xstormy16-ibld.c: Likewise.
  60
  61 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
  62
  63         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
  64         (print_insn_): Handle instruction endian.
  65         * bpf-dis.c: Regenerate.
  66         * bpf-desc.c: Regenerate.
  67         * epiphany-dis.c: Likewise.
  68         * epiphany-desc.c: Likewise.
  69         * fr30-dis.c: Likewise.
  70         * fr30-desc.c: Likewise.
  71         * frv-dis.c: Likewise.
  72         * frv-desc.c: Likewise.
  73         * ip2k-dis.c: Likewise.
  74         * ip2k-desc.c: Likewise.
  75         * iq2000-dis.c: Likewise.
  76         * iq2000-desc.c: Likewise.
  77         * lm32-dis.c: Likewise.
  78         * lm32-desc.c: Likewise.
  79         * m32c-dis.c: Likewise.
  80         * m32c-desc.c: Likewise.
  81         * m32r-dis.c: Likewise.
  82         * m32r-desc.c: Likewise.
  83         * mep-dis.c: Likewise.
  84         * mep-desc.c: Likewise.
  85         * mt-dis.c: Likewise.
  86         * mt-desc.c: Likewise.
  87         * or1k-dis.c: Likewise.
  88         * or1k-desc.c: Likewise.
  89         * xc16x-dis.c: Likewise.
  90         * xc16x-desc.c: Likewise.
  91         * xstormy16-dis.c: Likewise.
  92         * xstormy16-desc.c: Likewise.
  93
  94 2020-06-03  Nick Clifton  <nickc@redhat.com>
  95
  96         * po/sr.po: Updated Serbian translation.
  97
  98 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
  99
 100         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 101         (riscv_get_priv_spec_class): Likewise.
 102
 103 2020-06-01  Alan Modra  <amodra@gmail.com>
 104
 105         * bpf-desc.c: Regenerate.
 106
 107 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 108             David Faust <david.faust@oracle.com>
 109
 110         * bpf-desc.c: Regenerate.
 111         * bpf-opc.h: Likewise.
 112         * bpf-opc.c: Likewise.
 113         * bpf-dis.c: Likewise.
 114
 115 2020-05-28  Alan Modra  <amodra@gmail.com>
 116
 117         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 118         values.
 119
 120 2020-05-28  Alan Modra  <amodra@gmail.com>
 121
 122         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 123         immediates.
 124         (print_insn_ns32k): Revert last change.
 125
 126 2020-05-28  Nick Clifton  <nickc@redhat.com>
 127
 128         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 129         static.
 130
 131 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 132
 133         Fix extraction of signed constants in nios2 disassembler (again).
 134
 135         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 136         extractions of signed fields.
 137
 138 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 139
 140         * s390-opc.txt: Relocate vector load/store instructions with
 141         additional alignment parameter and change architecture level
 142         constraint from z14 to z13.
 143
 144 2020-05-21  Alan Modra  <amodra@gmail.com>
 145
 146         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 147         * sparc-dis.c: Likewise.
 148         * tic4x-dis.c: Likewise.
 149         * xtensa-dis.c: Likewise.
 150         * bpf-desc.c: Regenerate.
 151         * epiphany-desc.c: Regenerate.
 152         * fr30-desc.c: Regenerate.
 153         * frv-desc.c: Regenerate.
 154         * ip2k-desc.c: Regenerate.
 155         * iq2000-desc.c: Regenerate.
 156         * lm32-desc.c: Regenerate.
 157         * m32c-desc.c: Regenerate.
 158         * m32r-desc.c: Regenerate.
 159         * mep-asm.c: Regenerate.
 160         * mep-desc.c: Regenerate.
 161         * mt-desc.c: Regenerate.
 162         * or1k-desc.c: Regenerate.
 163         * xc16x-desc.c: Regenerate.
 164         * xstormy16-desc.c: Regenerate.
 165
 166 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 167
 168         * riscv-opc.c (riscv_ext_version_table): The table used to store
 169         all information about the supported spec and the corresponding ISA
 170         versions.  Currently, only Zicsr is supported to verify the
 171         correctness of Z sub extension settings.  Others will be supported
 172         in the future patches.
 173         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 174         classes and the corresponding strings.
 175         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 176         spec class by giving a ISA spec string.
 177         * riscv-opc.c (struct priv_spec_t): New structure.
 178         (struct priv_spec_t priv_specs): List for all supported privilege spec
 179         classes and the corresponding strings.
 180         (riscv_get_priv_spec_class): New function.  Get the corresponding
 181         privilege spec class by giving a spec string.
 182         (riscv_get_priv_spec_name): New function.  Get the corresponding
 183         privilege spec string by giving a CSR version class.
 184         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 185         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 186         according to the chosen version.  Build a hash table riscv_csr_hash to
 187         store the valid CSR for the chosen pirv verison.  Dump the direct
 188         CSR address rather than it's name if it is invalid.
 189         (parse_riscv_dis_option_without_args): New function.  Parse the options
 190         without arguments.
 191         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 192         parse the options without arguments first, and then handle the options
 193         with arguments.  Add the new option -Mpriv-spec, which has argument.
 194         * riscv-dis.c (print_riscv_disassembler_options): Add description
 195         about the new OBJDUMP option.
 196
 197 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 198
 199         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 200         WC values on POWER10 sync, dcbf  and wait instructions.
 201         (insert_pl, extract_pl): New functions.
 202         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 203         (LS3): New , 3-bit L for sync.
 204         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 205         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 206         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 207         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 208         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 209         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 210         <wait>: Enable PL operand on POWER10.
 211         <dcbf>: Enable L3OPT operand on POWER10.
 212         <sync>: Enable SC2 operand on POWER10.
 213
 214 2020-05-19  Stafford Horne  <shorne@gmail.com>
 215
 216         PR 25184
 217         * or1k-asm.c: Regenerate.
 218         * or1k-desc.c: Regenerate.
 219         * or1k-desc.h: Regenerate.
 220         * or1k-dis.c: Regenerate.
 221         * or1k-ibld.c: Regenerate.
 222         * or1k-opc.c: Regenerate.
 223         * or1k-opc.h: Regenerate.
 224         * or1k-opinst.c: Regenerate.
 225
 226 2020-05-11  Alan Modra  <amodra@gmail.com>
 227
 228         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 229         xsmaxcqp, xsmincqp.
 230
 231 2020-05-11  Alan Modra  <amodra@gmail.com>
 232
 233         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 234         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 235
 236 2020-05-11  Alan Modra  <amodra@gmail.com>
 237
 238         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 239
 240 2020-05-11  Alan Modra  <amodra@gmail.com>
 241
 242         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 243         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 244
 245 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 246
 247         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 248         mnemonics.
 249
 250 2020-05-11  Alan Modra  <amodra@gmail.com>
 251
 252         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 253         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 254         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 255         (prefix_opcodes): Add xxeval.
 256
 257 2020-05-11  Alan Modra  <amodra@gmail.com>
 258
 259         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 260         xxgenpcvwm, xxgenpcvdm.
 261
 262 2020-05-11  Alan Modra  <amodra@gmail.com>
 263
 264         * ppc-opc.c (MP, VXVAM_MASK): Define.
 265         (VXVAPS_MASK): Use VXVA_MASK.
 266         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 267         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 268         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 269         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 270
 271 2020-05-11  Alan Modra  <amodra@gmail.com>
 272             Peter Bergner  <bergner@linux.ibm.com>
 273
 274         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 275         New functions.
 276         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 277         YMSK2, XA6a, XA6ap, XB6a entries.
 278         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 279         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 280         (PPCVSX4): Define.
 281         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 282         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 283         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 284         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 285         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 286         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 287         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 288         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 289         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 290         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 291         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 292         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 293         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 294         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 295
 296 2020-05-11  Alan Modra  <amodra@gmail.com>
 297
 298         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 299         (insert_xts, extract_xts): New functions.
 300         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 301         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 302         (VXRC_MASK, VXSH_MASK): Define.
 303         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 304         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 305         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 306         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 307         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 308         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 309         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 310
 311 2020-05-11  Alan Modra  <amodra@gmail.com>
 312
 313         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 314         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 315         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 316         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 317         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 318
 319 2020-05-11  Alan Modra  <amodra@gmail.com>
 320
 321         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 322         (XTP, DQXP, DQXP_MASK): Define.
 323         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 324         (prefix_opcodes): Add plxvp and pstxvp.
 325
 326 2020-05-11  Alan Modra  <amodra@gmail.com>
 327
 328         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 329         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 330         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 331
 332 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 333
 334         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 335
 336 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 337
 338         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 339         (L1OPT): Define.
 340         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 341
 342 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 343
 344         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 345
 346 2020-05-11  Alan Modra  <amodra@gmail.com>
 347
 348         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 349
 350 2020-05-11  Alan Modra  <amodra@gmail.com>
 351
 352         * ppc-dis.c (ppc_opts): Add "power10" entry.
 353         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 354         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 355
 356 2020-05-11  Nick Clifton  <nickc@redhat.com>
 357
 358         * po/fr.po: Updated French translation.
 359
 360 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 361
 362         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 363         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 364         (operand_general_constraint_met_p): validate
 365         AARCH64_OPND_UNDEFINED.
 366         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 367         for FLD_imm16_2.
 368         * aarch64-asm-2.c: Regenerated.
 369         * aarch64-dis-2.c: Regenerated.
 370         * aarch64-opc-2.c: Regenerated.
 371
 372 2020-04-29  Nick Clifton  <nickc@redhat.com>
 373
 374         PR 22699
 375         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 376         and SETRC insns.
 377
 378 2020-04-29  Nick Clifton  <nickc@redhat.com>
 379
 380         * po/sv.po: Updated Swedish translation.
 381
 382 2020-04-29  Nick Clifton  <nickc@redhat.com>
 383
 384         PR 22699
 385         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 386         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 387         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 388         IMM0_8U case.
 389
 390 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 391
 392         PR 25848
 393         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 394         cmpi only on m68020up and cpu32.
 395
 396 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 397
 398         * aarch64-asm.c (aarch64_ins_none): New.
 399         * aarch64-asm.h (ins_none): New declaration.
 400         * aarch64-dis.c (aarch64_ext_none): New.
 401         * aarch64-dis.h (ext_none): New declaration.
 402         * aarch64-opc.c (aarch64_print_operand): Update case for
 403         AARCH64_OPND_BARRIER_PSB.
 404         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 405         (AARCH64_OPERANDS): Update inserter/extracter for
 406         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 407         * aarch64-asm-2.c: Regenerated.
 408         * aarch64-dis-2.c: Regenerated.
 409         * aarch64-opc-2.c: Regenerated.
 410
 411 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 412
 413         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 414         (aarch64_feature_ras, RAS): Likewise.
 415         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 416         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 417         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 418         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 419         * aarch64-asm-2.c: Regenerated.
 420         * aarch64-dis-2.c: Regenerated.
 421         * aarch64-opc-2.c: Regenerated.
 422
 423 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 424
 425         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 426         (print_insn_neon): Support disassembly of conditional
 427         instructions.
 428
 429 2020-02-16  David Faust  <david.faust@oracle.com>
 430
 431         * bpf-desc.c: Regenerate.
 432         * bpf-desc.h: Likewise.
 433         * bpf-opc.c: Regenerate.
 434         * bpf-opc.h: Likewise.
 435
 436 2020-04-07  Lili Cui  <lili.cui@intel.com>
 437
 438         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 439         (prefix_table): New instructions (see prefixes above).
 440         (rm_table): Likewise
 441         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 442         CPU_ANY_TSXLDTRK_FLAGS.
 443         (cpu_flags): Add CpuTSXLDTRK.
 444         * i386-opc.h (enum): Add CpuTSXLDTRK.
 445         (i386_cpu_flags): Add cputsxldtrk.
 446         * i386-opc.tbl: Add XSUSPLDTRK insns.
 447         * i386-init.h: Regenerate.
 448         * i386-tbl.h: Likewise.
 449
 450 2020-04-02  Lili Cui  <lili.cui@intel.com>
 451
 452         * i386-dis.c (prefix_table): New instructions serialize.
 453         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 454         CPU_ANY_SERIALIZE_FLAGS.
 455         (cpu_flags): Add CpuSERIALIZE.
 456         * i386-opc.h (enum): Add CpuSERIALIZE.
 457         (i386_cpu_flags): Add cpuserialize.
 458         * i386-opc.tbl: Add SERIALIZE insns.
 459         * i386-init.h: Regenerate.
 460         * i386-tbl.h: Likewise.
 461
 462 2020-03-26  Alan Modra  <amodra@gmail.com>
 463
 464         * disassemble.h (opcodes_assert): Declare.
 465         (OPCODES_ASSERT): Define.
 466         * disassemble.c: Don't include assert.h.  Include opintl.h.
 467         (opcodes_assert): New function.
 468         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 469         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 470         calculate maxlen.  Omit insn decoding when insn length exceeds
 471         maxlen.  Exit from nibble loop when looking for E, before
 472         accessing next data byte.  Move processing of E outside loop.
 473         Replace tests of maxlen in loop with assertions.
 474
 475 2020-03-26  Alan Modra  <amodra@gmail.com>
 476
 477         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 478
 479 2020-03-25  Alan Modra  <amodra@gmail.com>
 480
 481         * z80-dis.c (suffix): Init mybuf.
 482
 483 2020-03-22  Alan Modra  <amodra@gmail.com>
 484
 485         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 486         successflly read from section.
 487
 488 2020-03-22  Alan Modra  <amodra@gmail.com>
 489
 490         * arc-dis.c (find_format): Use ISO C string concatenation rather
 491         than line continuation within a string.  Don't access needs_limm
 492         before testing opcode != NULL.
 493
 494 2020-03-22  Alan Modra  <amodra@gmail.com>
 495
 496         * ns32k-dis.c (print_insn_arg): Update comment.
 497         (print_insn_ns32k): Reduce size of index_offset array, and
 498         initialize, passing -1 to print_insn_arg for args that are not
 499         an index.  Don't exit arg loop early.  Abort on bad arg number.
 500
 501 2020-03-22  Alan Modra  <amodra@gmail.com>
 502
 503         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 504         * s12z-opc.c: Formatting.
 505         (operands_f): Return an int.
 506         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 507         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 508         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 509         (exg_sex_discrim): Likewise.
 510         (create_immediate_operand, create_bitfield_operand),
 511         (create_register_operand_with_size, create_register_all_operand),
 512         (create_register_all16_operand, create_simple_memory_operand),
 513         (create_memory_operand, create_memory_auto_operand): Don't
 514         segfault on malloc failure.
 515         (z_ext24_decode): Return an int status, negative on fail, zero
 516         on success.
 517         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 518         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 519         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 520         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 521         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 522         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 523         (loop_primitive_decode, shift_decode, psh_pul_decode),
 524         (bit_field_decode): Similarly.
 525         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 526         to return value, update callers.
 527         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 528         Don't segfault on NULL operand.
 529         (decode_operation): Return OP_INVALID on first fail.
 530         (decode_s12z): Check all reads, returning -1 on fail.
 531
 532 2020-03-20  Alan Modra  <amodra@gmail.com>
 533
 534         * metag-dis.c (print_insn_metag): Don't ignore status from
 535         read_memory_func.
 536
 537 2020-03-20  Alan Modra  <amodra@gmail.com>
 538
 539         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 540         Initialize parts of buffer not written when handling a possible
 541         2-byte insn at end of section.  Don't attempt decoding of such
 542         an insn by the 4-byte machinery.
 543
 544 2020-03-20  Alan Modra  <amodra@gmail.com>
 545
 546         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 547         partially filled buffer.  Prevent lookup of 4-byte insns when
 548         only VLE 2-byte insns are possible due to section size.  Print
 549         ".word" rather than ".long" for 2-byte leftovers.
 550
 551 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 552
 553         PR 25641
 554         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 555
 556 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 557
 558         * i386-dis.c (X86_64_0D): Rename to ...
 559         (X86_64_0E): ... this.
 560
 561 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 564         * Makefile.in: Regenerated.
 565
 566 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 569         3-operand pseudos.
 570         * i386-tbl.h: Re-generate.
 571
 572 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 575         vprot*, vpsha*, and vpshl*.
 576         * i386-tbl.h: Re-generate.
 577
 578 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 581         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 582         * i386-tbl.h: Re-generate.
 583
 584 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 587         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 588         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 589         * i386-tbl.h: Re-generate.
 590
 591 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-gen.c (struct template_arg, struct template_instance,
 594         struct template_param, struct template, templates,
 595         parse_template, expand_templates): New.
 596         (process_i386_opcodes): Various local variables moved to
 597         expand_templates. Call parse_template and expand_templates.
 598         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 599         * i386-tbl.h: Re-generate.
 600
 601 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 604         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 605         register and memory source templates. Replace VexW= by VexW*
 606         where applicable.
 607         * i386-tbl.h: Re-generate.
 608
 609 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 612         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 613         * i386-tbl.h: Re-generate.
 614
 615 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 616
 617         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 618         * i386-tbl.h: Re-generate.
 619
 620 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 623         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 624         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 625         VexW0 on SSE2AVX variants.
 626         (vmovq): Drop NoRex64 from XMM/XMM variants.
 627         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 628         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 629         applicable use VexW0.
 630         * i386-tbl.h: Re-generate.
 631
 632 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 635         * i386-opc.h (Rex64): Delete.
 636         (struct i386_opcode_modifier): Remove rex64 field.
 637         * i386-opc.tbl (crc32): Drop Rex64.
 638         Replace Rex64 with Size64 everywhere else.
 639         * i386-tbl.h: Re-generate.
 640
 641 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-dis.c (OP_E_memory): Exclude recording of used address
 644         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 645         addressed memory operands for MPX insns.
 646
 647 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 650         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 651         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 652         (ptwrite): Split into non-64-bit and 64-bit forms.
 653         * i386-tbl.h: Re-generate.
 654
 655 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 658         template.
 659         * i386-tbl.h: Re-generate.
 660
 661 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 662
 663         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 664         (prefix_table): Move vmmcall here. Add vmgexit.
 665         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 666         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 667         (cpu_flags): Add CpuSEV_ES entry.
 668         * i386-opc.h (CpuSEV_ES): New.
 669         (union i386_cpu_flags): Add cpusev_es field.
 670         * i386-opc.tbl (vmgexit): New.
 671         * i386-init.h, i386-tbl.h: Re-generate.
 672
 673 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 676         with MnemonicSize.
 677         * i386-opc.h (IGNORESIZE): New.
 678         (DEFAULTSIZE): Likewise.
 679         (IgnoreSize): Removed.
 680         (DefaultSize): Likewise.
 681         (MnemonicSize): New.
 682         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 683         mnemonicsize.
 684         * i386-opc.tbl (IgnoreSize): New.
 685         (DefaultSize): Likewise.
 686         * i386-tbl.h: Regenerated.
 687
 688 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 689
 690         PR 25627
 691         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 692         instructions.
 693
 694 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 695
 696         PR gas/25622
 697         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 698         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 699         * i386-tbl.h: Regenerated.
 700
 701 2020-02-26  Alan Modra  <amodra@gmail.com>
 702
 703         * aarch64-asm.c: Indent labels correctly.
 704         * aarch64-dis.c: Likewise.
 705         * aarch64-gen.c: Likewise.
 706         * aarch64-opc.c: Likewise.
 707         * alpha-dis.c: Likewise.
 708         * i386-dis.c: Likewise.
 709         * nds32-asm.c: Likewise.
 710         * nfp-dis.c: Likewise.
 711         * visium-dis.c: Likewise.
 712
 713 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 714
 715         * arc-regs.h (int_vector_base): Make it available for all ARC
 716         CPUs.
 717
 718 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 719
 720         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 721         changed.
 722
 723 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 724
 725         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 726         c.mv/c.li if rs1 is zero.
 727
 728 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 731         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 732         CPU_POPCNT_FLAGS.
 733         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 734         * i386-opc.h (CpuABM): Removed.
 735         (CpuPOPCNT): New.
 736         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 737         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 738         popcnt.  Remove CpuABM from lzcnt.
 739         * i386-init.h: Regenerated.
 740         * i386-tbl.h: Likewise.
 741
 742 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 745         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 746         VexW1 instead of open-coding them.
 747         * i386-tbl.h: Re-generate.
 748
 749 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-opc.tbl (AddrPrefixOpReg): Define.
 752         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 753         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 754         templates. Drop NoRex64.
 755         * i386-tbl.h: Re-generate.
 756
 757 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 758
 759         PR gas/6518
 760         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 761         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 762         into Intel syntax instance (with Unpsecified) and AT&T one
 763         (without).
 764         (vcvtneps2bf16): Likewise, along with folding the two so far
 765         separate ones.
 766         * i386-tbl.h: Re-generate.
 767
 768 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 771         CPU_ANY_SSE4A_FLAGS.
 772
 773 2020-02-17  Alan Modra  <amodra@gmail.com>
 774
 775         * i386-gen.c (cpu_flag_init): Correct last change.
 776
 777 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 780         CPU_ANY_SSE4_FLAGS.
 781
 782 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 785         (movzx): Likewise.
 786
 787 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 788
 789         PR gas/25438
 790         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 791         destination for Cpu64-only variant.
 792         (movzx): Fold patterns.
 793         * i386-tbl.h: Re-generate.
 794
 795 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 798         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 799         CPU_ANY_SSE4_FLAGS entry.
 800         * i386-init.h: Re-generate.
 801
 802 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 805         with Unspecified, making the present one AT&T syntax only.
 806         * i386-tbl.h: Re-generate.
 807
 808 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 811         * i386-tbl.h: Re-generate.
 812
 813 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 814
 815         PR gas/24546
 816         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 817         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 818         Amd64 and Intel64 templates.
 819         (call, jmp): Likewise for far indirect variants. Dro
 820         Unspecified.
 821         * i386-tbl.h: Re-generate.
 822
 823 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 826         * i386-opc.h (ShortForm): Delete.
 827         (struct i386_opcode_modifier): Remove shortform field.
 828         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 829         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 830         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 831         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 832         Drop ShortForm.
 833         * i386-tbl.h: Re-generate.
 834
 835 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 836
 837         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 838         fucompi): Drop ShortForm from operand-less templates.
 839         * i386-tbl.h: Re-generate.
 840
 841 2020-02-11  Alan Modra  <amodra@gmail.com>
 842
 843         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 844         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 845         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 846         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 847         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 848
 849 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 850
 851         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 852         (cde_opcodes): Add VCX* instructions.
 853
 854 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 855             Matthew Malcomson  <matthew.malcomson@arm.com>
 856
 857         * arm-dis.c (struct cdeopcode32): New.
 858         (CDE_OPCODE): New macro.
 859         (cde_opcodes): New disassembly table.
 860         (regnames): New option to table.
 861         (cde_coprocs): New global variable.
 862         (print_insn_cde): New
 863         (print_insn_thumb32): Use print_insn_cde.
 864         (parse_arm_disassembler_options): Parse coprocN args.
 865
 866 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 867
 868         PR gas/25516
 869         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 870         with ISA64.
 871         * i386-opc.h (AMD64): Removed.
 872         (Intel64): Likewose.
 873         (AMD64): New.
 874         (INTEL64): Likewise.
 875         (INTEL64ONLY): Likewise.
 876         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 877         * i386-opc.tbl (Amd64): New.
 878         (Intel64): Likewise.
 879         (Intel64Only): Likewise.
 880         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 881         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 882         * i386-tbl.h: Regenerated.
 883
 884 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 885
 886         PR 25469
 887         * z80-dis.c: Add support for GBZ80 opcodes.
 888
 889 2020-02-04  Alan Modra  <amodra@gmail.com>
 890
 891         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 892
 893 2020-02-03  Alan Modra  <amodra@gmail.com>
 894
 895         * m32c-ibld.c: Regenerate.
 896
 897 2020-02-01  Alan Modra  <amodra@gmail.com>
 898
 899         * frv-ibld.c: Regenerate.
 900
 901 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 902
 903         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 904         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 905         (OP_E_memory): Replace xmm_mdq_mode case label by
 906         vex_scalar_w_dq_mode one.
 907         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 908
 909 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 912         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 913         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 914         (intel_operand_size): Drop vex_w_dq_mode case label.
 915
 916 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 917
 918         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 919         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 920
 921 2020-01-30  Alan Modra  <amodra@gmail.com>
 922
 923         * m32c-ibld.c: Regenerate.
 924
 925 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 926
 927         * bpf-opc.c: Regenerate.
 928
 929 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 930
 931         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 932         (dis386): Use them to replace C2/C3 table entries.
 933         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 934         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 935         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 936         * i386-tbl.h: Re-generate.
 937
 938 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 941         forms.
 942         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 943         DefaultSize.
 944         * i386-tbl.h: Re-generate.
 945
 946 2020-01-30  Alan Modra  <amodra@gmail.com>
 947
 948         * tic4x-dis.c (tic4x_dp): Make unsigned.
 949
 950 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 951             Jan Beulich  <jbeulich@suse.com>
 952
 953         PR binutils/25445
 954         * i386-dis.c (MOVSXD_Fixup): New function.
 955         (movsxd_mode): New enum.
 956         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 957         (intel_operand_size): Handle movsxd_mode.
 958         (OP_E_register): Likewise.
 959         (OP_G): Likewise.
 960         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 961         register on movsxd.  Add movsxd with 16-bit destination register
 962         for AMD64 and Intel64 ISAs.
 963         * i386-tbl.h: Regenerated.
 964
 965 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 966
 967         PR 25403
 968         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 969         * aarch64-asm-2.c: Regenerate
 970         * aarch64-dis-2.c: Likewise.
 971         * aarch64-opc-2.c: Likewise.
 972
 973 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 974
 975         * i386-opc.tbl (sysret): Drop DefaultSize.
 976         * i386-tbl.h: Re-generate.
 977
 978 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 981         Dword.
 982         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 983         * i386-tbl.h: Re-generate.
 984
 985 2020-01-20  Nick Clifton  <nickc@redhat.com>
 986
 987         * po/de.po: Updated German translation.
 988         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 989         * po/uk.po: Updated Ukranian translation.
 990
 991 2020-01-20  Alan Modra  <amodra@gmail.com>
 992
 993         * hppa-dis.c (fput_const): Remove useless cast.
 994
 995 2020-01-20  Alan Modra  <amodra@gmail.com>
 996
 997         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 998
 999 2020-01-18  Nick Clifton  <nickc@redhat.com>
1000
1001         * configure: Regenerate.
1002         * po/opcodes.pot: Regenerate.
1003
1004 2020-01-18  Nick Clifton  <nickc@redhat.com>
1005
1006         Binutils 2.34 branch created.
1007
1008 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1009
1010         * opintl.h: Fix spelling error (seperate).
1011
1012 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1013
1014         * i386-opc.tbl: Add {vex} pseudo prefix.
1015         * i386-tbl.h: Regenerated.
1016
1017 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1018
1019         PR 25376
1020         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1021         (neon_opcodes): Likewise.
1022         (select_arm_features): Make sure we enable MVE bits when selecting
1023         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1024         any architecture.
1025
1026 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl: Drop stale comment from XOP section.
1029
1030 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1033         (extractps): Add VexWIG to SSE2AVX forms.
1034         * i386-tbl.h: Re-generate.
1035
1036 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1039         Size64 from and use VexW1 on SSE2AVX forms.
1040         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1041         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1042         * i386-tbl.h: Re-generate.
1043
1044 2020-01-15  Alan Modra  <amodra@gmail.com>
1045
1046         * tic4x-dis.c (tic4x_version): Make unsigned long.
1047         (optab, optab_special, registernames): New file scope vars.
1048         (tic4x_print_register): Set up registernames rather than
1049         malloc'd registertable.
1050         (tic4x_disassemble): Delete optable and optable_special.  Use
1051         optab and optab_special instead.  Throw away old optab,
1052         optab_special and registernames when info->mach changes.
1053
1054 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1055
1056         PR 25377
1057         * z80-dis.c (suffix): Use .db instruction to generate double
1058         prefix.
1059
1060 2020-01-14  Alan Modra  <amodra@gmail.com>
1061
1062         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1063         values to unsigned before shifting.
1064
1065 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1066
1067         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1068         flow instructions.
1069         (print_insn_thumb16, print_insn_thumb32): Likewise.
1070         (print_insn): Initialize the insn info.
1071         * i386-dis.c (print_insn): Initialize the insn info fields, and
1072         detect jumps.
1073
1074 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1075
1076         * arc-opc.c (C_NE): Make it required.
1077
1078 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1079
1080         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1081         reserved register name.
1082
1083 2020-01-13  Alan Modra  <amodra@gmail.com>
1084
1085         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1086         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1087
1088 2020-01-13  Alan Modra  <amodra@gmail.com>
1089
1090         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1091         result of wasm_read_leb128 in a uint64_t and check that bits
1092         are not lost when copying to other locals.  Use uint32_t for
1093         most locals.  Use PRId64 when printing int64_t.
1094
1095 2020-01-13  Alan Modra  <amodra@gmail.com>
1096
1097         * score-dis.c: Formatting.
1098         * score7-dis.c: Formatting.
1099
1100 2020-01-13  Alan Modra  <amodra@gmail.com>
1101
1102         * score-dis.c (print_insn_score48): Use unsigned variables for
1103         unsigned values.  Don't left shift negative values.
1104         (print_insn_score32): Likewise.
1105         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1106
1107 2020-01-13  Alan Modra  <amodra@gmail.com>
1108
1109         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1110
1111 2020-01-13  Alan Modra  <amodra@gmail.com>
1112
1113         * fr30-ibld.c: Regenerate.
1114
1115 2020-01-13  Alan Modra  <amodra@gmail.com>
1116
1117         * xgate-dis.c (print_insn): Don't left shift signed value.
1118         (ripBits): Formatting, use 1u.
1119
1120 2020-01-10  Alan Modra  <amodra@gmail.com>
1121
1122         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1123         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1124
1125 2020-01-10  Alan Modra  <amodra@gmail.com>
1126
1127         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1128         and XRREG value earlier to avoid a shift with negative exponent.
1129         * m10200-dis.c (disassemble): Similarly.
1130
1131 2020-01-09  Nick Clifton  <nickc@redhat.com>
1132
1133         PR 25224
1134         * z80-dis.c (ld_ii_ii): Use correct cast.
1135
1136 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1137
1138         PR 25224
1139         * z80-dis.c (ld_ii_ii): Use character constant when checking
1140         opcode byte value.
1141
1142 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1143
1144         * i386-dis.c (SEP_Fixup): New.
1145         (SEP): Define.
1146         (dis386_twobyte): Use it for sysenter/sysexit.
1147         (enum x86_64_isa): Change amd64 enumerator to value 1.
1148         (OP_J): Compare isa64 against intel64 instead of amd64.
1149         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1150         forms.
1151         * i386-tbl.h: Re-generate.
1152
1153 2020-01-08  Alan Modra  <amodra@gmail.com>
1154
1155         * z8k-dis.c: Include libiberty.h
1156         (instr_data_s): Make max_fetched unsigned.
1157         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1158         Don't exceed byte_info bounds.
1159         (output_instr): Make num_bytes unsigned.
1160         (unpack_instr): Likewise for nibl_count and loop.
1161         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1162         idx unsigned.
1163         * z8k-opc.h: Regenerate.
1164
1165 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1166
1167         * arc-tbl.h (llock): Use 'LLOCK' as class.
1168         (llockd): Likewise.
1169         (scond): Use 'SCOND' as class.
1170         (scondd): Likewise.
1171         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1172         (scondd): Likewise.
1173
1174 2020-01-06  Alan Modra  <amodra@gmail.com>
1175
1176         * m32c-ibld.c: Regenerate.
1177
1178 2020-01-06  Alan Modra  <amodra@gmail.com>
1179
1180         PR 25344
1181         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1182         Peek at next byte to prevent recursion on repeated prefix bytes.
1183         Ensure uninitialised "mybuf" is not accessed.
1184         (print_insn_z80): Don't zero n_fetch and n_used here,..
1185         (print_insn_z80_buf): ..do it here instead.
1186
1187 2020-01-04  Alan Modra  <amodra@gmail.com>
1188
1189         * m32r-ibld.c: Regenerate.
1190
1191 2020-01-04  Alan Modra  <amodra@gmail.com>
1192
1193         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1194
1195 2020-01-04  Alan Modra  <amodra@gmail.com>
1196
1197         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1198
1199 2020-01-04  Alan Modra  <amodra@gmail.com>
1200
1201         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1202
1203 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1204
1205         * aarch64-tbl.h (aarch64_opcode_table): Use
1206         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1207
1208 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1209
1210         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1211         forms of SUDOT and USDOT.
1212
1213 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1214
1215         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1216         uzip{1,2}.
1217         * opcodes/aarch64-dis-2.c: Re-generate.
1218
1219 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1220
1221         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1222         FMMLA encoding.
1223         * opcodes/aarch64-dis-2.c: Re-generate.
1224
1225 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1226
1227         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1228
1229 2020-01-01  Alan Modra  <amodra@gmail.com>
1230
1231         Update year range in copyright notice of all files.
1232
1233 For older changes see ChangeLog-2019
1234 \f
1235 Copyright (C) 2020 Free Software Foundation, Inc.
1236
1237 Copying and distribution of this file, with or without modification,
1238 are permitted in any medium without royalty provided the copyright
1239 notice and this notice are preserved.
1240
1241 Local Variables:
1242 mode: change-log
1243 left-margin: 8
1244 fill-column: 74
1245 version-control: never
1246 End: