opcodes/ChangeLog

   1 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
   2
   3         * arc-dis.c (struct arc_operand_iterator): New structure.
   4         (find_format_from_table): All the old content from find_format,
   5         with some minor adjustments, and parameter renaming.
   6         (find_format_long_instructions): New function.
   7         (find_format): Rewritten.
   8         (arc_insn_length): Add LSB parameter.
   9         (extract_operand_value): New function.
  10         (operand_iterator_next): New function.
  11         (print_insn_arc): Use new functions to find opcode, and iterator
  12         over operands.
  13         * arc-opc.c (insert_nps_3bit_dst_short): New function.
  14         (extract_nps_3bit_dst_short): New function.
  15         (insert_nps_3bit_src2_short): New function.
  16         (extract_nps_3bit_src2_short): New function.
  17         (insert_nps_bitop1_size): New function.
  18         (extract_nps_bitop1_size): New function.
  19         (insert_nps_bitop2_size): New function.
  20         (extract_nps_bitop2_size): New function.
  21         (insert_nps_bitop_mod4_msb): New function.
  22         (extract_nps_bitop_mod4_msb): New function.
  23         (insert_nps_bitop_mod4_lsb): New function.
  24         (extract_nps_bitop_mod4_lsb): New function.
  25         (insert_nps_bitop_dst_pos3_pos4): New function.
  26         (extract_nps_bitop_dst_pos3_pos4): New function.
  27         (insert_nps_bitop_ins_ext): New function.
  28         (extract_nps_bitop_ins_ext): New function.
  29         (arc_operands): Add new operands.
  30         (arc_long_opcodes): New global array.
  31         (arc_num_long_opcodes): New global.
  32         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
  33
  34 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  35
  36         * nds32-asm.h: Add extern "C".
  37         * sh-opc.h: Likewise.
  38
  39 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
  40
  41         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
  42         0,b,limm to the rflt instruction.
  43
  44 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  45
  46         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
  47         constant.
  48
  49 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
  50
  51         PR gas/20145
  52         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
  53         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
  54         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
  55         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
  56         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
  57         * i386-init.h: Regenerated.
  58
  59 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  60
  61         PR gas/20145
  62         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
  63         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
  64         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
  65         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
  66         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
  67         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
  68         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
  69         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
  70         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
  71         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
  72         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
  73         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
  74         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
  75         CpuRegMask for AVX512.
  76         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
  77         and CpuRegMask.
  78         (set_bitfield_from_cpu_flag_init): New function.
  79         (set_bitfield): Remove const on f.  Call
  80         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
  81         * i386-opc.h (CpuRegMMX): New.
  82         (CpuRegXMM): Likewise.
  83         (CpuRegYMM): Likewise.
  84         (CpuRegZMM): Likewise.
  85         (CpuRegMask): Likewise.
  86         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
  87         and cpuregmask.
  88         * i386-init.h: Regenerated.
  89         * i386-tbl.h: Likewise.
  90
  91 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  92
  93         PR gas/20154
  94         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
  95         (opcode_modifiers): Add AMD64 and Intel64.
  96         (main): Properly verify CpuMax.
  97         * i386-opc.h (CpuAMD64): Removed.
  98         (CpuIntel64): Likewise.
  99         (CpuMax): Set to CpuNo64.
 100         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 101         (AMD64): New.
 102         (Intel64): Likewise.
 103         (i386_opcode_modifier): Add amd64 and intel64.
 104         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 105         on call and jmp.
 106         * i386-init.h: Regenerated.
 107         * i386-tbl.h: Likewise.
 108
 109 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 110
 111         PR gas/20154
 112         * i386-gen.c (main): Fail if CpuMax is incorrect.
 113         * i386-opc.h (CpuMax): Set to CpuIntel64.
 114         * i386-tbl.h: Regenerated.
 115
 116 2016-05-27  Nick Clifton  <nickc@redhat.com>
 117
 118         PR target/20150
 119         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 120         (msp430dis_opcode_unsigned): New function.
 121         (msp430dis_opcode_signed): New function.
 122         (msp430_singleoperand): Use the new opcode reading functions.
 123         Only disassenmble bytes if they were successfully read.
 124         (msp430_doubleoperand): Likewise.
 125         (msp430_branchinstr): Likewise.
 126         (msp430x_callx_instr): Likewise.
 127         (print_insn_msp430): Check that it is safe to read bytes before
 128         attempting disassembly.  Use the new opcode reading functions.
 129
 130 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 131
 132         * ppc-opc.c (CY): New define.  Document it.
 133         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 134
 135 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 136
 137         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 138         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 139         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 140         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 141         CPU_ANY_AVX_FLAGS.
 142         * i386-init.h: Regenerated.
 143
 144 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         PR gas/20141
 147         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 148         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 149         * i386-init.h: Regenerated.
 150
 151 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 154         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 155         * i386-init.h: Regenerated.
 156
 157 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 158
 159         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 160         information.
 161         (print_insn_arc): Set insn_type information.
 162         * arc-opc.c (C_CC): Add F_CLASS_COND.
 163         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 164         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 165         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 166         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 167         (brne, brne_s, jeq_s, jne_s): Likewise.
 168
 169 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 170
 171         * arc-tbl.h (neg): New instruction variant.
 172
 173 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 174
 175         * arc-dis.c (find_format, find_format, get_auxreg)
 176         (print_insn_arc): Changed.
 177         * arc-ext.h (INSERT_XOP): Likewise.
 178
 179 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 180
 181         * tic54x-dis.c (sprint_mmr): Adjust.
 182         * tic54x-opc.c: Likewise.
 183
 184 2016-05-19  Alan Modra  <amodra@gmail.com>
 185
 186         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 187
 188 2016-05-19  Alan Modra  <amodra@gmail.com>
 189
 190         * ppc-opc.c: Formatting.
 191         (NSISIGNOPT): Define.
 192         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 193
 194 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 195
 196         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 197         replacing references to `micromips_ase' throughout.
 198         (_print_insn_mips): Don't use file-level microMIPS annotation to
 199         determine the disassembly mode with the symbol table.
 200
 201 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 202
 203         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 204
 205 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 206
 207         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 208         mips64r6.
 209         * mips-opc.c (D34): New macro.
 210         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 211
 212 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 213
 214         * i386-dis.c (prefix_table): Add RDPID instruction.
 215         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 216         (cpu_flags): Add RDPID bitfield.
 217         * i386-opc.h (enum): Add RDPID element.
 218         (i386_cpu_flags): Add RDPID field.
 219         * i386-opc.tbl: Add RDPID instruction.
 220         * i386-init.h: Regenerate.
 221         * i386-tbl.h: Regenerate.
 222
 223 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 224
 225         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 226         branch type of a symbol.
 227         (print_insn): Likewise.
 228
 229 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 230
 231         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 232         Mainline Security Extensions instructions.
 233         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 234         Extensions instructions.
 235         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 236         instructions.
 237         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 238         special registers.
 239
 240 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 241
 242         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 243
 244 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 245
 246         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 247         (arcExtMap_genOpcode): Likewise.
 248         * arc-opc.c (arg_32bit_rc): Define new variable.
 249         (arg_32bit_u6): Likewise.
 250         (arg_32bit_limm): Likewise.
 251
 252 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 253
 254         * aarch64-gen.c (VERIFIER): Define.
 255         * aarch64-opc.c (VERIFIER): Define.
 256         (verify_ldpsw): Use static linkage.
 257         * aarch64-opc.h (verify_ldpsw): Remove.
 258         * aarch64-tbl.h: Use VERIFIER for verifiers.
 259
 260 2016-04-28  Nick Clifton  <nickc@redhat.com>
 261
 262         PR target/19722
 263         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 264         * aarch64-opc.c (verify_ldpsw): New function.
 265         * aarch64-opc.h (verify_ldpsw): New prototype.
 266         * aarch64-tbl.h: Add initialiser for verifier field.
 267         (LDPSW): Set verifier to verify_ldpsw.
 268
 269 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         PR binutils/19983
 272         PR binutils/19984
 273         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 274         smaller than address size.
 275
 276 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 277
 278         * alpha-dis.c: Regenerate.
 279         * crx-dis.c: Likewise.
 280         * disassemble.c: Likewise.
 281         * epiphany-opc.c: Likewise.
 282         * fr30-opc.c: Likewise.
 283         * frv-opc.c: Likewise.
 284         * ip2k-opc.c: Likewise.
 285         * iq2000-opc.c: Likewise.
 286         * lm32-opc.c: Likewise.
 287         * lm32-opinst.c: Likewise.
 288         * m32c-opc.c: Likewise.
 289         * m32r-opc.c: Likewise.
 290         * m32r-opinst.c: Likewise.
 291         * mep-opc.c: Likewise.
 292         * mt-opc.c: Likewise.
 293         * or1k-opc.c: Likewise.
 294         * or1k-opinst.c: Likewise.
 295         * tic80-opc.c: Likewise.
 296         * xc16x-opc.c: Likewise.
 297         * xstormy16-opc.c: Likewise.
 298
 299 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 300
 301         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 302         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 303         calcsd, and calcxd instructions.
 304         * arc-opc.c (insert_nps_bitop_size): Delete.
 305         (extract_nps_bitop_size): Delete.
 306         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 307         (extract_nps_qcmp_m3): Define.
 308         (extract_nps_qcmp_m2): Define.
 309         (extract_nps_qcmp_m1): Define.
 310         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 311         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 312         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 313         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 314         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 315         NPS_QCMP_M3.
 316
 317 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 318
 319         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 320
 321 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 322
 323         * Makefile.in: Regenerated with automake 1.11.6.
 324         * aclocal.m4: Likewise.
 325
 326 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 327
 328         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 329         instructions.
 330         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 331         (extract_nps_cmem_uimm16): New function.
 332         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 333
 334 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 335
 336         * arc-dis.c (arc_insn_length): New function.
 337         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 338         (find_format): Change insnLen parameter to unsigned.
 339
 340 2016-04-13  Nick Clifton  <nickc@redhat.com>
 341
 342         PR target/19937
 343         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 344         the LD.B and LD.BU instructions.
 345
 346 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 347
 348         * arc-dis.c (find_format): Check for extension flags.
 349         (print_flags): New function.
 350         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 351         .extAuxRegister.
 352         * arc-ext.c (arcExtMap_coreRegName): Use
 353         LAST_EXTENSION_CORE_REGISTER.
 354         (arcExtMap_coreReadWrite): Likewise.
 355         (dump_ARC_extmap): Update printing.
 356         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 357         (arc_aux_regs): Add cpu field.
 358         * arc-regs.h: Add cpu field, lower case name aux registers.
 359
 360 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 361
 362         * arc-tbl.h: Add rtsc, sleep with no arguments.
 363
 364 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 365
 366         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 367         Initialize.
 368         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 369         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 370         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 371         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 372         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 373         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 374         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 375         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 376         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 377         (arc_opcode arc_opcodes): Null terminate the array.
 378         (arc_num_opcodes): Remove.
 379         * arc-ext.h (INSERT_XOP): Define.
 380         (extInstruction_t): Likewise.
 381         (arcExtMap_instName): Delete.
 382         (arcExtMap_insn): New function.
 383         (arcExtMap_genOpcode): Likewise.
 384         * arc-ext.c (ExtInstruction): Remove.
 385         (create_map): Zero initialize instruction fields.
 386         (arcExtMap_instName): Remove.
 387         (arcExtMap_insn): New function.
 388         (dump_ARC_extmap): More info while debuging.
 389         (arcExtMap_genOpcode): New function.
 390         * arc-dis.c (find_format): New function.
 391         (print_insn_arc): Use find_format.
 392         (arc_get_disassembler): Enable dump_ARC_extmap only when
 393         debugging.
 394
 395 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 396
 397         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 398         instruction bits out.
 399
 400 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 401
 402         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 403         * arc-opc.c (arc_flag_operands): Add new flags.
 404         (arc_flag_classes): Add new classes.
 405
 406 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 407
 408         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 409
 410 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 411
 412         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 413         encode1, rflt, crc16, and crc32 instructions.
 414         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 415         (arc_flag_classes): Add C_NPS_R.
 416         (insert_nps_bitop_size_2b): New function.
 417         (extract_nps_bitop_size_2b): Likewise.
 418         (insert_nps_bitop_uimm8): Likewise.
 419         (extract_nps_bitop_uimm8): Likewise.
 420         (arc_operands): Add new operand entries.
 421
 422 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 423
 424         * arc-regs.h: Add a new subclass field.  Add double assist
 425         accumulator register values.
 426         * arc-tbl.h: Use DPA subclass to mark the double assist
 427         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 428         * arc-opc.c (RSP): Define instead of SP.
 429         (arc_aux_regs): Add the subclass field.
 430
 431 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 432
 433         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 434
 435 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 436
 437         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 438         NPS_R_SRC1.
 439
 440 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 441
 442         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 443         issues.  No functional changes.
 444
 445 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 446
 447         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 448         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 449         (RTT): Remove duplicate.
 450         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 451         (PCT_CONFIG*): Remove.
 452         (D1L, D1H, D2H, D2L): Define.
 453
 454 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 455
 456         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 457
 458 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 459
 460         * arc-tbl.h (invld07): Remove.
 461         * arc-ext-tbl.h: New file.
 462         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 463         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 464
 465 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 466
 467         Fix -Wstack-usage warnings.
 468         * aarch64-dis.c (print_operands): Substitute size.
 469         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 470
 471 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 472
 473         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 474         to get a proper diagnostic when an invalid ASR register is used.
 475
 476 2016-03-22  Nick Clifton  <nickc@redhat.com>
 477
 478         * configure: Regenerate.
 479
 480 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 481
 482         * arc-nps400-tbl.h: New file.
 483         * arc-opc.c: Add top level comment.
 484         (insert_nps_3bit_dst): New function.
 485         (extract_nps_3bit_dst): New function.
 486         (insert_nps_3bit_src2): New function.
 487         (extract_nps_3bit_src2): New function.
 488         (insert_nps_bitop_size): New function.
 489         (extract_nps_bitop_size): New function.
 490         (arc_flag_operands): Add nps400 entries.
 491         (arc_flag_classes): Add nps400 entries.
 492         (arc_operands): Add nps400 entries.
 493         (arc_opcodes): Add nps400 include.
 494
 495 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 496
 497         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 498         the new class enum values.
 499
 500 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 501
 502         * arc-dis.c (print_insn_arc): Handle nps400.
 503
 504 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 505
 506         * arc-opc.c (BASE): Delete.
 507
 508 2016-03-18  Nick Clifton  <nickc@redhat.com>
 509
 510         PR target/19721
 511         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 512         of MOV insn that aliases an ORR insn.
 513
 514 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 515
 516         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 517
 518 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 519
 520         * mcore-opc.h: Add const qualifiers.
 521         * microblaze-opc.h (struct op_code_struct): Likewise.
 522         * sh-opc.h: Likewise.
 523         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 524         (tic4x_print_op): Likewise.
 525
 526 2016-03-02  Alan Modra  <amodra@gmail.com>
 527
 528         * or1k-desc.h: Regenerate.
 529         * fr30-ibld.c: Regenerate.
 530         * rl78-decode.c: Regenerate.
 531
 532 2016-03-01  Nick Clifton  <nickc@redhat.com>
 533
 534         PR target/19747
 535         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 536
 537 2016-02-24  Renlin Li  <renlin.li@arm.com>
 538
 539         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 540         (print_insn_coprocessor): Support fp16 instructions.
 541
 542 2016-02-24  Renlin Li  <renlin.li@arm.com>
 543
 544         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 545         vminnm, vrint(mpna).
 546
 547 2016-02-24  Renlin Li  <renlin.li@arm.com>
 548
 549         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 550         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 551
 552 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         * i386-dis.c (print_insn): Parenthesize expression to prevent
 555         truncated addresses.
 556         (OP_J): Likewise.
 557
 558 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 559             Janek van Oirschot  <jvanoirs@synopsys.com>
 560
 561         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 562         variable.
 563
 564 2016-02-04  Nick Clifton  <nickc@redhat.com>
 565
 566         PR target/19561
 567         * msp430-dis.c (print_insn_msp430): Add a special case for
 568         decoding an RRC instruction with the ZC bit set in the extension
 569         word.
 570
 571 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 572
 573         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 574         * epiphany-ibld.c: Regenerate.
 575         * fr30-ibld.c: Regenerate.
 576         * frv-ibld.c: Regenerate.
 577         * ip2k-ibld.c: Regenerate.
 578         * iq2000-ibld.c: Regenerate.
 579         * lm32-ibld.c: Regenerate.
 580         * m32c-ibld.c: Regenerate.
 581         * m32r-ibld.c: Regenerate.
 582         * mep-ibld.c: Regenerate.
 583         * mt-ibld.c: Regenerate.
 584         * or1k-ibld.c: Regenerate.
 585         * xc16x-ibld.c: Regenerate.
 586         * xstormy16-ibld.c: Regenerate.
 587
 588 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 589
 590         * epiphany-dis.c: Regenerated from latest cpu files.
 591
 592 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 593
 594         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 595         test bit.
 596
 597 2016-01-25  Renlin Li  <renlin.li@arm.com>
 598
 599         * arm-dis.c (mapping_symbol_for_insn): New function.
 600         (find_ifthen_state): Call mapping_symbol_for_insn().
 601
 602 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 603
 604         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 605         of MSR UAO immediate operand.
 606
 607 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 608
 609         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 610         instruction support.
 611
 612 2016-01-17  Alan Modra  <amodra@gmail.com>
 613
 614         * configure: Regenerate.
 615
 616 2016-01-14  Nick Clifton  <nickc@redhat.com>
 617
 618         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 619         instructions that can support stack pointer operations.
 620         * rl78-decode.c: Regenerate.
 621         * rl78-dis.c: Fix display of stack pointer in MOVW based
 622         instructions.
 623
 624 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 625
 626         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 627         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 628         erxtatus_el1 and erxaddr_el1.
 629
 630 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 631
 632         * arm-dis.c (arm_opcodes): Add "esb".
 633         (thumb_opcodes): Likewise.
 634
 635 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 636
 637         * ppc-opc.c <xscmpnedp>: Delete.
 638         <xvcmpnedp>: Likewise.
 639         <xvcmpnedp.>: Likewise.
 640         <xvcmpnesp>: Likewise.
 641         <xvcmpnesp.>: Likewise.
 642
 643 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 644
 645         PR gas/13050
 646         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 647         addition to ISA_A.
 648
 649 2016-01-01  Alan Modra  <amodra@gmail.com>
 650
 651         Update year range in copyright notice of all files.
 652
 653 For older changes see ChangeLog-2015
 654 \f
 655 Copyright (C) 2016 Free Software Foundation, Inc.
 656
 657 Copying and distribution of this file, with or without modification,
 658 are permitted in any medium without royalty provided the copyright
 659 notice and this notice are preserved.
 660
 661 Local Variables:
 662 mode: change-log
 663 left-margin: 8
 664 fill-column: 74
 665 version-control: never
 666 End: