opcodes/ChangeLog

   1 2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
   2
   3         * aarch64-opc.c (CPENT): New define.
   4         (F_READONLY, F_WRITEONLY): Likewise.
   5         (aarch64_sys_regs): Add trace unit registers.
   6         (aarch64_sys_reg_readonly_p): New function.
   7         (aarch64_sys_reg_writeonly_p): Ditto.
   8
   9 2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
  10
  11         * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
  12         "mtcr".
  13
  14 2013-11-11  Catherine Moore  <clm@codesourcery.com>
  15
  16         * mips-dis.c (print_insn_mips): Use
  17         INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
  18         (print_insn_micromips): Likewise.
  19         * mips-opc.c (LDD): Remove.
  20         (CLD): Include INSN_LOAD_MEMORY.
  21         (LM): New.
  22         (mips_builtin_opcodes): Use LM instead of LDD.
  23         Add LM to load instructions.
  24
  25 2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  26
  27         PR gas/16140
  28         * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
  29         * i386-init.h: Regenerated.
  30
  31 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  32
  33         * aarch64-opc.c (F_DEPRECATED): New macro.
  34         (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
  35         F_DEPRECATED.
  36         (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
  37         AARCH64_OPND_SYSREG.
  38
  39 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  40
  41         * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
  42         (convert_from_csel): Likewise.
  43         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  44         AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
  45         (aarch64_print_operand): Handle AARCH64_OPND_COND1.
  46         * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
  47         COND for cinc, cset, cinv, csetm and cneg.
  48         (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
  49         * aarch64-asm-2.c: Re-generated.
  50         * aarch64-dis-2.c: Ditto.
  51         * aarch64-opc-2.c: Ditto.
  52
  53 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
  54
  55         * aarch64-opc.c (set_syntax_error): New function.
  56         (operand_general_constraint_met_p): Replace set_other_error
  57         with set_syntax_error.
  58
  59 2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
  60
  61         * s390-dis.c (init_disasm): Default to full 'zarch' opcode
  62         availability even for 31-bit programs.
  63
  64 2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
  65
  66         * arm-dis.c (neon_opcodes): Adjust print string for vshll.
  67
  68 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  69
  70         * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
  71         +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
  72         +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  73         (MSA): New define.
  74         (MSA64): New define.
  75         (micromips_opcodes): Add MSA instructions.
  76         * mips-dis.c (msa_control_names): New array.
  77         (mips_abi_choice): Add ASE_MSA to mips32r2.
  78         Remove ASE_MDMX from mips64r2.
  79         Add ASE_MSA and ASE_MSA64 to mips64r2.
  80         (parse_mips_dis_option): Handle -Mmsa.
  81         (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
  82         (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
  83         (print_mips_disassembler_options): Print -Mmsa.
  84         * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
  85         +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
  86         (MSA): New define.
  87         (MSA64): New define.
  88         (mips_builtin_op): Add MSA instructions.
  89
  90 2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
  91
  92         * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
  93         as the primary name of r30.
  94
  95 2013-10-12  Jan Beulich <jbeulich@suse.com>
  96
  97         * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
  98         default case.
  99         (OP_E_register): Move v_bnd_mode alongside m_mode.
 100         * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
 101         Drop Reg16 and Disp16. Add NoRex64.
 102         (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
 103         * i386-tbl.h: Re-generate.
 104
 105 2013-10-10  Sean Keys <skeys@ipdatasys.com>
 106
 107         * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
 108         table.
 109         * xgate-dis.c (print_insn): Refactor to work with table change.
 110
 111 2013-10-10  Roland McGrath  <mcgrathr@google.com>
 112
 113         * i386-dis.c (oappend_maybe_intel): New function.
 114         (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
 115         (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
 116         (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
 117
 118         * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
 119         possible compiler warnings when the union's initializer is
 120         actually meant for the 'preg' enum typed member.
 121         * crx-opc.c (REG): Likewise.
 122
 123         * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
 124         Remove duplicate const qualifier.
 125
 126 2013-10-08  Jan Beulich <jbeulich@suse.com>
 127
 128         * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
 129         (clflush): Use Anysize instead of Byte|Unspecified.
 130         (prefetch*): Likewise.
 131         * i386-tbl.h: Re-generate.
 132
 133 2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 134
 135         * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
 136
 137 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
 140         * i386-init.h: Regenerated.
 141
 142 2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 143
 144         * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
 145         * i386-init.h: Regenerated.
 146
 147 2013-09-20  Alan Modra  <amodra@gmail.com>
 148
 149         * configure: Regenerate.
 150
 151 2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 152
 153         * s390-opc.txt (clih): Make the immediate unsigned.
 154
 155 2013-09-04  Roland McGrath  <mcgrathr@google.com>
 156
 157         PR gas/15914
 158         * arm-dis.c (arm_opcodes): Add udf.
 159         (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
 160         (thumb32_opcodes): Add udf.w.
 161         (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
 162
 163 2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 164
 165         * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
 166         For the load fp integer instructions only the suppression flag was
 167         new with z196 version.
 168
 169 2013-08-28  Nick Clifton  <nickc@redhat.com>
 170
 171         * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
 172         immediate is not suitable for the 32-bit ABI.
 173
 174 2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
 175
 176         * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
 177         replacing NODS.
 178
 179 2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
 180
 181         PR binutils/15834
 182         * aarch64-asm.c: Fix typos.
 183         * aarch64-dis.c: Likewise.
 184         * msp430-dis.c: Likewise.
 185
 186 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 187
 188         * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
 189         macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
 190         Use +H rather than +C for the real "dext".
 191         * mips-opc.c (mips_builtin_opcodes): Likewise.
 192
 193 2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
 194
 195         * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
 196         * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
 197         and OPTIONAL_MAPPED_REG.
 198         * mips-opc.c (decode_mips_operand): Likewise.
 199         * mips16-opc.c (decode_mips16_operand): Likewise.
 200         * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
 201
 202 2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
 205         (PREFIX_EVEX_0F3A3F): Likewise.
 206         * i386-dis-evex.h (evex_table): Updated.
 207
 208 2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
 209
 210         * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
 211         VCLIPW.
 212
 213 2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
 214             Konrad Eisele  <konrad@gaisler.com>
 215
 216         * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
 217         bfd_mach_sparc.
 218         * sparc-opc.c (MASK_LEON): Define.
 219         (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
 220         (letandleon): New macro.
 221         (v9andleon): Likewise.
 222         (sparc_opc): Add leon.
 223         (umac): Enable for letandleon.
 224         (smac): Likewise.
 225         (casa): Enable for v9andleon.
 226         (cas): Likewise.
 227         (casl): Likewise.
 228
 229 2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
 230             Richard Sandiford  <rdsandiford@googlemail.com>
 231
 232         * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
 233         OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
 234         (print_vu0_channel): New function.
 235         (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
 236         (print_insn_args): Handle '#'.
 237         (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
 238         * mips-opc.c (mips_vu0_channel_mask): New constant.
 239         (decode_mips_operand): Handle new VU0 operand types.
 240         (VU0, VU0CH): New macros.
 241         (mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
 242         for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
 243         Use "+6" rather than "G" for QMFC2 and QMTC2.
 244
 245 2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
 246
 247         * mips-formats.h (PCREL): Reorder parameters and update the definition
 248         to match new mips_pcrel_operand layout.
 249         (JUMP, JALX, BRANCH): Update accordingly.
 250         * mips16-opc.c (decode_mips16_operand): Likewise.
 251
 252 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 253
 254         * micromips-opc.c (WR_s): Delete.
 255
 256 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 257
 258         * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
 259         New macros.
 260         (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
 261         (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
 262         (mips_builtin_opcodes): Use the new position-based read-write flags
 263         instead of field-based ones.  Use UDI for "udi..." instructions.
 264         * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 265         New macros.
 266         (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
 267         (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
 268         (WR_SP, RD_16): New macros.
 269         (RD_SP): Redefine as an INSN2_* flag.
 270         (MOD_SP): Redefine in terms of RD_SP and WR_SP.
 271         (mips16_opcodes): Use the new position-based read-write flags
 272         instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
 273         pinfo2 field.
 274         * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
 275         New macros.
 276         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
 277         (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
 278         (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
 279         (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
 280         (micromips_opcodes): Use the new position-based read-write flags
 281         instead of field-based ones.
 282         * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
 283         (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
 284         of field-based flags.
 285
 286 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 287
 288         * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
 289         (WR_SP): Replace with...
 290         (MOD_SP): ...this.
 291         (mips16_opcodes): Update accordingly.
 292         * mips-dis.c (print_insn_mips16): Likewise.
 293
 294 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 295
 296         * mips16-opc.c (mips16_opcodes): Reformat.
 297
 298 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 299
 300         * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
 301         for operands that are hard-coded to $0.
 302         * micromips-opc.c (micromips_opcodes): Likewise.
 303
 304 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 305
 306         * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 307         for the single-operand forms of JALR and JALR.HB.
 308         * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
 309         and JALRS.HB.
 310
 311 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 312
 313         * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
 314         instructions.  Fix them to use WR_MACC instead of WR_CC and
 315         add missing RD_MACCs.
 316
 317 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 318
 319         * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 320
 321 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
 322
 323         * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
 324
 325 2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
 326             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 327             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 328             Sergey Lega  <sergey.s.lega@intel.com>
 329             Anna Tikhonova  <anna.tikhonova@intel.com>
 330             Ilya Tocar  <ilya.tocar@intel.com>
 331             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 332             Ilya Verbin  <ilya.verbin@intel.com>
 333             Kirill Yukhin  <kirill.yukhin@intel.com>
 334             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 335
 336         * i386-dis-evex.h: New.
 337         * i386-dis.c (OP_Rounding): New.
 338         (VPCMP_Fixup): New.
 339         (OP_Mask): New.
 340         (Rdq): New.
 341         (XMxmmq): New.
 342         (EXdScalarS): New.
 343         (EXymm): New.
 344         (EXEvexHalfBcstXmmq): New.
 345         (EXxmm_mdq): New.
 346         (EXEvexXGscat): New.
 347         (EXEvexXNoBcst): New.
 348         (VPCMP): New.
 349         (EXxEVexR): New.
 350         (EXxEVexS): New.
 351         (XMask): New.
 352         (MaskG): New.
 353         (MaskE): New.
 354         (MaskR): New.
 355         (MaskVex): New.
 356         (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
 357         evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
 358         evex_rounding_mode, evex_sae_mode, mask_mode.
 359         (USE_EVEX_TABLE): New.
 360         (EVEX_TABLE): New.
 361         (EVEX enum): New.
 362         (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
 363         REG_EVEX_0F38C7.
 364         (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
 365         MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
 366         MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
 367         MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 368         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
 369         MOD_EVEX_0F38C7_REG_6.
 370         (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 371         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
 372         PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 373         PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
 374         PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
 375         PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
 376         PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
 377         PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
 378         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
 379         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
 380         PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
 381         PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
 382         PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
 383         PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
 384         PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
 385         PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 386         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 387         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 388         PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
 389         PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
 390         PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
 391         PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
 392         PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
 393         PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
 394         PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
 395         PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
 396         PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
 397         PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
 398         PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
 399         PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
 400         PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
 401         PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
 402         PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
 403         PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
 404         PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
 405         PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
 406         PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 407         PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
 408         PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
 409         PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
 410         PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
 411         PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
 412         PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
 413         PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
 414         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
 415         PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
 416         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 417         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
 418         PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
 419         PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
 420         PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
 421         PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
 422         PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
 423         PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
 424         PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
 425         PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
 426         PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
 427         PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
 428         PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
 429         PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
 430         PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
 431         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
 432         PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
 433         PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
 434         PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
 435         PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
 436         PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
 437         PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
 438         PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
 439         PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
 440         PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
 441         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
 442         PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
 443         PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
 444         PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
 445         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
 446         PREFIX_EVEX_0F3A55.
 447         (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
 448         VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
 449         VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
 450         VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
 451         VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
 452         VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
 453         VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
 454         VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
 455         VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
 456         VEX_W_0F3A32_P_2_LEN_0.
 457         (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
 458         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
 459         EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
 460         EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
 461         EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
 462         EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 463         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
 464         EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
 465         EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 466         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
 467         EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 468         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
 469         EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
 470         EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
 471         EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
 472         EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
 473         EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
 474         EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
 475         EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
 476         EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
 477         EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
 478         EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
 479         EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
 480         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
 481         EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
 482         EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
 483         EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
 484         EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
 485         EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
 486         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
 487         EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
 488         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
 489         EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
 490         EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
 491         EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
 492         EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
 493         EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
 494         EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
 495         EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
 496         EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
 497         EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
 498         EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
 499         EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
 500         EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
 501         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
 502         EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
 503         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
 504         EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
 505         EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
 506         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
 507         EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
 508         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
 509         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
 510         EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
 511         (struct vex): Add fields evex, r, v, mask_register_specifier,
 512         zeroing, ll, b.
 513         (intel_names_xmm): Add upper 16 registers.
 514         (att_names_xmm): Ditto.
 515         (intel_names_ymm): Ditto.
 516         (att_names_ymm): Ditto.
 517         (names_zmm): New.
 518         (intel_names_zmm): Ditto.
 519         (att_names_zmm): Ditto.
 520         (names_mask): Ditto.
 521         (intel_names_mask): Ditto.
 522         (att_names_mask): Ditto.
 523         (names_rounding): Ditto.
 524         (names_broadcast): Ditto.
 525         (x86_64_table): Add escape to evex-table.
 526         (reg_table): Include reg_table evex-entries from
 527         i386-dis-evex.h.  Fix prefetchwt1 instruction.
 528         (prefix_table): Add entries for new instructions.
 529         (vex_table): Ditto.
 530         (vex_len_table): Ditto.
 531         (vex_w_table): Ditto.
 532         (mod_table): Ditto.
 533         (get_valid_dis386): Properly handle new instructions.
 534         (print_insn): Handle zmm and mask registers, print mask operand.
 535         (intel_operand_size): Support EVEX, new modes and sizes.
 536         (OP_E_register): Handle new modes.
 537         (OP_E_memory): Ditto.
 538         (OP_G): Ditto.
 539         (OP_XMM): Ditto.
 540         (OP_EX): Ditto.
 541         (OP_VEX): Ditto.
 542         * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
 543         CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
 544         CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 545         (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
 546         CpuAVX512PF and CpuVREX.
 547         (operand_type_init): Add OPERAND_TYPE_REGZMM,
 548         OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
 549         (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
 550         StaticRounding, SAE, Disp8MemShift, NoDefMask.
 551         (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
 552         * i386-init.h: Regenerate.
 553         * i386-opc.h (CpuAVX512F): New.
 554         (CpuAVX512CD): New.
 555         (CpuAVX512ER): New.
 556         (CpuAVX512PF): New.
 557         (CpuVREX): New.
 558         (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
 559         cpuavx512pf and cpuvrex fields.
 560         (VecSIB): Add VecSIB512.
 561         (EVex): New.
 562         (Masking): New.
 563         (VecESize): New.
 564         (Broadcast): New.
 565         (StaticRounding): New.
 566         (SAE): New.
 567         (Disp8MemShift): New.
 568         (NoDefMask): New.
 569         (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
 570         staticrounding, sae, disp8memshift and nodefmask.
 571         (RegZMM): New.
 572         (Zmmword): Ditto.
 573         (Vec_Disp8): Ditto.
 574         (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
 575         fields.
 576         (RegVRex): New.
 577         * i386-opc.tbl: Add AVX512 instructions.
 578         * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
 579         registers, mask registers.
 580         * i386-tbl.h: Regenerate.
 581
 582 2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
 583
 584         PR gas/15220
 585         * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
 586         Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
 587
 588 2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 589
 590         * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
 591         PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
 592         PREFIX_0F3ACC.
 593         (prefix_table): Updated.
 594         (three_byte_table): Likewise.
 595         * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
 596         (cpu_flags): Add CpuSHA.
 597         (i386_cpu_flags): Add cpusha.
 598         * i386-init.h: Regenerate.
 599         * i386-opc.h (CpuSHA): New.
 600         (CpuUnused): Restored.
 601         (i386_cpu_flags): Add cpusha.
 602         * i386-opc.tbl: Add SHA instructions.
 603         * i386-tbl.h: Regenerate.
 604
 605 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
 606             Kirill Yukhin  <kirill.yukhin@intel.com>
 607             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 608
 609         * i386-dis.c (BND_Fixup): New.
 610         (Ebnd): New.
 611         (Ev_bnd): New.
 612         (Gbnd): New.
 613         (BND): New.
 614         (v_bnd_mode): New.
 615         (bnd_mode): New.
 616         (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
 617         MOD_0F1B_PREFIX_1.
 618         (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
 619         (dis tables): Replace XX with BND for near branch and call
 620         instructions.
 621         (prefix_table): Add new entries.
 622         (mod_table): Likewise.
 623         (names_bnd): New.
 624         (intel_names_bnd): New.
 625         (att_names_bnd): New.
 626         (BND_PREFIX): New.
 627         (prefix_name): Handle BND_PREFIX.
 628         (print_insn): Initialize names_bnd.
 629         (intel_operand_size): Handle new modes.
 630         (OP_E_register): Likewise.
 631         (OP_E_memory): Likewise.
 632         (OP_G): Likewise.
 633         * i386-gen.c (cpu_flag_init): Add CpuMPX.
 634         (cpu_flags): Add CpuMPX.
 635         (operand_type_init): Add RegBND.
 636         (opcode_modifiers): Add BNDPrefixOk.
 637         (operand_types): Add RegBND.
 638         * i386-init.h: Regenerate.
 639         * i386-opc.h (CpuMPX): New.
 640         (CpuUnused): Comment out.
 641         (i386_cpu_flags): Add cpumpx.
 642         (BNDPrefixOk): New.
 643         (i386_opcode_modifier): Add bndprefixok.
 644         (RegBND): New.
 645         (i386_operand_type): Add regbnd.
 646         * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
 647         Add MPX instructions and bnd prefix.
 648         * i386-reg.tbl: Add bnd0-bnd3 registers.
 649         * i386-tbl.h: Regenerate.
 650
 651 2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
 652
 653         * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
 654         ATTRIBUTE_UNUSED.
 655
 656 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 657
 658         * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
 659         special rules.
 660         * Makefile.in: Regenerate.
 661         * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
 662         all fields.  Reformat.
 663
 664 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 665
 666         * mips16-opc.c: Include mips-formats.h.
 667         (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
 668         static arrays.
 669         (decode_mips16_operand): New function.
 670         * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
 671         (print_insn_arg): Handle OP_ENTRY_EXIT list.
 672         Abort for OP_SAVE_RESTORE_LIST.
 673         (print_mips16_insn_arg): Change interface.  Use mips_operand
 674         structures.  Delete GET_OP_S.  Move GET_OP definition to...
 675         (print_insn_mips16): ...here.  Call init_print_arg_state.
 676         Update the call to print_mips16_insn_arg.
 677
 678 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 679
 680         * mips-formats.h: New file.
 681         * mips-opc.c: Include mips-formats.h.
 682         (reg_0_map): New static array.
 683         (decode_mips_operand): New function.
 684         * micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
 685         (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
 686         (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
 687         (int_c_map): New static arrays.
 688         (decode_micromips_operand): New function.
 689         * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
 690         (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
 691         (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
 692         (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
 693         (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
 694         (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
 695         (micromips_imm_b_map, micromips_imm_c_map): Delete.
 696         (print_reg): New function.
 697         (mips_print_arg_state): New structure.
 698         (init_print_arg_state, print_insn_arg): New functions.
 699         (print_insn_args): Change interface and use mips_operand structures.
 700         Delete GET_OP_S.  Move GET_OP definition to...
 701         (print_insn_mips): ...here.  Update the call to print_insn_args.
 702         (print_insn_micromips): Use print_insn_args.
 703
 704 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 705
 706         * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
 707         in macros.
 708
 709 2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
 710
 711         * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
 712         ADDA.S, MULA.S and SUBA.S.
 713
 714 2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
 715
 716         PR gas/13572
 717         * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
 718         * i386-tbl.h: Regenerated.
 719
 720 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 721
 722         * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
 723         and SD A(B) macros up.
 724         * micromips-opc.c (micromips_opcodes): Likewise.
 725
 726 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 727
 728         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
 729         instructions.
 730
 731 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 732
 733         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
 734         MDMX-like instructions.
 735         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
 736         printing "Q" operands for INSN_5400 instructions.
 737
 738 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 739
 740         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
 741         "+S" for "cins".
 742         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
 743         Combine cases.
 744
 745 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 746
 747         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
 748         "jalx".
 749         * mips16-opc.c (mips16_opcodes): Likewise.
 750         * micromips-opc.c (micromips_opcodes): Likewise.
 751         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
 752         (print_insn_mips16): Handle "+i".
 753         (print_insn_micromips): Likewise.  Conditionally preserve the
 754         ISA bit for "a" but not for "+i".
 755
 756 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 757
 758         * micromips-opc.c (WR_mhi): Rename to..
 759         (WR_mh): ...this.
 760         (micromips_opcodes): Update "movep" entry accordingly.  Replace
 761         "mh,mi" with "mh".
 762         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
 763         (micromips_to_32_reg_h_map1): ...this.
 764         (micromips_to_32_reg_i_map): Rename to...
 765         (micromips_to_32_reg_h_map2): ...this.
 766         (print_micromips_insn): Remove "mi" case.  Print both registers
 767         in the pair for "mh".
 768
 769 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
 770
 771         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
 772         * micromips-opc.c (micromips_opcodes): Likewise.
 773         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
 774         and "+T" handling.  Check for a "0" suffix when deciding whether to
 775         use coprocessor 0 names.  In that case, also check for ",H" selectors.
 776
 777 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 778
 779         * s390-opc.c (J12_12, J24_24): New macros.
 780         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
 781         (MASK_MII_UPI): Rename to MASK_MII_UPP.
 782         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
 783
 784 2013-07-04  Alan Modra  <amodra@gmail.com>
 785
 786         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
 787
 788 2013-06-26  Nick Clifton  <nickc@redhat.com>
 789
 790         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
 791         field when checking for type 2 nop.
 792         * rx-decode.c: Regenerate.
 793
 794 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
 795
 796         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
 797         and "movep" macros.
 798
 799 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
 800
 801         * mips-dis.c (is_mips16_plt_tail): New function.
 802         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
 803         word.
 804         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
 805
 806 2013-06-21  DJ Delorie  <dj@redhat.com>
 807
 808         * msp430-decode.opc: New.
 809         * msp430-decode.c: New/generated.
 810         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
 811         (MAINTAINER_CLEANFILES): Likewise.
 812         Add rule to build msp430-decode.c frommsp430decode.opc
 813         using the opc2c program.
 814         * Makefile.in: Regenerate.
 815         * configure.in: Add msp430-decode.lo to msp430 architecture files.
 816         * configure: Regenerate.
 817
 818 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
 819
 820         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
 821         (SYMTAB_AVAILABLE): Removed.
 822         (#include "elf/aarch64.h): Ditto.
 823
 824 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 825             Maciej W. Rozycki  <macro@codesourcery.com>
 826             Chao-Ying Fu  <fu@mips.com>
 827
 828         * micromips-opc.c (EVA): Define.
 829         (TLBINV): Define.
 830         (micromips_opcodes): Add EVA opcodes.
 831         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 832         (print_insn_args): Handle EVA offsets.
 833         (print_insn_micromips): Likewise.
 834         * mips-opc.c (EVA): Define.
 835         (TLBINV): Define.
 836         (mips_builtin_opcodes): Add EVA opcodes.
 837
 838 2013-06-17  Alan Modra  <amodra@gmail.com>
 839
 840         * Makefile.am (mips-opc.lo): Add rules to create automatic
 841         dependency files.  Pass archdefs.
 842         (micromips-opc.lo, mips16-opc.lo): Likewise.
 843         * Makefile.in: Regenerate.
 844
 845 2013-06-14  DJ Delorie  <dj@redhat.com>
 846
 847         * rx-decode.opc (rx_decode_opcode): Bit operations on
 848         registers are 32-bit operations, not 8-bit operations.
 849         * rx-decode.c: Regenerate.
 850
 851 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 852
 853         * micromips-opc.c (IVIRT): New define.
 854         (IVIRT64): New define.
 855         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 856         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 857
 858         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 859         dmtgc0 to print cp0 names.
 860
 861 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 862
 863         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 864         argument.
 865
 866 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 867             Richard Sandiford  <rdsandiford@googlemail.com>
 868
 869         * micromips-opc.c (D32, D33, MC): Update definitions.
 870         (micromips_opcodes):  Initialize ase field.
 871         * mips-dis.c (mips_arch_choice): Add ase field.
 872         (mips_arch_choices): Initialize ase field.
 873         (set_default_mips_dis_options): Declare and setup mips_ase.
 874         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 875         MT32, MC): Update definitions.
 876         (mips_builtin_opcodes): Initialize ase field.
 877
 878 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 879
 880         * s390-opc.txt (flogr): Require a register pair destination.
 881
 882 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 883
 884         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 885         instruction format.
 886
 887 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 888
 889         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 890
 891 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 892
 893         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 894         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 895         XLS_MASK, PPCVSX2): New defines.
 896         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 897         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 898         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 899         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 900         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 901         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 902         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 903         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 904         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 905         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 906         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 907         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 908         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 909         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 910         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 911         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 912         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 913         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 914         <lxvx, stxvx>: New extended mnemonics.
 915
 916 2013-05-17  Alan Modra  <amodra@gmail.com>
 917
 918         * ia64-raw.tbl: Replace non-ASCII char.
 919         * ia64-waw.tbl: Likewise.
 920         * ia64-asmtab.c: Regenerate.
 921
 922 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 923
 924         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 925         * i386-init.h: Regenerated.
 926
 927 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 928
 929         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 930         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 931         check from [0, 255] to [-128, 255].
 932
 933 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 934
 935         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 936         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 937         (parse_mips_dis_option): Handle the virt option.
 938         (print_insn_args): Handle "+J".
 939         (print_mips_disassembler_options): Print out message about virt64.
 940         * mips-opc.c (IVIRT): New define.
 941         (IVIRT64): New define.
 942         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 943         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 944         Move rfe to the bottom as it conflicts with tlbgp.
 945
 946 2013-05-09  Alan Modra  <amodra@gmail.com>
 947
 948         * ppc-opc.c (extract_vlesi): Properly sign extend.
 949         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 950
 951 2013-05-02  Nick Clifton  <nickc@redhat.com>
 952
 953         * msp430-dis.c: Add support for MSP430X instructions.
 954
 955 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 956
 957         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 958         to "eccinj".
 959
 960 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 961
 962         PR binutils/15369
 963         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 964         of CGEN_CPU_ENDIAN.
 965         (hash_insns_list): Likewise.
 966
 967 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 968
 969         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 970         warning workaround.
 971
 972 2013-04-08  Jan Beulich <jbeulich@suse.com>
 973
 974         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 975         * i386-tbl.h: Re-generate.
 976
 977 2013-04-06  David S. Miller  <davem@davemloft.net>
 978
 979         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 980         of an opcode, prefer the one with F_PREFERRED set.
 981         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 982         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 983         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 984         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 985         instructions generating condition codes, mark existing mnenomics
 986         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 987         existing mnenomics as aliases.
 988
 989 2013-04-03  Nick Clifton  <nickc@redhat.com>
 990
 991         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 992         destination address by subtracting the operand from the current
 993         address.
 994         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 995         a positive value in the insn.
 996         (extract_u16_loop): Do not negate the returned value.
 997         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 998
 999         (ceilf.sw): Remove duplicate entry.
1000         (cvtf.hs): New entry.
1001         (cvtf.sh): Likewise.
1002         (fmaf.s): Likewise.
1003         (fmsf.s): Likewise.
1004         (fnmaf.s): Likewise.
1005         (fnmsf.s): Likewise.
1006         (maddf.s): Restrict to E3V5 architectures.
1007         (msubf.s): Likewise.
1008         (nmaddf.s): Likewise.
1009         (nmsubf.s): Likewise.
1010
1011 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
1012
1013         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
1014         check address mode.
1015         (print_insn): Pass sizeflag to get_sib.
1016
1017 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
1018
1019         PR binutils/15068
1020         * tic6x-dis.c: Add support for displaying 16-bit insns.
1021
1022 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
1023
1024         PR gas/15095
1025         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1026         individual msb and lsb halves in src1 & src2 fields.  Discard the
1027         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1028         follow what Ti SDK does in that case as any value in the src1
1029         field yields the same output with SDK disassembler.
1030
1031 2013-03-12  Michael Eager <eager@eagercon.com>
1032
1033         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
1034
1035 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1036
1037         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1038
1039 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1040
1041         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1042
1043 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
1044
1045         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1046
1047 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1048
1049         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1050         (thumb32_opcodes): Likewise.
1051         (print_insn_thumb32): Handle 'S' control char.
1052
1053 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
1054
1055         * lm32-desc.c: Regenerate.
1056
1057 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1058
1059         * i386-reg.tbl (riz): Add RegRex64.
1060         * i386-tbl.h: Regenerated.
1061
1062 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
1063
1064         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1065         (aarch64_feature_crc): New static.
1066         (CRC): New macro.
1067         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1068         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1069         * aarch64-asm-2.c: Re-generate.
1070         * aarch64-dis-2.c: Ditto.
1071         * aarch64-opc-2.c: Ditto.
1072
1073 2013-02-27  Alan Modra  <amodra@gmail.com>
1074
1075         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1076         * rl78-decode.c: Regenerate.
1077
1078 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
1079
1080         * rl78-decode.opc: Fix encoding of DIVWU insn.
1081         * rl78-decode.c: Regenerate.
1082
1083 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         PR gas/15159
1086         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1087
1088         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1089         (cpu_flags): Add CpuSMAP.
1090
1091         * i386-opc.h (CpuSMAP): New.
1092         (i386_cpu_flags): Add cpusmap.
1093
1094         * i386-opc.tbl: Add clac and stac.
1095
1096         * i386-init.h: Regenerated.
1097         * i386-tbl.h: Likewise.
1098
1099 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
1100
1101         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1102         which also makes the disassembler output be in little
1103         endian like it should be.
1104
1105 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
1106
1107         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1108         fields to NULL.
1109         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1110
1111 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
1112
1113         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1114         section disassembled.
1115
1116 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1117
1118         * arm-dis.c: Update strht pattern.
1119
1120 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
1121
1122         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1123         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
1124         trunc.w.s macro for EE.
1125
1126 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
1127             Andrew Jenner <andrew@codesourcery.com>
1128
1129         Based on patches from Altera Corporation.
1130
1131         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1132         nios2-opc.c.
1133         * Makefile.in: Regenerated.
1134         * configure.in: Add case for bfd_nios2_arch.
1135         * configure: Regenerated.
1136         * disassemble.c (ARCH_nios2): Define.
1137         (disassembler): Add case for bfd_arch_nios2.
1138         * nios2-dis.c: New file.
1139         * nios2-opc.c: New file.
1140
1141 2013-02-04  Alan Modra  <amodra@gmail.com>
1142
1143         * po/POTFILES.in: Regenerate.
1144         * rl78-decode.c: Regenerate.
1145         * rx-decode.c: Regenerate.
1146
1147 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
1148
1149         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1150         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
1151         * aarch64-asm.c (convert_xtl_to_shll): New function.
1152         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1153         calling convert_xtl_to_shll.
1154         * aarch64-dis.c (convert_shll_to_xtl): New function.
1155         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1156         calling convert_shll_to_xtl.
1157         * aarch64-gen.c: Update copyright year.
1158         * aarch64-asm-2.c: Re-generate.
1159         * aarch64-dis-2.c: Re-generate.
1160         * aarch64-opc-2.c: Re-generate.
1161
1162 2013-01-24  Nick Clifton  <nickc@redhat.com>
1163
1164         * v850-dis.c: Add support for e3v5 architecture.
1165         * v850-opc.c: Likewise.
1166
1167 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
1168
1169         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1170         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1171         * aarch64-opc.c (operand_general_constraint_met_p): For
1172         AARCH64_MOD_LSL, move the range check on the shift amount before the
1173         alignment check; change to call set_sft_amount_out_of_range_error
1174         instead of set_imm_out_of_range_error.
1175         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1176         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1177         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1178         SIMD_IMM_SFT.
1179
1180 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
1181
1182         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1183
1184         * i386-init.h: Regenerated.
1185         * i386-tbl.h: Likewise.
1186
1187 2013-01-15  Nick Clifton  <nickc@redhat.com>
1188
1189         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1190         values.
1191         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1192
1193 2013-01-14  Will Newton <will.newton@imgtec.com>
1194
1195         * metag-dis.c (REG_WIDTH): Increase to 64.
1196
1197 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
1198
1199         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1200         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1201         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1202         (SH6): Update.
1203         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1204         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1205         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1206         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1207
1208 2013-01-10  Will Newton <will.newton@imgtec.com>
1209
1210         * Makefile.am: Add Meta.
1211         * configure.in: Add Meta.
1212         * disassemble.c: Add Meta support.
1213         * metag-dis.c: New file.
1214         * Makefile.in: Regenerate.
1215         * configure: Regenerate.
1216
1217 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1218
1219         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1220         (match_opcode): Rename to cr16_match_opcode.
1221
1222 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
1223
1224         * mips-dis.c: Add names for CP0 registers of r5900.
1225         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1226         instructions sq and lq.
1227         Add support for MIPS r5900 CPU.
1228         Add support for 128 bit MMI (Multimedia Instructions).
1229         Add support for EE instructions (Emotion Engine).
1230         Disable unsupported floating point instructions (64 bit and
1231         undefined compare operations).
1232         Enable instructions of MIPS ISA IV which are supported by r5900.
1233         Disable 64 bit co processor instructions.
1234         Disable 64 bit multiplication and division instructions.
1235         Disable instructions for co-processor 2 and 3, because these are
1236         not supported (preparation for later VU0 support (Vector Unit)).
1237         Disable cvt.w.s because this behaves like trunc.w.s and the
1238         correct execution can't be ensured on r5900.
1239         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1240         will confuse less developers and compilers.
1241
1242 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1243
1244         * aarch64-opc.c (aarch64_print_operand): Change to print
1245         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1246         in comment.
1247         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1248         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1249         OP_MOV_IMM_WIDE.
1250
1251 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
1252
1253         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1254         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1255
1256 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
1257
1258         * i386-gen.c (process_copyright): Update copyright year to 2013.
1259
1260 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
1261
1262         * cr16-dis.c (match_opcode,make_instruction): Remove static
1263         declaration.
1264         (dwordU,wordU): Moved typedefs to opcode/cr16.h
1265         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1266
1267 For older changes see ChangeLog-2012
1268 \f
1269 Copyright (C) 2013 Free Software Foundation, Inc.
1270
1271 Copying and distribution of this file, with or without modification,
1272 are permitted in any medium without royalty provided the copyright
1273 notice and this notice are preserved.
1274
1275 Local Variables:
1276 mode: change-log
1277 left-margin: 8
1278 fill-column: 74
1279 version-control: never
1280 End: