1 2006-05-25 Richard Sandiford <richard@codesourcery.com>
3 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
4 and fmovem entries. Put register list entries before immediate
5 mask entries. Use "l" rather than "L" in the fmovem entries.
6 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
8 (m68k_scan_mask): New function, split out from...
9 (print_insn_m68k): ...here. If no architecture has been set,
10 first try printing an m680x0 instruction, then try a Coldfire one.
12 2006-05-24 Nick Clifton <nickc@redhat.com>
14 * po/ga.po: Updated Irish translation.
16 2006-05-22 Nick Clifton <nickc@redhat.com>
18 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
20 2006-05-22 Nick Clifton <nickc@redhat.com>
22 * po/nl.po: Updated translation.
24 2006-05-18 Alan Modra <amodra@bigpond.net.au>
26 * avr-dis.c: Formatting fix.
28 2006-05-14 Thiemo Seufer <ths@mips.com>
30 * mips16-opc.c (I1, I32, I64): New shortcut defines.
31 (mips16_opcodes): Change membership of instructions to their
34 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
36 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
38 2006-05-05 Julian Brown <julian@codesourcery.com>
40 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
43 2006-05-05 Thiemo Seufer <ths@mips.com>
44 David Ung <davidu@mips.com>
46 * mips-opc.c: Add macro for cache instruction.
48 2006-05-04 Thiemo Seufer <ths@mips.com>
49 Nigel Stephens <nigel@mips.com>
50 David Ung <davidu@mips.com>
52 * mips-dis.c (mips_arch_choices): Add smartmips instruction
53 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
54 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
56 * mips-opc.c: fix random typos in comments.
57 (INSN_SMARTMIPS): New defines.
58 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
59 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
60 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
61 FP_S and FP_D flags to denote single and double register
62 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
63 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
64 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
65 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
67 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
69 2006-05-03 Thiemo Seufer <ths@mips.com>
71 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
73 2006-05-02 Thiemo Seufer <ths@mips.com>
74 Nigel Stephens <nigel@mips.com>
75 David Ung <davidu@mips.com>
77 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
78 (print_mips16_insn_arg): Force mips16 to odd addresses.
80 2006-04-30 Thiemo Seufer <ths@mips.com>
81 David Ung <davidu@mips.com>
83 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
85 * mips-dis.c (print_insn_args): Adds udi argument handling.
87 2006-04-28 James E Wilson <wilson@specifix.com>
89 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
92 2006-04-28 Thiemo Seufer <ths@mips.com>
93 David Ung <davidu@mips.com>
94 Nigel Stephens <nigel@mips.com>
96 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
99 2006-04-28 Thiemo Seufer <ths@mips.com>
100 Nigel Stephens <nigel@mips.com>
101 David Ung <davidu@mips.com>
103 * mips-dis.c (print_insn_args): Add mips_opcode argument.
104 (print_insn_mips): Adjust print_insn_args call.
106 2006-04-28 Thiemo Seufer <ths@mips.com>
107 Nigel Stephens <nigel@mips.com>
109 * mips-dis.c (print_insn_args): Print $fcc only for FP
110 instructions, use $cc elsewise.
112 2006-04-28 Thiemo Seufer <ths@mips.com>
113 Nigel Stephens <nigel@mips.com>
115 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
116 Map MIPS16 registers to O32 names.
117 (print_mips16_insn_arg): Use mips16_reg_names.
119 2006-04-26 Julian Brown <julian@codesourcery.com>
121 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
124 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
125 Julian Brown <julian@codesourcery.com>
127 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
128 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
129 Add unified load/store instruction names.
130 (neon_opcode_table): New.
131 (arm_opcodes): Expand meaning of %<bitfield>['`?].
132 (arm_decode_bitfield): New.
133 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
134 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
135 (print_insn_neon): New.
136 (print_insn_arm): Adjust print_insn_coprocessor call. Call
137 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
138 (print_insn_thumb32): Likewise.
140 2006-04-19 Alan Modra <amodra@bigpond.net.au>
142 * Makefile.am: Run "make dep-am".
143 * Makefile.in: Regenerate.
145 2006-04-19 Alan Modra <amodra@bigpond.net.au>
147 * avr-dis.c (avr_operand): Warning fix.
149 * configure: Regenerate.
151 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
153 * po/POTFILES.in: Regenerated.
155 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
158 * avr-dis.c (avr_operand): Arrange for a comment to appear before
159 the symolic form of an address, so that the output of objdump -d
162 2006-04-10 DJ Delorie <dj@redhat.com>
164 * m32c-asm.c: Regenerate.
166 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
168 * Makefile.am: Add install-html target.
169 * Makefile.in: Regenerate.
171 2006-04-06 Nick Clifton <nickc@redhat.com>
173 * po/vi/po: Updated Vietnamese translation.
175 2006-03-31 Paul Koning <ni1d@arrl.net>
177 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
179 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
181 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
182 logic to identify halfword shifts.
184 2006-03-16 Paul Brook <paul@codesourcery.com>
186 * arm-dis.c (arm_opcodes): Rename swi to svc.
187 (thumb_opcodes): Ditto.
189 2006-03-13 DJ Delorie <dj@redhat.com>
191 * m32c-asm.c: Regenerate.
192 * m32c-desc.c: Likewise.
193 * m32c-desc.h: Likewise.
194 * m32c-dis.c: Likewise.
195 * m32c-ibld.c: Likewise.
196 * m32c-opc.c: Likewise.
197 * m32c-opc.h: Likewise.
199 2006-03-10 DJ Delorie <dj@redhat.com>
201 * m32c-desc.c: Regenerate with mul.l, mulu.l.
202 * m32c-opc.c: Likewise.
203 * m32c-opc.h: Likewise.
206 2006-03-09 Nick Clifton <nickc@redhat.com>
208 * po/sv.po: Updated Swedish translation.
210 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
213 * i386-dis.c (REP_Fixup): New function.
214 (AL): Remove duplicate.
219 (indirDXr): Likewise.
222 (dis386): Updated entries of ins, outs, movs, lods and stos.
224 2006-03-05 Nick Clifton <nickc@redhat.com>
226 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
227 signed 32-bit value into an unsigned 32-bit field when the host is
229 * fr30-ibld.c: Regenerate.
230 * frv-ibld.c: Regenerate.
231 * ip2k-ibld.c: Regenerate.
232 * iq2000-asm.c: Regenerate.
233 * iq2000-ibld.c: Regenerate.
234 * m32c-ibld.c: Regenerate.
235 * m32r-ibld.c: Regenerate.
236 * openrisc-ibld.c: Regenerate.
237 * xc16x-ibld.c: Regenerate.
238 * xstormy16-ibld.c: Regenerate.
240 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
242 * xc16x-asm.c: Regenerate.
243 * xc16x-dis.c: Regenerate.
245 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
247 * po/Make-in: Add html target.
249 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
251 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
252 Intel Merom New Instructions.
253 (THREE_BYTE_0): Likewise.
254 (THREE_BYTE_1): Likewise.
255 (three_byte_table): Likewise.
256 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
257 THREE_BYTE_1 for entry 0x3a.
258 (twobyte_has_modrm): Updated.
259 (twobyte_uses_SSE_prefix): Likewise.
260 (print_insn): Handle 3-byte opcodes used by Intel Merom New
263 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
265 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
266 (v9_hpriv_reg_names): New table.
267 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
268 New cases '$' and '%' for read/write hyperprivileged register.
269 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
270 window handling and rdhpr/wrhpr instructions.
272 2006-02-24 DJ Delorie <dj@redhat.com>
274 * m32c-desc.c: Regenerate with linker relaxation attributes.
275 * m32c-desc.h: Likewise.
276 * m32c-dis.c: Likewise.
277 * m32c-opc.c: Likewise.
279 2006-02-24 Paul Brook <paul@codesourcery.com>
281 * arm-dis.c (arm_opcodes): Add V7 instructions.
282 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
283 (print_arm_address): New function.
284 (print_insn_arm): Use it. Add 'P' and 'U' cases.
285 (psr_name): New function.
286 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
288 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
290 * ia64-opc-i.c (bXc): New.
292 (OpX2TaTbYaXcC): Likewise.
295 (ia64_opcodes_i): Add instructions for tf.
297 * ia64-opc.h (IMMU5b): New.
299 * ia64-asmtab.c: Regenerated.
301 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
303 * ia64-gen.c: Update copyright years.
304 * ia64-opc-b.c: Likewise.
306 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
308 * ia64-gen.c (lookup_regindex): Handle ".vm".
309 (print_dependency_table): Handle '\"'.
311 * ia64-ic.tbl: Updated from SDM 2.2.
312 * ia64-raw.tbl: Likewise.
313 * ia64-waw.tbl: Likewise.
314 * ia64-asmtab.c: Regenerated.
316 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
318 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
319 Anil Paranjape <anilp1@kpitcummins.com>
320 Shilin Shakti <shilins@kpitcummins.com>
322 * xc16x-desc.h: New file
323 * xc16x-desc.c: New file
324 * xc16x-opc.h: New file
325 * xc16x-opc.c: New file
326 * xc16x-ibld.c: New file
327 * xc16x-asm.c: New file
328 * xc16x-dis.c: New file
329 * Makefile.am: Entries for xc16x
330 * Makefile.in: Regenerate
331 * cofigure.in: Add xc16x target information.
332 * configure: Regenerate.
333 * disassemble.c: Add xc16x target information.
335 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
337 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
340 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
342 * i386-dis.c ('Z'): Add a new macro.
343 (dis386_twobyte): Use "movZ" for control register moves.
345 2006-02-10 Nick Clifton <nickc@redhat.com>
347 * iq2000-asm.c: Regenerate.
349 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
351 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
353 2006-01-26 David Ung <davidu@mips.com>
355 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
356 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
357 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
358 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
359 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
361 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
363 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
364 ld_d_r, pref_xd_cb): Use signed char to hold data to be
366 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
367 buffer overflows when disassembling instructions like
369 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
370 operand, if the offset is negative.
372 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
374 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
375 unsigned char to hold data to be disassembled.
377 2006-01-17 Andreas Schwab <schwab@suse.de>
380 * disassemble.c (disassemble_init_for_target): Set
381 disassembler_needs_relocs for bfd_arch_arm.
383 2006-01-16 Paul Brook <paul@codesourcery.com>
385 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
386 f?add?, and f?sub? instructions.
388 2006-01-16 Nick Clifton <nickc@redhat.com>
390 * po/zh_CN.po: New Chinese (simplified) translation.
391 * configure.in (ALL_LINGUAS): Add "zh_CH".
392 * configure: Regenerate.
394 2006-01-05 Paul Brook <paul@codesourcery.com>
396 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
398 2006-01-06 DJ Delorie <dj@redhat.com>
400 * m32c-desc.c: Regenerate.
401 * m32c-opc.c: Regenerate.
402 * m32c-opc.h: Regenerate.
404 2006-01-03 DJ Delorie <dj@redhat.com>
406 * cgen-ibld.in (extract_normal): Avoid memory range errors.
407 * m32c-ibld.c: Regenerated.
409 For older changes see ChangeLog-2005
415 version-control: never