opcodes/ChangeLog

   1 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
   2
   3         * arc-dis.c (arc_insn_length): Add comment on instruction length.
   4         Use same method for determining instruction length on ARC700 and
   5         NPS-400.
   6         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
   7         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
   8         with the NPS400 subclass.
   9         * arc-opc.c: Likewise.
  10
  11 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  12
  13         * sparc-opc.c (rdasr): New macro.
  14         (wrasr): Likewise.
  15         (rdpr): Likewise.
  16         (wrpr): Likewise.
  17         (rdhpr): Likewise.
  18         (wrhpr): Likewise.
  19         (sparc_opcodes): Use the macros above to fix and expand the
  20         definition of read/write instructions from/to
  21         asr/privileged/hyperprivileged instructions.
  22         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
  23         %hva_mask_nz.  Prefer softint_set and softint_clear over
  24         set_softint and clear_softint.
  25         (print_insn_sparc): Support %ver in Rd.
  26
  27 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  28
  29         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
  30         architecture according to the hardware capabilities they require.
  31
  32 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  33
  34         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
  35         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
  36         bfd_mach_sparc_v9{c,d,e,v,m}.
  37         * sparc-opc.c (MASK_V9C): Define.
  38         (MASK_V9D): Likewise.
  39         (MASK_V9E): Likewise.
  40         (MASK_V9V): Likewise.
  41         (MASK_V9M): Likewise.
  42         (v6): Add MASK_V9{C,D,E,V,M}.
  43         (v6notlet): Likewise.
  44         (v7): Likewise.
  45         (v8): Likewise.
  46         (v9): Likewise.
  47         (v9andleon): Likewise.
  48         (v9a): Likewise.
  49         (v9b): Likewise.
  50         (v9c): Define.
  51         (v9d): Likewise.
  52         (v9e): Likewise.
  53         (v9v): Likewise.
  54         (v9m): Likewise.
  55         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
  56
  57 2016-06-15  Nick Clifton  <nickc@redhat.com>
  58
  59         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
  60         constants to match expected behaviour.
  61         (nds32_parse_opcode): Likewise.  Also for whitespace.
  62
  63 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
  64
  65         * arc-opc.c (extract_rhv1): Extract value from insn.
  66
  67 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
  68
  69         * arc-nps400-tbl.h: Add ldbit instruction.
  70         * arc-opc.c: Add flag classes required for ldbit.
  71
  72 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
  73
  74         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
  75         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
  76         support the above instructions.
  77
  78 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
  79
  80         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
  81         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
  82         csma, cbba, zncv, and hofs.
  83         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
  84         support the above instructions.
  85
  86 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
  87
  88         * arc-nps400-tbl.h: Add andab and orab instructions.
  89
  90 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
  91
  92         * arc-nps400-tbl.h: Add addl-like instructions.
  93
  94 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
  95
  96         * arc-nps400-tbl.h: Add mxb and imxb instructions.
  97
  98 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
  99
 100         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 101         instructions.
 102
 103 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 104
 105         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 106         variable.
 107         (init_disasm): Handle new command line option "insnlength".
 108         (print_s390_disassembler_options): Mention new option in help
 109         output.
 110         (print_insn_s390): Use the encoded insn length when dumping
 111         unknown instructions.
 112
 113 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 114
 115         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 116          to the address and set as symbol address for LDS/ STS immediate operands.
 117
 118 2016-06-07  Alan Modra  <amodra@gmail.com>
 119
 120         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 121         cpu for "vle" to e500.
 122         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 123         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 124         (PPCNONE): Delete, substitute throughout.
 125         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 126         except for major opcode 4 and 31.
 127         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 128
 129 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 130
 131         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 132         ARM_EXT_RAS in relevant entries.
 133
 134 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 135
 136         PR binutils/20196
 137         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 138         opcodes for E6500.
 139
 140 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 141
 142         PR binutis/18386
 143         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 144         (indir_v_mode): New.
 145         Add comments for '&'.
 146         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 147         (putop): Handle '&'.
 148         (intel_operand_size): Handle indir_v_mode.
 149         (OP_E_register): Likewise.
 150         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 151         64-bit indirect call/jmp for AMD64.
 152         * i386-tbl.h: Regenerated
 153
 154 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 155
 156         * arc-dis.c (struct arc_operand_iterator): New structure.
 157         (find_format_from_table): All the old content from find_format,
 158         with some minor adjustments, and parameter renaming.
 159         (find_format_long_instructions): New function.
 160         (find_format): Rewritten.
 161         (arc_insn_length): Add LSB parameter.
 162         (extract_operand_value): New function.
 163         (operand_iterator_next): New function.
 164         (print_insn_arc): Use new functions to find opcode, and iterator
 165         over operands.
 166         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 167         (extract_nps_3bit_dst_short): New function.
 168         (insert_nps_3bit_src2_short): New function.
 169         (extract_nps_3bit_src2_short): New function.
 170         (insert_nps_bitop1_size): New function.
 171         (extract_nps_bitop1_size): New function.
 172         (insert_nps_bitop2_size): New function.
 173         (extract_nps_bitop2_size): New function.
 174         (insert_nps_bitop_mod4_msb): New function.
 175         (extract_nps_bitop_mod4_msb): New function.
 176         (insert_nps_bitop_mod4_lsb): New function.
 177         (extract_nps_bitop_mod4_lsb): New function.
 178         (insert_nps_bitop_dst_pos3_pos4): New function.
 179         (extract_nps_bitop_dst_pos3_pos4): New function.
 180         (insert_nps_bitop_ins_ext): New function.
 181         (extract_nps_bitop_ins_ext): New function.
 182         (arc_operands): Add new operands.
 183         (arc_long_opcodes): New global array.
 184         (arc_num_long_opcodes): New global.
 185         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 186
 187 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 188
 189         * nds32-asm.h: Add extern "C".
 190         * sh-opc.h: Likewise.
 191
 192 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 193
 194         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 195         0,b,limm to the rflt instruction.
 196
 197 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 198
 199         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 200         constant.
 201
 202 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         PR gas/20145
 205         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 206         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 207         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 208         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 209         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 210         * i386-init.h: Regenerated.
 211
 212 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         PR gas/20145
 215         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 216         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 217         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 218         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 219         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 220         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 221         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 222         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 223         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 224         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 225         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 226         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 227         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 228         CpuRegMask for AVX512.
 229         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 230         and CpuRegMask.
 231         (set_bitfield_from_cpu_flag_init): New function.
 232         (set_bitfield): Remove const on f.  Call
 233         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 234         * i386-opc.h (CpuRegMMX): New.
 235         (CpuRegXMM): Likewise.
 236         (CpuRegYMM): Likewise.
 237         (CpuRegZMM): Likewise.
 238         (CpuRegMask): Likewise.
 239         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 240         and cpuregmask.
 241         * i386-init.h: Regenerated.
 242         * i386-tbl.h: Likewise.
 243
 244 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         PR gas/20154
 247         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 248         (opcode_modifiers): Add AMD64 and Intel64.
 249         (main): Properly verify CpuMax.
 250         * i386-opc.h (CpuAMD64): Removed.
 251         (CpuIntel64): Likewise.
 252         (CpuMax): Set to CpuNo64.
 253         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 254         (AMD64): New.
 255         (Intel64): Likewise.
 256         (i386_opcode_modifier): Add amd64 and intel64.
 257         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 258         on call and jmp.
 259         * i386-init.h: Regenerated.
 260         * i386-tbl.h: Likewise.
 261
 262 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 263
 264         PR gas/20154
 265         * i386-gen.c (main): Fail if CpuMax is incorrect.
 266         * i386-opc.h (CpuMax): Set to CpuIntel64.
 267         * i386-tbl.h: Regenerated.
 268
 269 2016-05-27  Nick Clifton  <nickc@redhat.com>
 270
 271         PR target/20150
 272         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 273         (msp430dis_opcode_unsigned): New function.
 274         (msp430dis_opcode_signed): New function.
 275         (msp430_singleoperand): Use the new opcode reading functions.
 276         Only disassenmble bytes if they were successfully read.
 277         (msp430_doubleoperand): Likewise.
 278         (msp430_branchinstr): Likewise.
 279         (msp430x_callx_instr): Likewise.
 280         (print_insn_msp430): Check that it is safe to read bytes before
 281         attempting disassembly.  Use the new opcode reading functions.
 282
 283 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 284
 285         * ppc-opc.c (CY): New define.  Document it.
 286         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 287
 288 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 289
 290         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 291         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 292         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 293         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 294         CPU_ANY_AVX_FLAGS.
 295         * i386-init.h: Regenerated.
 296
 297 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         PR gas/20141
 300         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 301         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 302         * i386-init.h: Regenerated.
 303
 304 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 307         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 308         * i386-init.h: Regenerated.
 309
 310 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 311
 312         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 313         information.
 314         (print_insn_arc): Set insn_type information.
 315         * arc-opc.c (C_CC): Add F_CLASS_COND.
 316         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 317         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 318         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 319         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 320         (brne, brne_s, jeq_s, jne_s): Likewise.
 321
 322 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 323
 324         * arc-tbl.h (neg): New instruction variant.
 325
 326 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 327
 328         * arc-dis.c (find_format, find_format, get_auxreg)
 329         (print_insn_arc): Changed.
 330         * arc-ext.h (INSERT_XOP): Likewise.
 331
 332 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 333
 334         * tic54x-dis.c (sprint_mmr): Adjust.
 335         * tic54x-opc.c: Likewise.
 336
 337 2016-05-19  Alan Modra  <amodra@gmail.com>
 338
 339         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 340
 341 2016-05-19  Alan Modra  <amodra@gmail.com>
 342
 343         * ppc-opc.c: Formatting.
 344         (NSISIGNOPT): Define.
 345         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 346
 347 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 348
 349         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 350         replacing references to `micromips_ase' throughout.
 351         (_print_insn_mips): Don't use file-level microMIPS annotation to
 352         determine the disassembly mode with the symbol table.
 353
 354 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 355
 356         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 357
 358 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 359
 360         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 361         mips64r6.
 362         * mips-opc.c (D34): New macro.
 363         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 364
 365 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 366
 367         * i386-dis.c (prefix_table): Add RDPID instruction.
 368         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 369         (cpu_flags): Add RDPID bitfield.
 370         * i386-opc.h (enum): Add RDPID element.
 371         (i386_cpu_flags): Add RDPID field.
 372         * i386-opc.tbl: Add RDPID instruction.
 373         * i386-init.h: Regenerate.
 374         * i386-tbl.h: Regenerate.
 375
 376 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 377
 378         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 379         branch type of a symbol.
 380         (print_insn): Likewise.
 381
 382 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 383
 384         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 385         Mainline Security Extensions instructions.
 386         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 387         Extensions instructions.
 388         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 389         instructions.
 390         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 391         special registers.
 392
 393 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 394
 395         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 396
 397 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 398
 399         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 400         (arcExtMap_genOpcode): Likewise.
 401         * arc-opc.c (arg_32bit_rc): Define new variable.
 402         (arg_32bit_u6): Likewise.
 403         (arg_32bit_limm): Likewise.
 404
 405 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 406
 407         * aarch64-gen.c (VERIFIER): Define.
 408         * aarch64-opc.c (VERIFIER): Define.
 409         (verify_ldpsw): Use static linkage.
 410         * aarch64-opc.h (verify_ldpsw): Remove.
 411         * aarch64-tbl.h: Use VERIFIER for verifiers.
 412
 413 2016-04-28  Nick Clifton  <nickc@redhat.com>
 414
 415         PR target/19722
 416         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 417         * aarch64-opc.c (verify_ldpsw): New function.
 418         * aarch64-opc.h (verify_ldpsw): New prototype.
 419         * aarch64-tbl.h: Add initialiser for verifier field.
 420         (LDPSW): Set verifier to verify_ldpsw.
 421
 422 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         PR binutils/19983
 425         PR binutils/19984
 426         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 427         smaller than address size.
 428
 429 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 430
 431         * alpha-dis.c: Regenerate.
 432         * crx-dis.c: Likewise.
 433         * disassemble.c: Likewise.
 434         * epiphany-opc.c: Likewise.
 435         * fr30-opc.c: Likewise.
 436         * frv-opc.c: Likewise.
 437         * ip2k-opc.c: Likewise.
 438         * iq2000-opc.c: Likewise.
 439         * lm32-opc.c: Likewise.
 440         * lm32-opinst.c: Likewise.
 441         * m32c-opc.c: Likewise.
 442         * m32r-opc.c: Likewise.
 443         * m32r-opinst.c: Likewise.
 444         * mep-opc.c: Likewise.
 445         * mt-opc.c: Likewise.
 446         * or1k-opc.c: Likewise.
 447         * or1k-opinst.c: Likewise.
 448         * tic80-opc.c: Likewise.
 449         * xc16x-opc.c: Likewise.
 450         * xstormy16-opc.c: Likewise.
 451
 452 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 453
 454         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 455         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 456         calcsd, and calcxd instructions.
 457         * arc-opc.c (insert_nps_bitop_size): Delete.
 458         (extract_nps_bitop_size): Delete.
 459         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 460         (extract_nps_qcmp_m3): Define.
 461         (extract_nps_qcmp_m2): Define.
 462         (extract_nps_qcmp_m1): Define.
 463         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 464         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 465         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 466         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 467         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 468         NPS_QCMP_M3.
 469
 470 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 471
 472         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 473
 474 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * Makefile.in: Regenerated with automake 1.11.6.
 477         * aclocal.m4: Likewise.
 478
 479 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 480
 481         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 482         instructions.
 483         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 484         (extract_nps_cmem_uimm16): New function.
 485         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 486
 487 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 488
 489         * arc-dis.c (arc_insn_length): New function.
 490         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 491         (find_format): Change insnLen parameter to unsigned.
 492
 493 2016-04-13  Nick Clifton  <nickc@redhat.com>
 494
 495         PR target/19937
 496         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 497         the LD.B and LD.BU instructions.
 498
 499 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 500
 501         * arc-dis.c (find_format): Check for extension flags.
 502         (print_flags): New function.
 503         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 504         .extAuxRegister.
 505         * arc-ext.c (arcExtMap_coreRegName): Use
 506         LAST_EXTENSION_CORE_REGISTER.
 507         (arcExtMap_coreReadWrite): Likewise.
 508         (dump_ARC_extmap): Update printing.
 509         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 510         (arc_aux_regs): Add cpu field.
 511         * arc-regs.h: Add cpu field, lower case name aux registers.
 512
 513 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 514
 515         * arc-tbl.h: Add rtsc, sleep with no arguments.
 516
 517 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 518
 519         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 520         Initialize.
 521         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 522         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 523         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 524         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 525         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 526         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 527         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 528         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 529         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 530         (arc_opcode arc_opcodes): Null terminate the array.
 531         (arc_num_opcodes): Remove.
 532         * arc-ext.h (INSERT_XOP): Define.
 533         (extInstruction_t): Likewise.
 534         (arcExtMap_instName): Delete.
 535         (arcExtMap_insn): New function.
 536         (arcExtMap_genOpcode): Likewise.
 537         * arc-ext.c (ExtInstruction): Remove.
 538         (create_map): Zero initialize instruction fields.
 539         (arcExtMap_instName): Remove.
 540         (arcExtMap_insn): New function.
 541         (dump_ARC_extmap): More info while debuging.
 542         (arcExtMap_genOpcode): New function.
 543         * arc-dis.c (find_format): New function.
 544         (print_insn_arc): Use find_format.
 545         (arc_get_disassembler): Enable dump_ARC_extmap only when
 546         debugging.
 547
 548 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 549
 550         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 551         instruction bits out.
 552
 553 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 554
 555         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 556         * arc-opc.c (arc_flag_operands): Add new flags.
 557         (arc_flag_classes): Add new classes.
 558
 559 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 560
 561         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 562
 563 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 564
 565         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 566         encode1, rflt, crc16, and crc32 instructions.
 567         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 568         (arc_flag_classes): Add C_NPS_R.
 569         (insert_nps_bitop_size_2b): New function.
 570         (extract_nps_bitop_size_2b): Likewise.
 571         (insert_nps_bitop_uimm8): Likewise.
 572         (extract_nps_bitop_uimm8): Likewise.
 573         (arc_operands): Add new operand entries.
 574
 575 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 576
 577         * arc-regs.h: Add a new subclass field.  Add double assist
 578         accumulator register values.
 579         * arc-tbl.h: Use DPA subclass to mark the double assist
 580         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 581         * arc-opc.c (RSP): Define instead of SP.
 582         (arc_aux_regs): Add the subclass field.
 583
 584 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 585
 586         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 587
 588 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 589
 590         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 591         NPS_R_SRC1.
 592
 593 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 594
 595         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 596         issues.  No functional changes.
 597
 598 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 599
 600         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 601         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 602         (RTT): Remove duplicate.
 603         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 604         (PCT_CONFIG*): Remove.
 605         (D1L, D1H, D2H, D2L): Define.
 606
 607 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 608
 609         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 610
 611 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 612
 613         * arc-tbl.h (invld07): Remove.
 614         * arc-ext-tbl.h: New file.
 615         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 616         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 617
 618 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 619
 620         Fix -Wstack-usage warnings.
 621         * aarch64-dis.c (print_operands): Substitute size.
 622         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 623
 624 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 625
 626         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 627         to get a proper diagnostic when an invalid ASR register is used.
 628
 629 2016-03-22  Nick Clifton  <nickc@redhat.com>
 630
 631         * configure: Regenerate.
 632
 633 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 634
 635         * arc-nps400-tbl.h: New file.
 636         * arc-opc.c: Add top level comment.
 637         (insert_nps_3bit_dst): New function.
 638         (extract_nps_3bit_dst): New function.
 639         (insert_nps_3bit_src2): New function.
 640         (extract_nps_3bit_src2): New function.
 641         (insert_nps_bitop_size): New function.
 642         (extract_nps_bitop_size): New function.
 643         (arc_flag_operands): Add nps400 entries.
 644         (arc_flag_classes): Add nps400 entries.
 645         (arc_operands): Add nps400 entries.
 646         (arc_opcodes): Add nps400 include.
 647
 648 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 649
 650         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 651         the new class enum values.
 652
 653 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 654
 655         * arc-dis.c (print_insn_arc): Handle nps400.
 656
 657 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 658
 659         * arc-opc.c (BASE): Delete.
 660
 661 2016-03-18  Nick Clifton  <nickc@redhat.com>
 662
 663         PR target/19721
 664         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 665         of MOV insn that aliases an ORR insn.
 666
 667 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 668
 669         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 670
 671 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 672
 673         * mcore-opc.h: Add const qualifiers.
 674         * microblaze-opc.h (struct op_code_struct): Likewise.
 675         * sh-opc.h: Likewise.
 676         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 677         (tic4x_print_op): Likewise.
 678
 679 2016-03-02  Alan Modra  <amodra@gmail.com>
 680
 681         * or1k-desc.h: Regenerate.
 682         * fr30-ibld.c: Regenerate.
 683         * rl78-decode.c: Regenerate.
 684
 685 2016-03-01  Nick Clifton  <nickc@redhat.com>
 686
 687         PR target/19747
 688         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 689
 690 2016-02-24  Renlin Li  <renlin.li@arm.com>
 691
 692         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 693         (print_insn_coprocessor): Support fp16 instructions.
 694
 695 2016-02-24  Renlin Li  <renlin.li@arm.com>
 696
 697         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 698         vminnm, vrint(mpna).
 699
 700 2016-02-24  Renlin Li  <renlin.li@arm.com>
 701
 702         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 703         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 704
 705 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 706
 707         * i386-dis.c (print_insn): Parenthesize expression to prevent
 708         truncated addresses.
 709         (OP_J): Likewise.
 710
 711 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 712             Janek van Oirschot  <jvanoirs@synopsys.com>
 713
 714         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 715         variable.
 716
 717 2016-02-04  Nick Clifton  <nickc@redhat.com>
 718
 719         PR target/19561
 720         * msp430-dis.c (print_insn_msp430): Add a special case for
 721         decoding an RRC instruction with the ZC bit set in the extension
 722         word.
 723
 724 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 725
 726         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 727         * epiphany-ibld.c: Regenerate.
 728         * fr30-ibld.c: Regenerate.
 729         * frv-ibld.c: Regenerate.
 730         * ip2k-ibld.c: Regenerate.
 731         * iq2000-ibld.c: Regenerate.
 732         * lm32-ibld.c: Regenerate.
 733         * m32c-ibld.c: Regenerate.
 734         * m32r-ibld.c: Regenerate.
 735         * mep-ibld.c: Regenerate.
 736         * mt-ibld.c: Regenerate.
 737         * or1k-ibld.c: Regenerate.
 738         * xc16x-ibld.c: Regenerate.
 739         * xstormy16-ibld.c: Regenerate.
 740
 741 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 742
 743         * epiphany-dis.c: Regenerated from latest cpu files.
 744
 745 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 746
 747         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 748         test bit.
 749
 750 2016-01-25  Renlin Li  <renlin.li@arm.com>
 751
 752         * arm-dis.c (mapping_symbol_for_insn): New function.
 753         (find_ifthen_state): Call mapping_symbol_for_insn().
 754
 755 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 756
 757         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 758         of MSR UAO immediate operand.
 759
 760 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 761
 762         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 763         instruction support.
 764
 765 2016-01-17  Alan Modra  <amodra@gmail.com>
 766
 767         * configure: Regenerate.
 768
 769 2016-01-14  Nick Clifton  <nickc@redhat.com>
 770
 771         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 772         instructions that can support stack pointer operations.
 773         * rl78-decode.c: Regenerate.
 774         * rl78-dis.c: Fix display of stack pointer in MOVW based
 775         instructions.
 776
 777 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 778
 779         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 780         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 781         erxtatus_el1 and erxaddr_el1.
 782
 783 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 784
 785         * arm-dis.c (arm_opcodes): Add "esb".
 786         (thumb_opcodes): Likewise.
 787
 788 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 789
 790         * ppc-opc.c <xscmpnedp>: Delete.
 791         <xvcmpnedp>: Likewise.
 792         <xvcmpnedp.>: Likewise.
 793         <xvcmpnesp>: Likewise.
 794         <xvcmpnesp.>: Likewise.
 795
 796 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 797
 798         PR gas/13050
 799         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 800         addition to ISA_A.
 801
 802 2016-01-01  Alan Modra  <amodra@gmail.com>
 803
 804         Update year range in copyright notice of all files.
 805
 806 For older changes see ChangeLog-2015
 807 \f
 808 Copyright (C) 2016 Free Software Foundation, Inc.
 809
 810 Copying and distribution of this file, with or without modification,
 811 are permitted in any medium without royalty provided the copyright
 812 notice and this notice are preserved.
 813
 814 Local Variables:
 815 mode: change-log
 816 left-margin: 8
 817 fill-column: 74
 818 version-control: never
 819 End: