opcodes/ChangeLog

   1 2020-06-17  Lili Cui  <lili.cui@intel.com>
   2
   3         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
   4
   5 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         PR gas/26115
   8         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
   9         * i386-opc.tbl: Likewise.
  10         * i386-tbl.h: Regenerated.
  11
  12 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  13
  14         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  15
  16 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  17
  18         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  19         (SR_CORE): Likewise.
  20         (SR_FEAT): Likewise.
  21         (SR_RNG): Likewise.
  22         (SR_V8_1): Likewise.
  23         (SR_V8_2): Likewise.
  24         (SR_V8_3): Likewise.
  25         (SR_V8_4): Likewise.
  26         (SR_PAN): Likewise.
  27         (SR_RAS): Likewise.
  28         (SR_SSBS): Likewise.
  29         (SR_SVE): Likewise.
  30         (SR_ID_PFR2): Likewise.
  31         (SR_PROFILE): Likewise.
  32         (SR_MEMTAG): Likewise.
  33         (SR_SCXTNUM): Likewise.
  34         (aarch64_sys_regs): Refactor to store feature information in the table.
  35         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  36         that now describe their own features.
  37         (aarch64_pstatefield_supported_p): Likewise.
  38
  39 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         * i386-dis.c (prefix_table): Fix a typo in comments.
  42
  43 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-dis.c (rex_ignored): Delete.
  46         (ckprefix): Drop rex_ignored initialization.
  47         (get_valid_dis386): Drop setting of rex_ignored.
  48         (print_insn): Drop checking of rex_ignored. Don't record data
  49         size prefix as used with VEX-and-alike encodings.
  50
  51 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  54         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  55         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  56         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  57         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  58         VEX_0F12, and VEX_0F16.
  59         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  60         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  61         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  62         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  63         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  64         MOD_VEX_0F16_PREFIX_2 entries.
  65
  66 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  69         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  70         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  71         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  72         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  73         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  74         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
  75         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
  76         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
  77         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
  78         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
  79         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
  80         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
  81         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
  82         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
  83         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
  84         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
  85         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
  86         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
  87         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
  88         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
  89         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
  90         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
  91         EVEX_W_0FC6_P_2): Delete.
  92         (print_insn): Add EVEX.W vs embedded prefix consistency check
  93         to prefix validation.
  94         * i386-dis-evex.h (evex_table): Don't further descend for
  95         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
  96         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
  97         and 0F2B.
  98         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
  99         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 100         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 101         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 102         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 103         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 104         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 105         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 106         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 107         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 108         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 109         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 110         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 111         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 112         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 113         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 114         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 115         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 116         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 117         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 118         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 119         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 120         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 121         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 122         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 123         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 124         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 125
 126 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 127
 128         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 129         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 130         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 131         vmovmskpX.
 132         (print_insn): Drop pointless check against bad_opcode. Split
 133         prefix validation into legacy and VEX-and-alike parts.
 134         (putop): Re-work 'X' macro handling.
 135
 136 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-dis.c (MOD_0F51): Rename to ...
 139         (MOD_0F50): ... this.
 140
 141 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 142
 143         * arm-dis.c (arm_opcodes): Add dfb.
 144         (thumb32_opcodes): Add dfb.
 145
 146 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 149
 150 2020-06-06  Alan Modra  <amodra@gmail.com>
 151
 152         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 153
 154 2020-06-05  Alan Modra  <amodra@gmail.com>
 155
 156         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 157         size is large enough.
 158
 159 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 160
 161         * disassemble.c (disassemble_init_for_target): Set endian_code for
 162         bpf targets.
 163         * bpf-desc.c: Regenerate.
 164         * bpf-opc.c: Likewise.
 165         * bpf-dis.c: Likewise.
 166
 167 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 168
 169         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 170         (cgen_put_insn_value): Likewise.
 171         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 172         * cgen-dis.in (print_insn): Likewise.
 173         * cgen-ibld.in (insert_1): Likewise.
 174         (insert_1): Likewise.
 175         (insert_insn_normal): Likewise.
 176         (extract_1): Likewise.
 177         * bpf-dis.c: Regenerate.
 178         * bpf-ibld.c: Likewise.
 179         * bpf-ibld.c: Likewise.
 180         * cgen-dis.in: Likewise.
 181         * cgen-ibld.in: Likewise.
 182         * cgen-opc.c: Likewise.
 183         * epiphany-dis.c: Likewise.
 184         * epiphany-ibld.c: Likewise.
 185         * fr30-dis.c: Likewise.
 186         * fr30-ibld.c: Likewise.
 187         * frv-dis.c: Likewise.
 188         * frv-ibld.c: Likewise.
 189         * ip2k-dis.c: Likewise.
 190         * ip2k-ibld.c: Likewise.
 191         * iq2000-dis.c: Likewise.
 192         * iq2000-ibld.c: Likewise.
 193         * lm32-dis.c: Likewise.
 194         * lm32-ibld.c: Likewise.
 195         * m32c-dis.c: Likewise.
 196         * m32c-ibld.c: Likewise.
 197         * m32r-dis.c: Likewise.
 198         * m32r-ibld.c: Likewise.
 199         * mep-dis.c: Likewise.
 200         * mep-ibld.c: Likewise.
 201         * mt-dis.c: Likewise.
 202         * mt-ibld.c: Likewise.
 203         * or1k-dis.c: Likewise.
 204         * or1k-ibld.c: Likewise.
 205         * xc16x-dis.c: Likewise.
 206         * xc16x-ibld.c: Likewise.
 207         * xstormy16-dis.c: Likewise.
 208         * xstormy16-ibld.c: Likewise.
 209
 210 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 211
 212         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 213         (print_insn_): Handle instruction endian.
 214         * bpf-dis.c: Regenerate.
 215         * bpf-desc.c: Regenerate.
 216         * epiphany-dis.c: Likewise.
 217         * epiphany-desc.c: Likewise.
 218         * fr30-dis.c: Likewise.
 219         * fr30-desc.c: Likewise.
 220         * frv-dis.c: Likewise.
 221         * frv-desc.c: Likewise.
 222         * ip2k-dis.c: Likewise.
 223         * ip2k-desc.c: Likewise.
 224         * iq2000-dis.c: Likewise.
 225         * iq2000-desc.c: Likewise.
 226         * lm32-dis.c: Likewise.
 227         * lm32-desc.c: Likewise.
 228         * m32c-dis.c: Likewise.
 229         * m32c-desc.c: Likewise.
 230         * m32r-dis.c: Likewise.
 231         * m32r-desc.c: Likewise.
 232         * mep-dis.c: Likewise.
 233         * mep-desc.c: Likewise.
 234         * mt-dis.c: Likewise.
 235         * mt-desc.c: Likewise.
 236         * or1k-dis.c: Likewise.
 237         * or1k-desc.c: Likewise.
 238         * xc16x-dis.c: Likewise.
 239         * xc16x-desc.c: Likewise.
 240         * xstormy16-dis.c: Likewise.
 241         * xstormy16-desc.c: Likewise.
 242
 243 2020-06-03  Nick Clifton  <nickc@redhat.com>
 244
 245         * po/sr.po: Updated Serbian translation.
 246
 247 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 248
 249         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 250         (riscv_get_priv_spec_class): Likewise.
 251
 252 2020-06-01  Alan Modra  <amodra@gmail.com>
 253
 254         * bpf-desc.c: Regenerate.
 255
 256 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 257             David Faust <david.faust@oracle.com>
 258
 259         * bpf-desc.c: Regenerate.
 260         * bpf-opc.h: Likewise.
 261         * bpf-opc.c: Likewise.
 262         * bpf-dis.c: Likewise.
 263
 264 2020-05-28  Alan Modra  <amodra@gmail.com>
 265
 266         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 267         values.
 268
 269 2020-05-28  Alan Modra  <amodra@gmail.com>
 270
 271         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 272         immediates.
 273         (print_insn_ns32k): Revert last change.
 274
 275 2020-05-28  Nick Clifton  <nickc@redhat.com>
 276
 277         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 278         static.
 279
 280 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 281
 282         Fix extraction of signed constants in nios2 disassembler (again).
 283
 284         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 285         extractions of signed fields.
 286
 287 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 288
 289         * s390-opc.txt: Relocate vector load/store instructions with
 290         additional alignment parameter and change architecture level
 291         constraint from z14 to z13.
 292
 293 2020-05-21  Alan Modra  <amodra@gmail.com>
 294
 295         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 296         * sparc-dis.c: Likewise.
 297         * tic4x-dis.c: Likewise.
 298         * xtensa-dis.c: Likewise.
 299         * bpf-desc.c: Regenerate.
 300         * epiphany-desc.c: Regenerate.
 301         * fr30-desc.c: Regenerate.
 302         * frv-desc.c: Regenerate.
 303         * ip2k-desc.c: Regenerate.
 304         * iq2000-desc.c: Regenerate.
 305         * lm32-desc.c: Regenerate.
 306         * m32c-desc.c: Regenerate.
 307         * m32r-desc.c: Regenerate.
 308         * mep-asm.c: Regenerate.
 309         * mep-desc.c: Regenerate.
 310         * mt-desc.c: Regenerate.
 311         * or1k-desc.c: Regenerate.
 312         * xc16x-desc.c: Regenerate.
 313         * xstormy16-desc.c: Regenerate.
 314
 315 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 316
 317         * riscv-opc.c (riscv_ext_version_table): The table used to store
 318         all information about the supported spec and the corresponding ISA
 319         versions.  Currently, only Zicsr is supported to verify the
 320         correctness of Z sub extension settings.  Others will be supported
 321         in the future patches.
 322         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 323         classes and the corresponding strings.
 324         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 325         spec class by giving a ISA spec string.
 326         * riscv-opc.c (struct priv_spec_t): New structure.
 327         (struct priv_spec_t priv_specs): List for all supported privilege spec
 328         classes and the corresponding strings.
 329         (riscv_get_priv_spec_class): New function.  Get the corresponding
 330         privilege spec class by giving a spec string.
 331         (riscv_get_priv_spec_name): New function.  Get the corresponding
 332         privilege spec string by giving a CSR version class.
 333         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 334         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 335         according to the chosen version.  Build a hash table riscv_csr_hash to
 336         store the valid CSR for the chosen pirv verison.  Dump the direct
 337         CSR address rather than it's name if it is invalid.
 338         (parse_riscv_dis_option_without_args): New function.  Parse the options
 339         without arguments.
 340         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 341         parse the options without arguments first, and then handle the options
 342         with arguments.  Add the new option -Mpriv-spec, which has argument.
 343         * riscv-dis.c (print_riscv_disassembler_options): Add description
 344         about the new OBJDUMP option.
 345
 346 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 347
 348         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 349         WC values on POWER10 sync, dcbf  and wait instructions.
 350         (insert_pl, extract_pl): New functions.
 351         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 352         (LS3): New , 3-bit L for sync.
 353         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 354         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 355         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 356         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 357         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 358         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 359         <wait>: Enable PL operand on POWER10.
 360         <dcbf>: Enable L3OPT operand on POWER10.
 361         <sync>: Enable SC2 operand on POWER10.
 362
 363 2020-05-19  Stafford Horne  <shorne@gmail.com>
 364
 365         PR 25184
 366         * or1k-asm.c: Regenerate.
 367         * or1k-desc.c: Regenerate.
 368         * or1k-desc.h: Regenerate.
 369         * or1k-dis.c: Regenerate.
 370         * or1k-ibld.c: Regenerate.
 371         * or1k-opc.c: Regenerate.
 372         * or1k-opc.h: Regenerate.
 373         * or1k-opinst.c: Regenerate.
 374
 375 2020-05-11  Alan Modra  <amodra@gmail.com>
 376
 377         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 378         xsmaxcqp, xsmincqp.
 379
 380 2020-05-11  Alan Modra  <amodra@gmail.com>
 381
 382         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 383         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 384
 385 2020-05-11  Alan Modra  <amodra@gmail.com>
 386
 387         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 388
 389 2020-05-11  Alan Modra  <amodra@gmail.com>
 390
 391         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 392         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 393
 394 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 395
 396         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 397         mnemonics.
 398
 399 2020-05-11  Alan Modra  <amodra@gmail.com>
 400
 401         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 402         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 403         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 404         (prefix_opcodes): Add xxeval.
 405
 406 2020-05-11  Alan Modra  <amodra@gmail.com>
 407
 408         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 409         xxgenpcvwm, xxgenpcvdm.
 410
 411 2020-05-11  Alan Modra  <amodra@gmail.com>
 412
 413         * ppc-opc.c (MP, VXVAM_MASK): Define.
 414         (VXVAPS_MASK): Use VXVA_MASK.
 415         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 416         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 417         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 418         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 419
 420 2020-05-11  Alan Modra  <amodra@gmail.com>
 421             Peter Bergner  <bergner@linux.ibm.com>
 422
 423         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 424         New functions.
 425         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 426         YMSK2, XA6a, XA6ap, XB6a entries.
 427         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 428         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 429         (PPCVSX4): Define.
 430         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 431         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 432         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 433         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 434         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 435         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 436         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 437         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 438         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 439         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 440         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 441         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 442         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 443         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 444
 445 2020-05-11  Alan Modra  <amodra@gmail.com>
 446
 447         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 448         (insert_xts, extract_xts): New functions.
 449         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 450         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 451         (VXRC_MASK, VXSH_MASK): Define.
 452         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 453         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 454         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 455         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 456         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 457         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 458         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 459
 460 2020-05-11  Alan Modra  <amodra@gmail.com>
 461
 462         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 463         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 464         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 465         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 466         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 467
 468 2020-05-11  Alan Modra  <amodra@gmail.com>
 469
 470         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 471         (XTP, DQXP, DQXP_MASK): Define.
 472         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 473         (prefix_opcodes): Add plxvp and pstxvp.
 474
 475 2020-05-11  Alan Modra  <amodra@gmail.com>
 476
 477         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 478         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 479         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 480
 481 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 482
 483         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 484
 485 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 486
 487         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 488         (L1OPT): Define.
 489         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 490
 491 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 492
 493         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 494
 495 2020-05-11  Alan Modra  <amodra@gmail.com>
 496
 497         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 498
 499 2020-05-11  Alan Modra  <amodra@gmail.com>
 500
 501         * ppc-dis.c (ppc_opts): Add "power10" entry.
 502         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 503         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 504
 505 2020-05-11  Nick Clifton  <nickc@redhat.com>
 506
 507         * po/fr.po: Updated French translation.
 508
 509 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 510
 511         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 512         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 513         (operand_general_constraint_met_p): validate
 514         AARCH64_OPND_UNDEFINED.
 515         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 516         for FLD_imm16_2.
 517         * aarch64-asm-2.c: Regenerated.
 518         * aarch64-dis-2.c: Regenerated.
 519         * aarch64-opc-2.c: Regenerated.
 520
 521 2020-04-29  Nick Clifton  <nickc@redhat.com>
 522
 523         PR 22699
 524         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 525         and SETRC insns.
 526
 527 2020-04-29  Nick Clifton  <nickc@redhat.com>
 528
 529         * po/sv.po: Updated Swedish translation.
 530
 531 2020-04-29  Nick Clifton  <nickc@redhat.com>
 532
 533         PR 22699
 534         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 535         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 536         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 537         IMM0_8U case.
 538
 539 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 540
 541         PR 25848
 542         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 543         cmpi only on m68020up and cpu32.
 544
 545 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 546
 547         * aarch64-asm.c (aarch64_ins_none): New.
 548         * aarch64-asm.h (ins_none): New declaration.
 549         * aarch64-dis.c (aarch64_ext_none): New.
 550         * aarch64-dis.h (ext_none): New declaration.
 551         * aarch64-opc.c (aarch64_print_operand): Update case for
 552         AARCH64_OPND_BARRIER_PSB.
 553         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 554         (AARCH64_OPERANDS): Update inserter/extracter for
 555         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 556         * aarch64-asm-2.c: Regenerated.
 557         * aarch64-dis-2.c: Regenerated.
 558         * aarch64-opc-2.c: Regenerated.
 559
 560 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 561
 562         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 563         (aarch64_feature_ras, RAS): Likewise.
 564         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 565         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 566         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 567         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 568         * aarch64-asm-2.c: Regenerated.
 569         * aarch64-dis-2.c: Regenerated.
 570         * aarch64-opc-2.c: Regenerated.
 571
 572 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 573
 574         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 575         (print_insn_neon): Support disassembly of conditional
 576         instructions.
 577
 578 2020-02-16  David Faust  <david.faust@oracle.com>
 579
 580         * bpf-desc.c: Regenerate.
 581         * bpf-desc.h: Likewise.
 582         * bpf-opc.c: Regenerate.
 583         * bpf-opc.h: Likewise.
 584
 585 2020-04-07  Lili Cui  <lili.cui@intel.com>
 586
 587         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 588         (prefix_table): New instructions (see prefixes above).
 589         (rm_table): Likewise
 590         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 591         CPU_ANY_TSXLDTRK_FLAGS.
 592         (cpu_flags): Add CpuTSXLDTRK.
 593         * i386-opc.h (enum): Add CpuTSXLDTRK.
 594         (i386_cpu_flags): Add cputsxldtrk.
 595         * i386-opc.tbl: Add XSUSPLDTRK insns.
 596         * i386-init.h: Regenerate.
 597         * i386-tbl.h: Likewise.
 598
 599 2020-04-02  Lili Cui  <lili.cui@intel.com>
 600
 601         * i386-dis.c (prefix_table): New instructions serialize.
 602         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 603         CPU_ANY_SERIALIZE_FLAGS.
 604         (cpu_flags): Add CpuSERIALIZE.
 605         * i386-opc.h (enum): Add CpuSERIALIZE.
 606         (i386_cpu_flags): Add cpuserialize.
 607         * i386-opc.tbl: Add SERIALIZE insns.
 608         * i386-init.h: Regenerate.
 609         * i386-tbl.h: Likewise.
 610
 611 2020-03-26  Alan Modra  <amodra@gmail.com>
 612
 613         * disassemble.h (opcodes_assert): Declare.
 614         (OPCODES_ASSERT): Define.
 615         * disassemble.c: Don't include assert.h.  Include opintl.h.
 616         (opcodes_assert): New function.
 617         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 618         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 619         calculate maxlen.  Omit insn decoding when insn length exceeds
 620         maxlen.  Exit from nibble loop when looking for E, before
 621         accessing next data byte.  Move processing of E outside loop.
 622         Replace tests of maxlen in loop with assertions.
 623
 624 2020-03-26  Alan Modra  <amodra@gmail.com>
 625
 626         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 627
 628 2020-03-25  Alan Modra  <amodra@gmail.com>
 629
 630         * z80-dis.c (suffix): Init mybuf.
 631
 632 2020-03-22  Alan Modra  <amodra@gmail.com>
 633
 634         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 635         successflly read from section.
 636
 637 2020-03-22  Alan Modra  <amodra@gmail.com>
 638
 639         * arc-dis.c (find_format): Use ISO C string concatenation rather
 640         than line continuation within a string.  Don't access needs_limm
 641         before testing opcode != NULL.
 642
 643 2020-03-22  Alan Modra  <amodra@gmail.com>
 644
 645         * ns32k-dis.c (print_insn_arg): Update comment.
 646         (print_insn_ns32k): Reduce size of index_offset array, and
 647         initialize, passing -1 to print_insn_arg for args that are not
 648         an index.  Don't exit arg loop early.  Abort on bad arg number.
 649
 650 2020-03-22  Alan Modra  <amodra@gmail.com>
 651
 652         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 653         * s12z-opc.c: Formatting.
 654         (operands_f): Return an int.
 655         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 656         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 657         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 658         (exg_sex_discrim): Likewise.
 659         (create_immediate_operand, create_bitfield_operand),
 660         (create_register_operand_with_size, create_register_all_operand),
 661         (create_register_all16_operand, create_simple_memory_operand),
 662         (create_memory_operand, create_memory_auto_operand): Don't
 663         segfault on malloc failure.
 664         (z_ext24_decode): Return an int status, negative on fail, zero
 665         on success.
 666         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 667         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 668         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 669         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 670         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 671         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 672         (loop_primitive_decode, shift_decode, psh_pul_decode),
 673         (bit_field_decode): Similarly.
 674         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 675         to return value, update callers.
 676         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 677         Don't segfault on NULL operand.
 678         (decode_operation): Return OP_INVALID on first fail.
 679         (decode_s12z): Check all reads, returning -1 on fail.
 680
 681 2020-03-20  Alan Modra  <amodra@gmail.com>
 682
 683         * metag-dis.c (print_insn_metag): Don't ignore status from
 684         read_memory_func.
 685
 686 2020-03-20  Alan Modra  <amodra@gmail.com>
 687
 688         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 689         Initialize parts of buffer not written when handling a possible
 690         2-byte insn at end of section.  Don't attempt decoding of such
 691         an insn by the 4-byte machinery.
 692
 693 2020-03-20  Alan Modra  <amodra@gmail.com>
 694
 695         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 696         partially filled buffer.  Prevent lookup of 4-byte insns when
 697         only VLE 2-byte insns are possible due to section size.  Print
 698         ".word" rather than ".long" for 2-byte leftovers.
 699
 700 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 701
 702         PR 25641
 703         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 704
 705 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 706
 707         * i386-dis.c (X86_64_0D): Rename to ...
 708         (X86_64_0E): ... this.
 709
 710 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 711
 712         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 713         * Makefile.in: Regenerated.
 714
 715 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 718         3-operand pseudos.
 719         * i386-tbl.h: Re-generate.
 720
 721 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 724         vprot*, vpsha*, and vpshl*.
 725         * i386-tbl.h: Re-generate.
 726
 727 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 728
 729         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 730         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 731         * i386-tbl.h: Re-generate.
 732
 733 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 734
 735         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 736         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 737         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 738         * i386-tbl.h: Re-generate.
 739
 740 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-gen.c (struct template_arg, struct template_instance,
 743         struct template_param, struct template, templates,
 744         parse_template, expand_templates): New.
 745         (process_i386_opcodes): Various local variables moved to
 746         expand_templates. Call parse_template and expand_templates.
 747         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 748         * i386-tbl.h: Re-generate.
 749
 750 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 753         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 754         register and memory source templates. Replace VexW= by VexW*
 755         where applicable.
 756         * i386-tbl.h: Re-generate.
 757
 758 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 761         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 762         * i386-tbl.h: Re-generate.
 763
 764 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 767         * i386-tbl.h: Re-generate.
 768
 769 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 772         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 773         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 774         VexW0 on SSE2AVX variants.
 775         (vmovq): Drop NoRex64 from XMM/XMM variants.
 776         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 777         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 778         applicable use VexW0.
 779         * i386-tbl.h: Re-generate.
 780
 781 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 784         * i386-opc.h (Rex64): Delete.
 785         (struct i386_opcode_modifier): Remove rex64 field.
 786         * i386-opc.tbl (crc32): Drop Rex64.
 787         Replace Rex64 with Size64 everywhere else.
 788         * i386-tbl.h: Re-generate.
 789
 790 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 791
 792         * i386-dis.c (OP_E_memory): Exclude recording of used address
 793         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 794         addressed memory operands for MPX insns.
 795
 796 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 799         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 800         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 801         (ptwrite): Split into non-64-bit and 64-bit forms.
 802         * i386-tbl.h: Re-generate.
 803
 804 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 807         template.
 808         * i386-tbl.h: Re-generate.
 809
 810 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 813         (prefix_table): Move vmmcall here. Add vmgexit.
 814         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 815         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 816         (cpu_flags): Add CpuSEV_ES entry.
 817         * i386-opc.h (CpuSEV_ES): New.
 818         (union i386_cpu_flags): Add cpusev_es field.
 819         * i386-opc.tbl (vmgexit): New.
 820         * i386-init.h, i386-tbl.h: Re-generate.
 821
 822 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 823
 824         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 825         with MnemonicSize.
 826         * i386-opc.h (IGNORESIZE): New.
 827         (DEFAULTSIZE): Likewise.
 828         (IgnoreSize): Removed.
 829         (DefaultSize): Likewise.
 830         (MnemonicSize): New.
 831         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 832         mnemonicsize.
 833         * i386-opc.tbl (IgnoreSize): New.
 834         (DefaultSize): Likewise.
 835         * i386-tbl.h: Regenerated.
 836
 837 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 838
 839         PR 25627
 840         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 841         instructions.
 842
 843 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 844
 845         PR gas/25622
 846         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 847         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 848         * i386-tbl.h: Regenerated.
 849
 850 2020-02-26  Alan Modra  <amodra@gmail.com>
 851
 852         * aarch64-asm.c: Indent labels correctly.
 853         * aarch64-dis.c: Likewise.
 854         * aarch64-gen.c: Likewise.
 855         * aarch64-opc.c: Likewise.
 856         * alpha-dis.c: Likewise.
 857         * i386-dis.c: Likewise.
 858         * nds32-asm.c: Likewise.
 859         * nfp-dis.c: Likewise.
 860         * visium-dis.c: Likewise.
 861
 862 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 863
 864         * arc-regs.h (int_vector_base): Make it available for all ARC
 865         CPUs.
 866
 867 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 868
 869         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 870         changed.
 871
 872 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 873
 874         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 875         c.mv/c.li if rs1 is zero.
 876
 877 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 878
 879         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 880         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 881         CPU_POPCNT_FLAGS.
 882         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 883         * i386-opc.h (CpuABM): Removed.
 884         (CpuPOPCNT): New.
 885         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 886         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 887         popcnt.  Remove CpuABM from lzcnt.
 888         * i386-init.h: Regenerated.
 889         * i386-tbl.h: Likewise.
 890
 891 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 894         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 895         VexW1 instead of open-coding them.
 896         * i386-tbl.h: Re-generate.
 897
 898 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-opc.tbl (AddrPrefixOpReg): Define.
 901         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 902         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 903         templates. Drop NoRex64.
 904         * i386-tbl.h: Re-generate.
 905
 906 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 907
 908         PR gas/6518
 909         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 910         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 911         into Intel syntax instance (with Unpsecified) and AT&T one
 912         (without).
 913         (vcvtneps2bf16): Likewise, along with folding the two so far
 914         separate ones.
 915         * i386-tbl.h: Re-generate.
 916
 917 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 918
 919         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 920         CPU_ANY_SSE4A_FLAGS.
 921
 922 2020-02-17  Alan Modra  <amodra@gmail.com>
 923
 924         * i386-gen.c (cpu_flag_init): Correct last change.
 925
 926 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 927
 928         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 929         CPU_ANY_SSE4_FLAGS.
 930
 931 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 932
 933         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 934         (movzx): Likewise.
 935
 936 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 937
 938         PR gas/25438
 939         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 940         destination for Cpu64-only variant.
 941         (movzx): Fold patterns.
 942         * i386-tbl.h: Re-generate.
 943
 944 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 945
 946         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 947         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 948         CPU_ANY_SSE4_FLAGS entry.
 949         * i386-init.h: Re-generate.
 950
 951 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 952
 953         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 954         with Unspecified, making the present one AT&T syntax only.
 955         * i386-tbl.h: Re-generate.
 956
 957 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 960         * i386-tbl.h: Re-generate.
 961
 962 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 963
 964         PR gas/24546
 965         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 966         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 967         Amd64 and Intel64 templates.
 968         (call, jmp): Likewise for far indirect variants. Dro
 969         Unspecified.
 970         * i386-tbl.h: Re-generate.
 971
 972 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 973
 974         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 975         * i386-opc.h (ShortForm): Delete.
 976         (struct i386_opcode_modifier): Remove shortform field.
 977         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 978         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 979         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 980         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 981         Drop ShortForm.
 982         * i386-tbl.h: Re-generate.
 983
 984 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 985
 986         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 987         fucompi): Drop ShortForm from operand-less templates.
 988         * i386-tbl.h: Re-generate.
 989
 990 2020-02-11  Alan Modra  <amodra@gmail.com>
 991
 992         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 993         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 994         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 995         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 996         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 997
 998 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 999
1000         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1001         (cde_opcodes): Add VCX* instructions.
1002
1003 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1004             Matthew Malcomson  <matthew.malcomson@arm.com>
1005
1006         * arm-dis.c (struct cdeopcode32): New.
1007         (CDE_OPCODE): New macro.
1008         (cde_opcodes): New disassembly table.
1009         (regnames): New option to table.
1010         (cde_coprocs): New global variable.
1011         (print_insn_cde): New
1012         (print_insn_thumb32): Use print_insn_cde.
1013         (parse_arm_disassembler_options): Parse coprocN args.
1014
1015 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1016
1017         PR gas/25516
1018         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1019         with ISA64.
1020         * i386-opc.h (AMD64): Removed.
1021         (Intel64): Likewose.
1022         (AMD64): New.
1023         (INTEL64): Likewise.
1024         (INTEL64ONLY): Likewise.
1025         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1026         * i386-opc.tbl (Amd64): New.
1027         (Intel64): Likewise.
1028         (Intel64Only): Likewise.
1029         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1030         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1031         * i386-tbl.h: Regenerated.
1032
1033 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1034
1035         PR 25469
1036         * z80-dis.c: Add support for GBZ80 opcodes.
1037
1038 2020-02-04  Alan Modra  <amodra@gmail.com>
1039
1040         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1041
1042 2020-02-03  Alan Modra  <amodra@gmail.com>
1043
1044         * m32c-ibld.c: Regenerate.
1045
1046 2020-02-01  Alan Modra  <amodra@gmail.com>
1047
1048         * frv-ibld.c: Regenerate.
1049
1050 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1053         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1054         (OP_E_memory): Replace xmm_mdq_mode case label by
1055         vex_scalar_w_dq_mode one.
1056         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1057
1058 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1061         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1062         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1063         (intel_operand_size): Drop vex_w_dq_mode case label.
1064
1065 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1066
1067         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1068         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1069
1070 2020-01-30  Alan Modra  <amodra@gmail.com>
1071
1072         * m32c-ibld.c: Regenerate.
1073
1074 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1075
1076         * bpf-opc.c: Regenerate.
1077
1078 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1081         (dis386): Use them to replace C2/C3 table entries.
1082         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1083         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1084         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1085         * i386-tbl.h: Re-generate.
1086
1087 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1090         forms.
1091         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1092         DefaultSize.
1093         * i386-tbl.h: Re-generate.
1094
1095 2020-01-30  Alan Modra  <amodra@gmail.com>
1096
1097         * tic4x-dis.c (tic4x_dp): Make unsigned.
1098
1099 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1100             Jan Beulich  <jbeulich@suse.com>
1101
1102         PR binutils/25445
1103         * i386-dis.c (MOVSXD_Fixup): New function.
1104         (movsxd_mode): New enum.
1105         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1106         (intel_operand_size): Handle movsxd_mode.
1107         (OP_E_register): Likewise.
1108         (OP_G): Likewise.
1109         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1110         register on movsxd.  Add movsxd with 16-bit destination register
1111         for AMD64 and Intel64 ISAs.
1112         * i386-tbl.h: Regenerated.
1113
1114 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1115
1116         PR 25403
1117         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1118         * aarch64-asm-2.c: Regenerate
1119         * aarch64-dis-2.c: Likewise.
1120         * aarch64-opc-2.c: Likewise.
1121
1122 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1123
1124         * i386-opc.tbl (sysret): Drop DefaultSize.
1125         * i386-tbl.h: Re-generate.
1126
1127 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1130         Dword.
1131         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1132         * i386-tbl.h: Re-generate.
1133
1134 2020-01-20  Nick Clifton  <nickc@redhat.com>
1135
1136         * po/de.po: Updated German translation.
1137         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1138         * po/uk.po: Updated Ukranian translation.
1139
1140 2020-01-20  Alan Modra  <amodra@gmail.com>
1141
1142         * hppa-dis.c (fput_const): Remove useless cast.
1143
1144 2020-01-20  Alan Modra  <amodra@gmail.com>
1145
1146         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1147
1148 2020-01-18  Nick Clifton  <nickc@redhat.com>
1149
1150         * configure: Regenerate.
1151         * po/opcodes.pot: Regenerate.
1152
1153 2020-01-18  Nick Clifton  <nickc@redhat.com>
1154
1155         Binutils 2.34 branch created.
1156
1157 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1158
1159         * opintl.h: Fix spelling error (seperate).
1160
1161 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1162
1163         * i386-opc.tbl: Add {vex} pseudo prefix.
1164         * i386-tbl.h: Regenerated.
1165
1166 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1167
1168         PR 25376
1169         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1170         (neon_opcodes): Likewise.
1171         (select_arm_features): Make sure we enable MVE bits when selecting
1172         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1173         any architecture.
1174
1175 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1176
1177         * i386-opc.tbl: Drop stale comment from XOP section.
1178
1179 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1180
1181         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1182         (extractps): Add VexWIG to SSE2AVX forms.
1183         * i386-tbl.h: Re-generate.
1184
1185 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1186
1187         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1188         Size64 from and use VexW1 on SSE2AVX forms.
1189         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1190         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1191         * i386-tbl.h: Re-generate.
1192
1193 2020-01-15  Alan Modra  <amodra@gmail.com>
1194
1195         * tic4x-dis.c (tic4x_version): Make unsigned long.
1196         (optab, optab_special, registernames): New file scope vars.
1197         (tic4x_print_register): Set up registernames rather than
1198         malloc'd registertable.
1199         (tic4x_disassemble): Delete optable and optable_special.  Use
1200         optab and optab_special instead.  Throw away old optab,
1201         optab_special and registernames when info->mach changes.
1202
1203 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1204
1205         PR 25377
1206         * z80-dis.c (suffix): Use .db instruction to generate double
1207         prefix.
1208
1209 2020-01-14  Alan Modra  <amodra@gmail.com>
1210
1211         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1212         values to unsigned before shifting.
1213
1214 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1215
1216         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1217         flow instructions.
1218         (print_insn_thumb16, print_insn_thumb32): Likewise.
1219         (print_insn): Initialize the insn info.
1220         * i386-dis.c (print_insn): Initialize the insn info fields, and
1221         detect jumps.
1222
1223 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1224
1225         * arc-opc.c (C_NE): Make it required.
1226
1227 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1228
1229         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1230         reserved register name.
1231
1232 2020-01-13  Alan Modra  <amodra@gmail.com>
1233
1234         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1235         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1236
1237 2020-01-13  Alan Modra  <amodra@gmail.com>
1238
1239         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1240         result of wasm_read_leb128 in a uint64_t and check that bits
1241         are not lost when copying to other locals.  Use uint32_t for
1242         most locals.  Use PRId64 when printing int64_t.
1243
1244 2020-01-13  Alan Modra  <amodra@gmail.com>
1245
1246         * score-dis.c: Formatting.
1247         * score7-dis.c: Formatting.
1248
1249 2020-01-13  Alan Modra  <amodra@gmail.com>
1250
1251         * score-dis.c (print_insn_score48): Use unsigned variables for
1252         unsigned values.  Don't left shift negative values.
1253         (print_insn_score32): Likewise.
1254         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1255
1256 2020-01-13  Alan Modra  <amodra@gmail.com>
1257
1258         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1259
1260 2020-01-13  Alan Modra  <amodra@gmail.com>
1261
1262         * fr30-ibld.c: Regenerate.
1263
1264 2020-01-13  Alan Modra  <amodra@gmail.com>
1265
1266         * xgate-dis.c (print_insn): Don't left shift signed value.
1267         (ripBits): Formatting, use 1u.
1268
1269 2020-01-10  Alan Modra  <amodra@gmail.com>
1270
1271         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1272         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1273
1274 2020-01-10  Alan Modra  <amodra@gmail.com>
1275
1276         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1277         and XRREG value earlier to avoid a shift with negative exponent.
1278         * m10200-dis.c (disassemble): Similarly.
1279
1280 2020-01-09  Nick Clifton  <nickc@redhat.com>
1281
1282         PR 25224
1283         * z80-dis.c (ld_ii_ii): Use correct cast.
1284
1285 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1286
1287         PR 25224
1288         * z80-dis.c (ld_ii_ii): Use character constant when checking
1289         opcode byte value.
1290
1291 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1292
1293         * i386-dis.c (SEP_Fixup): New.
1294         (SEP): Define.
1295         (dis386_twobyte): Use it for sysenter/sysexit.
1296         (enum x86_64_isa): Change amd64 enumerator to value 1.
1297         (OP_J): Compare isa64 against intel64 instead of amd64.
1298         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1299         forms.
1300         * i386-tbl.h: Re-generate.
1301
1302 2020-01-08  Alan Modra  <amodra@gmail.com>
1303
1304         * z8k-dis.c: Include libiberty.h
1305         (instr_data_s): Make max_fetched unsigned.
1306         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1307         Don't exceed byte_info bounds.
1308         (output_instr): Make num_bytes unsigned.
1309         (unpack_instr): Likewise for nibl_count and loop.
1310         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1311         idx unsigned.
1312         * z8k-opc.h: Regenerate.
1313
1314 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1315
1316         * arc-tbl.h (llock): Use 'LLOCK' as class.
1317         (llockd): Likewise.
1318         (scond): Use 'SCOND' as class.
1319         (scondd): Likewise.
1320         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1321         (scondd): Likewise.
1322
1323 2020-01-06  Alan Modra  <amodra@gmail.com>
1324
1325         * m32c-ibld.c: Regenerate.
1326
1327 2020-01-06  Alan Modra  <amodra@gmail.com>
1328
1329         PR 25344
1330         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1331         Peek at next byte to prevent recursion on repeated prefix bytes.
1332         Ensure uninitialised "mybuf" is not accessed.
1333         (print_insn_z80): Don't zero n_fetch and n_used here,..
1334         (print_insn_z80_buf): ..do it here instead.
1335
1336 2020-01-04  Alan Modra  <amodra@gmail.com>
1337
1338         * m32r-ibld.c: Regenerate.
1339
1340 2020-01-04  Alan Modra  <amodra@gmail.com>
1341
1342         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1343
1344 2020-01-04  Alan Modra  <amodra@gmail.com>
1345
1346         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1347
1348 2020-01-04  Alan Modra  <amodra@gmail.com>
1349
1350         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1351
1352 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1353
1354         * aarch64-tbl.h (aarch64_opcode_table): Use
1355         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1356
1357 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1358
1359         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1360         forms of SUDOT and USDOT.
1361
1362 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1363
1364         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1365         uzip{1,2}.
1366         * opcodes/aarch64-dis-2.c: Re-generate.
1367
1368 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1369
1370         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1371         FMMLA encoding.
1372         * opcodes/aarch64-dis-2.c: Re-generate.
1373
1374 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1375
1376         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1377
1378 2020-01-01  Alan Modra  <amodra@gmail.com>
1379
1380         Update year range in copyright notice of all files.
1381
1382 For older changes see ChangeLog-2019
1383 \f
1384 Copyright (C) 2020 Free Software Foundation, Inc.
1385
1386 Copying and distribution of this file, with or without modification,
1387 are permitted in any medium without royalty provided the copyright
1388 notice and this notice are preserved.
1389
1390 Local Variables:
1391 mode: change-log
1392 left-margin: 8
1393 fill-column: 74
1394 version-control: never
1395 End: