1 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
3 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
4 * ppc-opc.c (FXM4): Add non-zero optional value.
7 (insert_fxm): Handle new default operand value.
8 (extract_fxm): Likewise.
9 (insert_tbr): Likewise.
10 (extract_tbr): Likewise.
12 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
14 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
16 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
18 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
20 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
22 * ppc-opc.c: Add comment accidentally removed by old commit.
25 2015-06-04 Nick Clifton <nickc@redhat.com>
28 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
30 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
32 * arm-dis.c (arm_opcodes): Add "setpan".
33 (thumb_opcodes): Add "setpan".
35 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
37 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
40 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
42 * aarch64-tbl.h (aarch64_feature_rdma): New.
44 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Regenerate.
47 * aarch64-opc-2.c: Regenerate.
49 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
51 * aarch64-tbl.h (aarch64_feature_lor): New.
53 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
55 * aarch64-asm-2.c: Regenerate.
56 * aarch64-dis-2.c: Regenerate.
57 * aarch64-opc-2.c: Regenerate.
59 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
61 * aarch64-opc.c (F_ARCHEXT): New.
62 (aarch64_sys_regs): Add "pan".
63 (aarch64_sys_reg_supported_p): New.
64 (aarch64_pstatefields): Add "pan".
65 (aarch64_pstatefield_supported_p): New.
67 2015-06-01 Jan Beulich <jbeulich@suse.com>
69 * i386-tbl.h: Regenerate.
71 2015-06-01 Jan Beulich <jbeulich@suse.com>
73 * i386-dis.c (print_insn): Swap rounding mode specifier and
74 general purpose register in Intel mode.
76 2015-06-01 Jan Beulich <jbeulich@suse.com>
78 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
79 * i386-tbl.h: Regenerate.
81 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
83 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
84 * i386-init.h: Regenerated.
86 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
89 * i386-dis.c: Add comments for '@'.
90 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
91 (enum x86_64_isa): New.
93 (print_i386_disassembler_options): Add amd64 and intel64.
94 (print_insn): Handle amd64 and intel64.
96 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
97 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
98 * i386-opc.h (AMD64): New.
99 (CpuIntel64): Likewise.
100 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
101 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
102 Mark direct call/jmp without Disp16|Disp32 as Intel64.
103 * i386-init.h: Regenerated.
104 * i386-tbl.h: Likewise.
106 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
108 * ppc-opc.c (IH) New define.
109 (powerpc_opcodes) <wait>: Do not enable for POWER7.
110 <tlbie>: Add RS operand for POWER7.
111 <slbia>: Add IH operand for POWER6.
113 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
115 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
118 * i386-tbl.h: Regenerated.
120 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
122 * configure.ac: Support bfd_iamcu_arch.
123 * disassemble.c (disassembler): Support bfd_iamcu_arch.
124 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
125 CPU_IAMCU_COMPAT_FLAGS.
126 (cpu_flags): Add CpuIAMCU.
127 * i386-opc.h (CpuIAMCU): New.
128 (i386_cpu_flags): Add cpuiamcu.
129 * configure: Regenerated.
130 * i386-init.h: Likewise.
131 * i386-tbl.h: Likewise.
133 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
136 * i386-dis.c (X86_64_E8): New.
137 (X86_64_E9): Likewise.
138 Update comments on 'T', 'U', 'V'. Add comments for '^'.
139 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
140 (x86_64_table): Add X86_64_E8 and X86_64_E9.
141 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
143 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
146 2015-04-30 DJ Delorie <dj@redhat.com>
148 * disassemble.c (disassembler): Choose suitable disassembler based
150 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
151 it to decode mul/div insns.
152 * rl78-decode.c: Regenerate.
153 * rl78-dis.c (print_insn_rl78): Rename to...
154 (print_insn_rl78_common): ...this, take ISA parameter.
155 (print_insn_rl78): New.
156 (print_insn_rl78_g10): New.
157 (print_insn_rl78_g13): New.
158 (print_insn_rl78_g14): New.
159 (rl78_get_disassembler): New.
161 2015-04-29 Nick Clifton <nickc@redhat.com>
163 * po/fr.po: Updated French translation.
165 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
167 * ppc-opc.c (DCBT_EO): New define.
168 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
172 <waitrsv>: Do not enable for POWER7 and later.
173 <waitimpl>: Likewise.
174 <dcbt>: Default to the two operand form of the instruction for all
175 "old" cpus. For "new" cpus, use the operand ordering that matches
176 whether the cpu is server or embedded.
179 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
181 * s390-opc.c: New instruction type VV0UU2.
182 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
185 2015-04-23 Jan Beulich <jbeulich@suse.com>
187 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
188 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
189 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
190 (vfpclasspd, vfpclassps): Add %XZ.
192 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
194 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
195 (PREFIX_UD_REPZ): Likewise.
196 (PREFIX_UD_REPNZ): Likewise.
197 (PREFIX_UD_DATA): Likewise.
198 (PREFIX_UD_ADDR): Likewise.
199 (PREFIX_UD_LOCK): Likewise.
201 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
203 * i386-dis.c (prefix_requirement): Removed.
204 (print_insn): Don't set prefix_requirement. Check
205 dp->prefix_requirement instead of prefix_requirement.
207 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
210 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
211 (PREFIX_MOD_0_0FC7_REG_6): This.
212 (PREFIX_MOD_3_0FC7_REG_6): New.
213 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
214 (prefix_table): Replace PREFIX_0FC7_REG_6 with
215 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
216 PREFIX_MOD_3_0FC7_REG_7.
217 (mod_table): Replace PREFIX_0FC7_REG_6 with
218 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
219 PREFIX_MOD_3_0FC7_REG_7.
221 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
223 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
224 (PREFIX_MANDATORY_REPNZ): Likewise.
225 (PREFIX_MANDATORY_DATA): Likewise.
226 (PREFIX_MANDATORY_ADDR): Likewise.
227 (PREFIX_MANDATORY_LOCK): Likewise.
228 (PREFIX_MANDATORY): Likewise.
229 (PREFIX_UD_SHIFT): Set to 8
230 (PREFIX_UD_REPZ): Updated.
231 (PREFIX_UD_REPNZ): Likewise.
232 (PREFIX_UD_DATA): Likewise.
233 (PREFIX_UD_ADDR): Likewise.
234 (PREFIX_UD_LOCK): Likewise.
235 (PREFIX_IGNORED_SHIFT): New.
236 (PREFIX_IGNORED_REPZ): Likewise.
237 (PREFIX_IGNORED_REPNZ): Likewise.
238 (PREFIX_IGNORED_DATA): Likewise.
239 (PREFIX_IGNORED_ADDR): Likewise.
240 (PREFIX_IGNORED_LOCK): Likewise.
241 (PREFIX_OPCODE): Likewise.
242 (PREFIX_IGNORED): Likewise.
243 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
244 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
245 (three_byte_table): Likewise.
246 (mod_table): Likewise.
247 (mandatory_prefix): Renamed to ...
248 (prefix_requirement): This.
249 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
250 Update PREFIX_90 entry.
251 (get_valid_dis386): Check prefix_requirement to see if a prefix
253 (print_insn): Replace mandatory_prefix with prefix_requirement.
255 2015-04-15 Renlin Li <renlin.li@arm.com>
257 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
258 use it for ssat and ssat16.
259 (print_insn_thumb32): Add handle case for 'D' control code.
261 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
262 H.J. Lu <hongjiu.lu@intel.com>
264 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
265 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
266 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
267 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
268 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
269 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
270 Fill prefix_requirement field.
271 (struct dis386): Add prefix_requirement field.
272 (dis386): Fill prefix_requirement field.
273 (dis386_twobyte): Ditto.
274 (twobyte_has_mandatory_prefix_: Remove.
275 (reg_table): Fill prefix_requirement field.
276 (prefix_table): Ditto.
277 (x86_64_table): Ditto.
278 (three_byte_table): Ditto.
281 (vex_len_table): Ditto.
282 (vex_w_table): Ditto.
285 (print_insn): Use prefix_requirement.
286 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
287 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
290 2015-03-30 Mike Frysinger <vapier@gentoo.org>
292 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
294 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
296 * Makefile.in: Regenerated.
298 2015-03-25 Anton Blanchard <anton@samba.org>
300 * ppc-dis.c (disassemble_init_powerpc): Only initialise
301 powerpc_opcd_indices and vle_opcd_indices once.
303 2015-03-25 Anton Blanchard <anton@samba.org>
305 * ppc-opc.c (powerpc_opcodes): Add slbfee.
307 2015-03-24 Terry Guo <terry.guo@arm.com>
309 * arm-dis.c (opcode32): Updated to use new arm feature struct.
310 (opcode16): Likewise.
311 (coprocessor_opcodes): Replace bit with feature struct.
312 (neon_opcodes): Likewise.
313 (arm_opcodes): Likewise.
314 (thumb_opcodes): Likewise.
315 (thumb32_opcodes): Likewise.
316 (print_insn_coprocessor): Likewise.
317 (print_insn_arm): Likewise.
318 (select_arm_features): Follow new feature struct.
320 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
322 * i386-dis.c (rm_table): Add clzero.
323 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
324 Add CPU_CLZERO_FLAGS.
325 (cpu_flags): Add CpuCLZERO.
326 * i386-opc.h: Add CpuCLZERO.
327 * i386-opc.tbl: Add clzero.
328 * i386-init.h: Re-generated.
329 * i386-tbl.h: Re-generated.
331 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
333 * mips-opc.c (decode_mips_operand): Fix constraint issues
334 with u and y operands.
336 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
338 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
340 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
342 * s390-opc.c: Add new IBM z13 instructions.
343 * s390-opc.txt: Likewise.
345 2015-03-10 Renlin Li <renlin.li@arm.com>
347 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
348 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
350 * aarch64-asm-2.c: Regenerate.
351 * aarch64-dis-2.c: Likewise.
352 * aarch64-opc-2.c: Likewise.
354 2015-03-03 Jiong Wang <jiong.wang@arm.com>
356 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
358 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
360 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
362 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
363 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
365 2015-02-23 Vinay <Vinay.G@kpit.com>
367 * rl78-decode.opc (MOV): Added space between two operands for
368 'mov' instruction in index addressing mode.
369 * rl78-decode.c: Regenerate.
371 2015-02-19 Pedro Alves <palves@redhat.com>
373 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
375 2015-02-10 Pedro Alves <palves@redhat.com>
376 Tom Tromey <tromey@redhat.com>
378 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
379 microblaze_and, microblaze_xor.
380 * microblaze-opc.h (opcodes): Adjust.
382 2015-01-28 James Bowman <james.bowman@ftdichip.com>
384 * Makefile.am: Add FT32 files.
385 * configure.ac: Handle FT32.
386 * disassemble.c (disassembler): Call print_insn_ft32.
387 * ft32-dis.c: New file.
388 * ft32-opc.c: New file.
389 * Makefile.in: Regenerate.
390 * configure: Regenerate.
391 * po/POTFILES.in: Regenerate.
393 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
395 * nds32-asm.c (keyword_sr): Add new system registers.
397 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
399 * s390-dis.c (s390_extract_operand): Support vector register
401 (s390_print_insn_with_opcode): Support new operands types and add
402 new handling of optional operands.
403 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
404 and include opcode/s390.h instead.
405 (struct op_struct): New field `flags'.
406 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
407 (dumpTable): Dump flags.
408 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
410 * s390-opc.c: Add new operands types, instruction formats, and
412 (s390_opformats): Add new formats for .insn.
413 * s390-opc.txt: Add new instructions.
415 2015-01-01 Alan Modra <amodra@gmail.com>
417 Update year range in copyright notice of all files.
419 For older changes see ChangeLog-2014
421 Copyright (C) 2015 Free Software Foundation, Inc.
423 Copying and distribution of this file, with or without modification,
424 are permitted in any medium without royalty provided the copyright
425 notice and this notice are preserved.
431 version-control: never