1 2019-11-08 Jan Beulich <jbeulich@suse.com>
3 * i386-gen.c (operand_type_init): Add Class=. New
4 OPERAND_TYPE_ANYIMM entry.
5 (operand_classes): New.
6 (operand_types): Drop Reg entry.
7 (output_operand_type): New parameter "class". Process it.
8 (process_i386_operand_type): New local variable "class".
9 (main): Adjust static assertions.
10 * i386-opc.h (CLASS_WIDTH): Define.
11 (enum operand_class): New.
12 (Reg): Replace by Class. Adjust comment.
13 (union i386_operand_type): Replace reg by class.
14 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
16 * i386-reg.tbl: Replace Reg by Class=Reg.
17 * i386-init.h: Re-generate.
19 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
21 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
22 (aarch64_opcode_table): Add data gathering hint mnemonic.
23 * opcodes/aarch64-dis-2.c: Account for new instruction.
25 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
27 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
30 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
32 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
33 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
34 aarch64_feature_f64mm): New feature sets.
35 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
36 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
38 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
40 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
41 (OP_SVE_QQQ): New qualifier.
42 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
43 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
44 the movprfx constraint.
45 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
46 (aarch64_opcode_table): Define new instructions smmla,
47 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
49 * aarch64-opc.c (operand_general_constraint_met_p): Handle
50 AARCH64_OPND_SVE_ADDR_RI_S4x32.
51 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
52 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
53 Account for new instructions.
54 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
56 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
58 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
59 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
61 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
63 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
64 (neon_opcodes): Add bfloat SIMD instructions.
65 (print_insn_coprocessor): Add new control character %b to print
66 condition code without checking cp_num.
67 (print_insn_neon): Account for BFloat16 instructions that have no
68 special top-byte handling.
70 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
71 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
73 * arm-dis.c (print_insn_coprocessor,
74 print_insn_generic_coprocessor): Create wrapper functions around
75 the implementation of the print_insn_coprocessor control codes.
76 (print_insn_coprocessor_1): Original print_insn_coprocessor
77 function that now takes which array to look at as an argument.
78 (print_insn_arm): Use both print_insn_coprocessor and
79 print_insn_generic_coprocessor.
80 (print_insn_thumb32): As above.
82 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
83 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
85 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
86 in reglane special case.
87 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
88 aarch64_find_next_opcode): Account for new instructions.
89 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
90 in reglane special case.
91 * aarch64-opc.c (struct operand_qualifier_data): Add data for
92 new AARCH64_OPND_QLF_S_2H qualifier.
93 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
94 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
95 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
97 (BFLOAT_SVE, BFLOAT): New feature set macros.
98 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
100 (aarch64_opcode_table): Define new instructions bfdot,
101 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
104 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
105 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
107 * aarch64-tbl.h (ARMV8_6): New macro.
109 2019-11-07 Jan Beulich <jbeulich@suse.com>
111 * i386-dis.c (prefix_table): Add mcommit.
112 (rm_table): Add rdpru.
113 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
114 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
115 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
116 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
117 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
118 * i386-opc.tbl (mcommit, rdpru): New.
119 * i386-init.h, i386-tbl.h: Re-generate.
121 2019-11-07 Jan Beulich <jbeulich@suse.com>
123 * i386-dis.c (OP_Mwait): Drop local variable "names", use
125 (OP_Monitor): Drop local variable "op1_names", re-purpose
126 "names" for it instead, and replace former "names" uses by
129 2019-11-07 Jan Beulich <jbeulich@suse.com>
132 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
134 * opcodes/i386-tbl.h: Re-generate.
136 2019-11-05 Jan Beulich <jbeulich@suse.com>
138 * i386-dis.c (OP_Mwaitx): Delete.
139 (prefix_table): Use OP_Mwait for mwaitx entry.
140 (OP_Mwait): Also handle mwaitx.
142 2019-11-05 Jan Beulich <jbeulich@suse.com>
144 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
145 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
146 (prefix_table): Add respective entries.
147 (rm_table): Link to those entries.
149 2019-11-05 Jan Beulich <jbeulich@suse.com>
151 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
152 (REG_0F1C_P_0_MOD_0): ... this.
153 (REG_0F1E_MOD_3): Rename to ...
154 (REG_0F1E_P_1_MOD_3): ... this.
155 (RM_0F01_REG_5): Rename to ...
156 (RM_0F01_REG_5_MOD_3): ... this.
157 (RM_0F01_REG_7): Rename to ...
158 (RM_0F01_REG_7_MOD_3): ... this.
159 (RM_0F1E_MOD_3_REG_7): Rename to ...
160 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
161 (RM_0FAE_REG_6): Rename to ...
162 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
163 (RM_0FAE_REG_7): Rename to ...
164 (RM_0FAE_REG_7_MOD_3): ... this.
165 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
166 (PREFIX_0F01_REG_5_MOD_0): ... this.
167 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
168 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
169 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
170 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
171 (PREFIX_0FAE_REG_0): Rename to ...
172 (PREFIX_0FAE_REG_0_MOD_3): ... this.
173 (PREFIX_0FAE_REG_1): Rename to ...
174 (PREFIX_0FAE_REG_1_MOD_3): ... this.
175 (PREFIX_0FAE_REG_2): Rename to ...
176 (PREFIX_0FAE_REG_2_MOD_3): ... this.
177 (PREFIX_0FAE_REG_3): Rename to ...
178 (PREFIX_0FAE_REG_3_MOD_3): ... this.
179 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
180 (PREFIX_0FAE_REG_4_MOD_0): ... this.
181 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
182 (PREFIX_0FAE_REG_4_MOD_3): ... this.
183 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
184 (PREFIX_0FAE_REG_5_MOD_0): ... this.
185 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
186 (PREFIX_0FAE_REG_5_MOD_3): ... this.
187 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
188 (PREFIX_0FAE_REG_6_MOD_0): ... this.
189 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
190 (PREFIX_0FAE_REG_6_MOD_3): ... this.
191 (PREFIX_0FAE_REG_7): Rename to ...
192 (PREFIX_0FAE_REG_7_MOD_0): ... this.
193 (PREFIX_MOD_0_0FC3): Rename to ...
194 (PREFIX_0FC3_MOD_0): ... this.
195 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
196 (PREFIX_0FC7_REG_6_MOD_0): ... this.
197 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
198 (PREFIX_0FC7_REG_6_MOD_3): ... this.
199 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
200 (PREFIX_0FC7_REG_7_MOD_3): ... this.
201 (reg_table, prefix_table, mod_table, rm_table): Adjust
204 2019-11-04 Nick Clifton <nickc@redhat.com>
206 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
207 of a v850 system register. Move the v850_sreg_names array into
209 (get_v850_reg_name): Likewise for ordinary register names.
210 (get_v850_vreg_name): Likewise for vector register names.
211 (get_v850_cc_name): Likewise for condition codes.
212 * get_v850_float_cc_name): Likewise for floating point condition
214 (get_v850_cacheop_name): Likewise for cache-ops.
215 (get_v850_prefop_name): Likewise for pref-ops.
216 (disassemble): Use the new accessor functions.
218 2019-10-30 Delia Burduv <delia.burduv@arm.com>
220 * aarch64-opc.c (print_immediate_offset_address): Don't print the
221 immediate for the writeback form of ldraa/ldrab if it is 0.
222 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
223 * aarch64-opc-2.c: Regenerated.
225 2019-10-30 Jan Beulich <jbeulich@suse.com>
227 * i386-gen.c (operand_type_shorthands): Delete.
228 (operand_type_init): Expand previous shorthands.
229 (set_bitfield_from_shorthand): Rename back to ...
230 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
231 of operand_type_init[].
232 (set_bitfield): Adjust call to the above function.
233 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
234 RegXMM, RegYMM, RegZMM): Define.
235 * i386-reg.tbl: Expand prior shorthands.
237 2019-10-30 Jan Beulich <jbeulich@suse.com>
239 * i386-gen.c (output_i386_opcode): Change order of fields
241 * i386-opc.h (struct insn_template): Move operands field.
242 Convert extension_opcode field to unsigned short.
243 * i386-tbl.h: Re-generate.
245 2019-10-30 Jan Beulich <jbeulich@suse.com>
247 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
249 * i386-opc.h (W): Extend comment.
250 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
251 general purpose variants not allowing for byte operands.
252 * i386-tbl.h: Re-generate.
254 2019-10-29 Nick Clifton <nickc@redhat.com>
256 * tic30-dis.c (print_branch): Correct size of operand array.
258 2019-10-29 Nick Clifton <nickc@redhat.com>
260 * d30v-dis.c (print_insn): Check that operand index is valid
261 before attempting to access the operands array.
263 2019-10-29 Nick Clifton <nickc@redhat.com>
265 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
266 locating the bit to be tested.
268 2019-10-29 Nick Clifton <nickc@redhat.com>
270 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
272 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
273 (print_insn_s12z): Check for illegal size values.
275 2019-10-28 Nick Clifton <nickc@redhat.com>
277 * csky-dis.c (csky_chars_to_number): Check for a negative
278 count. Use an unsigned integer to construct the return value.
280 2019-10-28 Nick Clifton <nickc@redhat.com>
282 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
283 operand buffer. Set value to 15 not 13.
284 (get_register_operand): Use OPERAND_BUFFER_LEN.
285 (get_indirect_operand): Likewise.
286 (print_two_operand): Likewise.
287 (print_three_operand): Likewise.
288 (print_oar_insn): Likewise.
290 2019-10-28 Nick Clifton <nickc@redhat.com>
292 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
293 (bit_extract_simple): Likewise.
294 (bit_copy): Likewise.
295 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
296 index_offset array are not accessed.
298 2019-10-28 Nick Clifton <nickc@redhat.com>
300 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
303 2019-10-25 Nick Clifton <nickc@redhat.com>
305 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
306 access to opcodes.op array element.
308 2019-10-23 Nick Clifton <nickc@redhat.com>
310 * rx-dis.c (get_register_name): Fix spelling typo in error
312 (get_condition_name, get_flag_name, get_double_register_name)
313 (get_double_register_high_name, get_double_register_low_name)
314 (get_double_control_register_name, get_double_condition_name)
315 (get_opsize_name, get_size_name): Likewise.
317 2019-10-22 Nick Clifton <nickc@redhat.com>
319 * rx-dis.c (get_size_name): New function. Provides safe
320 access to name array.
321 (get_opsize_name): Likewise.
322 (print_insn_rx): Use the accessor functions.
324 2019-10-16 Nick Clifton <nickc@redhat.com>
326 * rx-dis.c (get_register_name): New function. Provides safe
327 access to name array.
328 (get_condition_name, get_flag_name, get_double_register_name)
329 (get_double_register_high_name, get_double_register_low_name)
330 (get_double_control_register_name, get_double_condition_name):
332 (print_insn_rx): Use the accessor functions.
334 2019-10-09 Nick Clifton <nickc@redhat.com>
337 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
340 2019-10-07 Jan Beulich <jbeulich@suse.com>
342 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
343 (cmpsd): Likewise. Move EsSeg to other operand.
344 * opcodes/i386-tbl.h: Re-generate.
346 2019-09-23 Alan Modra <amodra@gmail.com>
348 * m68k-dis.c: Include cpu-m68k.h
350 2019-09-23 Alan Modra <amodra@gmail.com>
352 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
353 "elf/mips.h" earlier.
355 2018-09-20 Jan Beulich <jbeulich@suse.com>
358 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
360 * i386-tbl.h: Re-generate.
362 2019-09-18 Alan Modra <amodra@gmail.com>
364 * arc-ext.c: Update throughout for bfd section macro changes.
366 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
368 * Makefile.in: Re-generate.
369 * configure: Re-generate.
371 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
373 * riscv-opc.c (riscv_opcodes): Change subset field
374 to insn_class field for all instructions.
375 (riscv_insn_types): Likewise.
377 2019-09-16 Phil Blundell <pb@pbcl.net>
379 * configure: Regenerated.
381 2019-09-10 Miod Vallat <miod@online.fr>
384 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
386 2019-09-09 Phil Blundell <pb@pbcl.net>
388 binutils 2.33 branch created.
390 2019-09-03 Nick Clifton <nickc@redhat.com>
393 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
394 greater than zero before indexing via (bufcnt -1).
396 2019-09-03 Nick Clifton <nickc@redhat.com>
399 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
400 (MAX_SPEC_REG_NAME_LEN): Define.
401 (struct mmix_dis_info): Use defined constants for array lengths.
402 (get_reg_name): New function.
403 (get_sprec_reg_name): New function.
404 (print_insn_mmix): Use new functions.
406 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
408 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
409 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
410 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
412 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
414 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
415 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
416 (aarch64_sys_reg_supported_p): Update checks for the above.
418 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
420 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
421 cases MVE_SQRSHRL and MVE_UQRSHLL.
422 (print_insn_mve): Add case for specifier 'k' to check
423 specific bit of the instruction.
425 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
428 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
429 encountering an unknown machine type.
430 (print_insn_arc): Handle arc_insn_length returning 0. In error
431 cases return -1 rather than calling abort.
433 2019-08-07 Jan Beulich <jbeulich@suse.com>
435 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
436 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
438 * i386-tbl.h: Re-generate.
440 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
442 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
445 2019-07-30 Mel Chen <mel.chen@sifive.com>
447 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
448 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
450 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
453 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
455 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
456 and MPY class instructions.
457 (parse_option): Add nps400 option.
458 (print_arc_disassembler_options): Add nps400 info.
460 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
462 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
465 * arc-opc.c (RAD_CHK): Add.
466 * arc-tbl.h: Regenerate.
468 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
470 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
471 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
473 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
475 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
476 instructions as UNPREDICTABLE.
478 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
480 * bpf-desc.c: Regenerated.
482 2019-07-17 Jan Beulich <jbeulich@suse.com>
484 * i386-gen.c (static_assert): Define.
486 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
487 (Opcode_Modifier_Num): ... this.
490 2019-07-16 Jan Beulich <jbeulich@suse.com>
492 * i386-gen.c (operand_types): Move RegMem ...
493 (opcode_modifiers): ... here.
494 * i386-opc.h (RegMem): Move to opcode modifer enum.
495 (union i386_operand_type): Move regmem field ...
496 (struct i386_opcode_modifier): ... here.
497 * i386-opc.tbl (RegMem): Define.
498 (mov, movq): Move RegMem on segment, control, debug, and test
500 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
501 to non-SSE2AVX flavor.
502 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
503 Move RegMem on register only flavors. Drop IgnoreSize from
504 legacy encoding flavors.
505 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
507 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
508 register only flavors.
509 (vmovd): Move RegMem and drop IgnoreSize on register only
510 flavor. Change opcode and operand order to store form.
511 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
513 2019-07-16 Jan Beulich <jbeulich@suse.com>
515 * i386-gen.c (operand_type_init, operand_types): Replace SReg
517 * i386-opc.h (SReg2, SReg3): Replace by ...
519 (union i386_operand_type): Replace sreg fields.
520 * i386-opc.tbl (mov, ): Use SReg.
521 (push, pop): Likewies. Drop i386 and x86-64 specific segment
523 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
524 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
526 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
528 * bpf-desc.c: Regenerate.
529 * bpf-opc.c: Likewise.
530 * bpf-opc.h: Likewise.
532 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
534 * bpf-desc.c: Regenerate.
535 * bpf-opc.c: Likewise.
537 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
539 * arm-dis.c (print_insn_coprocessor): Rename index to
542 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
544 * riscv-opc.c (riscv_insn_types): Add r4 type.
546 * riscv-opc.c (riscv_insn_types): Add b and j type.
548 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
549 format for sb type and correct s type.
551 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
553 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
554 SVE FMOV alias of FCPY.
556 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
558 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
559 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
561 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
563 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
564 registers in an instruction prefixed by MOVPRFX.
566 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
568 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
569 sve_size_13 icode to account for variant behaviour of
571 * aarch64-dis-2.c: Regenerate.
572 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
573 sve_size_13 icode to account for variant behaviour of
575 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
576 (OP_SVE_VVV_Q_D): Add new qualifier.
577 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
578 (struct aarch64_opcode): Split pmull{t,b} into those requiring
581 2019-07-01 Jan Beulich <jbeulich@suse.com>
583 * opcodes/i386-gen.c (operand_type_init): Remove
584 OPERAND_TYPE_VEC_IMM4 entry.
585 (operand_types): Remove Vec_Imm4.
586 * opcodes/i386-opc.h (Vec_Imm4): Delete.
587 (union i386_operand_type): Remove vec_imm4.
588 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
589 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
591 2019-07-01 Jan Beulich <jbeulich@suse.com>
593 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
594 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
595 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
596 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
597 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
598 monitorx, mwaitx): Drop ImmExt from operand-less forms.
599 * i386-tbl.h: Re-generate.
601 2019-07-01 Jan Beulich <jbeulich@suse.com>
603 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
605 * i386-tbl.h: Re-generate.
607 2019-07-01 Jan Beulich <jbeulich@suse.com>
609 * i386-opc.tbl (C): New.
610 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
611 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
612 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
613 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
614 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
615 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
616 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
617 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
618 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
619 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
620 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
621 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
622 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
623 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
624 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
625 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
626 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
627 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
628 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
629 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
630 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
631 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
632 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
633 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
634 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
635 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
637 * i386-tbl.h: Re-generate.
639 2019-07-01 Jan Beulich <jbeulich@suse.com>
641 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
643 * i386-tbl.h: Re-generate.
645 2019-07-01 Jan Beulich <jbeulich@suse.com>
647 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
648 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
649 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
650 * i386-tbl.h: Re-generate.
652 2019-07-01 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
655 Disp8MemShift from register only templates.
656 * i386-tbl.h: Re-generate.
658 2019-07-01 Jan Beulich <jbeulich@suse.com>
660 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
661 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
662 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
663 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
664 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
665 EVEX_W_0F11_P_3_M_1): Delete.
666 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
667 EVEX_W_0F11_P_3): New.
668 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
669 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
670 MOD_EVEX_0F11_PREFIX_3 table entries.
671 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
672 PREFIX_EVEX_0F11 table entries.
673 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
674 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
675 EVEX_W_0F11_P_3_M_{0,1} table entries.
677 2019-07-01 Jan Beulich <jbeulich@suse.com>
679 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
682 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
685 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
686 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
687 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
688 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
689 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
690 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
691 EVEX_LEN_0F38C7_R_6_P_2_W_1.
692 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
693 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
694 PREFIX_EVEX_0F38C6_REG_6 entries.
695 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
696 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
697 EVEX_W_0F38C7_R_6_P_2 entries.
698 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
699 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
700 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
701 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
702 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
703 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
704 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
706 2019-06-27 Jan Beulich <jbeulich@suse.com>
708 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
709 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
710 VEX_LEN_0F2D_P_3): Delete.
711 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
712 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
713 (prefix_table): ... here.
715 2019-06-27 Jan Beulich <jbeulich@suse.com>
717 * i386-dis.c (Iq): Delete.
719 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
721 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
722 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
723 (OP_E_memory): Also honor needindex when deciding whether an
724 address size prefix needs printing.
725 (OP_I): Remove handling of q_mode. Add handling of d_mode.
727 2019-06-26 Jim Wilson <jimw@sifive.com>
730 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
731 Set info->display_endian to info->endian_code.
733 2019-06-25 Jan Beulich <jbeulich@suse.com>
735 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
736 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
737 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
738 OPERAND_TYPE_ACC64 entries.
739 * i386-init.h: Re-generate.
741 2019-06-25 Jan Beulich <jbeulich@suse.com>
743 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
745 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
747 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
749 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
750 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
752 2019-06-25 Jan Beulich <jbeulich@suse.com>
754 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
757 2019-06-25 Jan Beulich <jbeulich@suse.com>
759 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
760 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
762 * i386-opc.tbl (movnti): Add IgnoreSize.
763 * i386-tbl.h: Re-generate.
765 2019-06-25 Jan Beulich <jbeulich@suse.com>
767 * i386-opc.tbl (and): Mark Imm8S form for optimization.
768 * i386-tbl.h: Re-generate.
770 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
772 * i386-dis-evex.h: Break into ...
773 * i386-dis-evex-len.h: New file.
774 * i386-dis-evex-mod.h: Likewise.
775 * i386-dis-evex-prefix.h: Likewise.
776 * i386-dis-evex-reg.h: Likewise.
777 * i386-dis-evex-w.h: Likewise.
778 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
779 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
782 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
785 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
786 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
788 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
789 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
790 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
791 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
792 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
793 EVEX_LEN_0F385B_P_2_W_1.
794 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
795 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
796 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
797 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
798 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
799 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
800 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
801 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
802 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
803 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
805 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
808 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
809 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
810 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
811 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
812 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
813 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
814 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
815 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
816 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
817 EVEX_LEN_0F3A43_P_2_W_1.
818 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
819 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
820 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
821 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
822 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
823 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
824 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
825 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
826 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
827 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
828 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
829 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
831 2019-06-14 Nick Clifton <nickc@redhat.com>
833 * po/fr.po; Updated French translation.
835 2019-06-13 Stafford Horne <shorne@gmail.com>
837 * or1k-asm.c: Regenerated.
838 * or1k-desc.c: Regenerated.
839 * or1k-desc.h: Regenerated.
840 * or1k-dis.c: Regenerated.
841 * or1k-ibld.c: Regenerated.
842 * or1k-opc.c: Regenerated.
843 * or1k-opc.h: Regenerated.
844 * or1k-opinst.c: Regenerated.
846 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
848 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
850 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
853 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
854 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
855 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
856 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
857 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
858 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
859 EVEX_LEN_0F3A1B_P_2_W_1.
860 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
861 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
862 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
863 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
864 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
865 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
866 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
867 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
869 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
872 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
873 EVEX.vvvv when disassembling VEX and EVEX instructions.
874 (OP_VEX): Set vex.register_specifier to 0 after readding
875 vex.register_specifier.
876 (OP_Vex_2src_1): Likewise.
877 (OP_Vex_2src_2): Likewise.
878 (OP_LWP_E): Likewise.
879 (OP_EX_Vex): Don't check vex.register_specifier.
880 (OP_XMM_Vex): Likewise.
882 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
883 Lili Cui <lili.cui@intel.com>
885 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
886 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
888 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
889 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
890 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
891 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
892 (i386_cpu_flags): Add cpuavx512_vp2intersect.
893 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
894 * i386-init.h: Regenerated.
895 * i386-tbl.h: Likewise.
897 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
898 Lili Cui <lili.cui@intel.com>
900 * doc/c-i386.texi: Document enqcmd.
901 * testsuite/gas/i386/enqcmd-intel.d: New file.
902 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
903 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
904 * testsuite/gas/i386/enqcmd.d: Likewise.
905 * testsuite/gas/i386/enqcmd.s: Likewise.
906 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
907 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
908 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
909 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
910 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
911 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
912 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
915 2019-06-04 Alan Hayward <alan.hayward@arm.com>
917 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
919 2019-06-03 Alan Modra <amodra@gmail.com>
921 * ppc-dis.c (prefix_opcd_indices): Correct size.
923 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
928 * i386-tbl.h: Regenerated.
930 2019-05-24 Alan Modra <amodra@gmail.com>
932 * po/POTFILES.in: Regenerate.
934 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
935 Alan Modra <amodra@gmail.com>
937 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
938 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
939 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
940 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
941 XTOP>): Define and add entries.
942 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
943 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
944 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
945 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
947 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
948 Alan Modra <amodra@gmail.com>
950 * ppc-dis.c (ppc_opts): Add "future" entry.
951 (PREFIX_OPCD_SEGS): Define.
952 (prefix_opcd_indices): New array.
953 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
954 (lookup_prefix): New function.
955 (print_insn_powerpc): Handle 64-bit prefix instructions.
956 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
957 (PMRR, POWERXX): Define.
958 (prefix_opcodes): New instruction table.
959 (prefix_num_opcodes): New constant.
961 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
963 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
964 * configure: Regenerated.
965 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
967 (HFILES): Add bpf-desc.h and bpf-opc.h.
968 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
969 bpf-ibld.c and bpf-opc.c.
971 * Makefile.in: Regenerated.
972 * disassemble.c (ARCH_bpf): Define.
973 (disassembler): Add case for bfd_arch_bpf.
974 (disassemble_init_for_target): Likewise.
975 (enum epbf_isa_attr): Define.
976 * disassemble.h: extern print_insn_bpf.
977 * bpf-asm.c: Generated.
978 * bpf-opc.h: Likewise.
979 * bpf-opc.c: Likewise.
980 * bpf-ibld.c: Likewise.
981 * bpf-dis.c: Likewise.
982 * bpf-desc.h: Likewise.
983 * bpf-desc.c: Likewise.
985 2019-05-21 Sudakshina Das <sudi.das@arm.com>
987 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
988 and VMSR with the new operands.
990 2019-05-21 Sudakshina Das <sudi.das@arm.com>
992 * arm-dis.c (enum mve_instructions): New enum
993 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
995 (mve_opcodes): New instructions as above.
996 (is_mve_encoding_conflict): Add cases for csinc, csinv,
998 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1000 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1002 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1003 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1004 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1005 uqshl, urshrl and urshr.
1006 (is_mve_okay_in_it): Add new instructions to TRUE list.
1007 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1008 (print_insn_mve): Updated to accept new %j,
1009 %<bitfield>m and %<bitfield>n patterns.
1011 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1013 * mips-opc.c (mips_builtin_opcodes): Change source register
1014 constraint for DAUI.
1016 2019-05-20 Nick Clifton <nickc@redhat.com>
1018 * po/fr.po: Updated French translation.
1020 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1021 Michael Collison <michael.collison@arm.com>
1023 * arm-dis.c (thumb32_opcodes): Add new instructions.
1024 (enum mve_instructions): Likewise.
1025 (enum mve_undefined): Add new reasons.
1026 (is_mve_encoding_conflict): Handle new instructions.
1027 (is_mve_undefined): Likewise.
1028 (is_mve_unpredictable): Likewise.
1029 (print_mve_undefined): Likewise.
1030 (print_mve_size): Likewise.
1032 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1033 Michael Collison <michael.collison@arm.com>
1035 * arm-dis.c (thumb32_opcodes): Add new instructions.
1036 (enum mve_instructions): Likewise.
1037 (is_mve_encoding_conflict): Handle new instructions.
1038 (is_mve_undefined): Likewise.
1039 (is_mve_unpredictable): Likewise.
1040 (print_mve_size): Likewise.
1042 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1043 Michael Collison <michael.collison@arm.com>
1045 * arm-dis.c (thumb32_opcodes): Add new instructions.
1046 (enum mve_instructions): Likewise.
1047 (is_mve_encoding_conflict): Likewise.
1048 (is_mve_unpredictable): Likewise.
1049 (print_mve_size): Likewise.
1051 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1052 Michael Collison <michael.collison@arm.com>
1054 * arm-dis.c (thumb32_opcodes): Add new instructions.
1055 (enum mve_instructions): Likewise.
1056 (is_mve_encoding_conflict): Handle new instructions.
1057 (is_mve_undefined): Likewise.
1058 (is_mve_unpredictable): Likewise.
1059 (print_mve_size): Likewise.
1061 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1062 Michael Collison <michael.collison@arm.com>
1064 * arm-dis.c (thumb32_opcodes): Add new instructions.
1065 (enum mve_instructions): Likewise.
1066 (is_mve_encoding_conflict): Handle new instructions.
1067 (is_mve_undefined): Likewise.
1068 (is_mve_unpredictable): Likewise.
1069 (print_mve_size): Likewise.
1070 (print_insn_mve): Likewise.
1072 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1073 Michael Collison <michael.collison@arm.com>
1075 * arm-dis.c (thumb32_opcodes): Add new instructions.
1076 (print_insn_thumb32): Handle new instructions.
1078 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1079 Michael Collison <michael.collison@arm.com>
1081 * arm-dis.c (enum mve_instructions): Add new instructions.
1082 (enum mve_undefined): Add new reasons.
1083 (is_mve_encoding_conflict): Handle new instructions.
1084 (is_mve_undefined): Likewise.
1085 (is_mve_unpredictable): Likewise.
1086 (print_mve_undefined): Likewise.
1087 (print_mve_size): Likewise.
1088 (print_mve_shift_n): Likewise.
1089 (print_insn_mve): Likewise.
1091 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1092 Michael Collison <michael.collison@arm.com>
1094 * arm-dis.c (enum mve_instructions): Add new instructions.
1095 (is_mve_encoding_conflict): Handle new instructions.
1096 (is_mve_unpredictable): Likewise.
1097 (print_mve_rotate): Likewise.
1098 (print_mve_size): Likewise.
1099 (print_insn_mve): Likewise.
1101 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1102 Michael Collison <michael.collison@arm.com>
1104 * arm-dis.c (enum mve_instructions): Add new instructions.
1105 (is_mve_encoding_conflict): Handle new instructions.
1106 (is_mve_unpredictable): Likewise.
1107 (print_mve_size): Likewise.
1108 (print_insn_mve): Likewise.
1110 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1111 Michael Collison <michael.collison@arm.com>
1113 * arm-dis.c (enum mve_instructions): Add new instructions.
1114 (enum mve_undefined): Add new reasons.
1115 (is_mve_encoding_conflict): Handle new instructions.
1116 (is_mve_undefined): Likewise.
1117 (is_mve_unpredictable): Likewise.
1118 (print_mve_undefined): Likewise.
1119 (print_mve_size): Likewise.
1120 (print_insn_mve): Likewise.
1122 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1123 Michael Collison <michael.collison@arm.com>
1125 * arm-dis.c (enum mve_instructions): Add new instructions.
1126 (is_mve_encoding_conflict): Handle new instructions.
1127 (is_mve_undefined): Likewise.
1128 (is_mve_unpredictable): Likewise.
1129 (print_mve_size): Likewise.
1130 (print_insn_mve): Likewise.
1132 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1133 Michael Collison <michael.collison@arm.com>
1135 * arm-dis.c (enum mve_instructions): Add new instructions.
1136 (enum mve_unpredictable): Add new reasons.
1137 (enum mve_undefined): Likewise.
1138 (is_mve_okay_in_it): Handle new isntructions.
1139 (is_mve_encoding_conflict): Likewise.
1140 (is_mve_undefined): Likewise.
1141 (is_mve_unpredictable): Likewise.
1142 (print_mve_vmov_index): Likewise.
1143 (print_simd_imm8): Likewise.
1144 (print_mve_undefined): Likewise.
1145 (print_mve_unpredictable): Likewise.
1146 (print_mve_size): Likewise.
1147 (print_insn_mve): Likewise.
1149 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1150 Michael Collison <michael.collison@arm.com>
1152 * arm-dis.c (enum mve_instructions): Add new instructions.
1153 (enum mve_unpredictable): Add new reasons.
1154 (enum mve_undefined): Likewise.
1155 (is_mve_encoding_conflict): Handle new instructions.
1156 (is_mve_undefined): Likewise.
1157 (is_mve_unpredictable): Likewise.
1158 (print_mve_undefined): Likewise.
1159 (print_mve_unpredictable): Likewise.
1160 (print_mve_rounding_mode): Likewise.
1161 (print_mve_vcvt_size): Likewise.
1162 (print_mve_size): Likewise.
1163 (print_insn_mve): Likewise.
1165 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1166 Michael Collison <michael.collison@arm.com>
1168 * arm-dis.c (enum mve_instructions): Add new instructions.
1169 (enum mve_unpredictable): Add new reasons.
1170 (enum mve_undefined): Likewise.
1171 (is_mve_undefined): Handle new instructions.
1172 (is_mve_unpredictable): Likewise.
1173 (print_mve_undefined): Likewise.
1174 (print_mve_unpredictable): Likewise.
1175 (print_mve_size): Likewise.
1176 (print_insn_mve): Likewise.
1178 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1179 Michael Collison <michael.collison@arm.com>
1181 * arm-dis.c (enum mve_instructions): Add new instructions.
1182 (enum mve_undefined): Add new reasons.
1183 (insns): Add new instructions.
1184 (is_mve_encoding_conflict):
1185 (print_mve_vld_str_addr): New print function.
1186 (is_mve_undefined): Handle new instructions.
1187 (is_mve_unpredictable): Likewise.
1188 (print_mve_undefined): Likewise.
1189 (print_mve_size): Likewise.
1190 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1191 (print_insn_mve): Handle new operands.
1193 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1194 Michael Collison <michael.collison@arm.com>
1196 * arm-dis.c (enum mve_instructions): Add new instructions.
1197 (enum mve_unpredictable): Add new reasons.
1198 (is_mve_encoding_conflict): Handle new instructions.
1199 (is_mve_unpredictable): Likewise.
1200 (mve_opcodes): Add new instructions.
1201 (print_mve_unpredictable): Handle new reasons.
1202 (print_mve_register_blocks): New print function.
1203 (print_mve_size): Handle new instructions.
1204 (print_insn_mve): Likewise.
1206 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1207 Michael Collison <michael.collison@arm.com>
1209 * arm-dis.c (enum mve_instructions): Add new instructions.
1210 (enum mve_unpredictable): Add new reasons.
1211 (enum mve_undefined): Likewise.
1212 (is_mve_encoding_conflict): Handle new instructions.
1213 (is_mve_undefined): Likewise.
1214 (is_mve_unpredictable): Likewise.
1215 (coprocessor_opcodes): Move NEON VDUP from here...
1216 (neon_opcodes): ... to here.
1217 (mve_opcodes): Add new instructions.
1218 (print_mve_undefined): Handle new reasons.
1219 (print_mve_unpredictable): Likewise.
1220 (print_mve_size): Handle new instructions.
1221 (print_insn_neon): Handle vdup.
1222 (print_insn_mve): Handle new operands.
1224 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1225 Michael Collison <michael.collison@arm.com>
1227 * arm-dis.c (enum mve_instructions): Add new instructions.
1228 (enum mve_unpredictable): Add new values.
1229 (mve_opcodes): Add new instructions.
1230 (vec_condnames): New array with vector conditions.
1231 (mve_predicatenames): New array with predicate suffixes.
1232 (mve_vec_sizename): New array with vector sizes.
1233 (enum vpt_pred_state): New enum with vector predication states.
1234 (struct vpt_block): New struct type for vpt blocks.
1235 (vpt_block_state): Global struct to keep track of state.
1236 (mve_extract_pred_mask): New helper function.
1237 (num_instructions_vpt_block): Likewise.
1238 (mark_outside_vpt_block): Likewise.
1239 (mark_inside_vpt_block): Likewise.
1240 (invert_next_predicate_state): Likewise.
1241 (update_next_predicate_state): Likewise.
1242 (update_vpt_block_state): Likewise.
1243 (is_vpt_instruction): Likewise.
1244 (is_mve_encoding_conflict): Add entries for new instructions.
1245 (is_mve_unpredictable): Likewise.
1246 (print_mve_unpredictable): Handle new cases.
1247 (print_instruction_predicate): Likewise.
1248 (print_mve_size): New function.
1249 (print_vec_condition): New function.
1250 (print_insn_mve): Handle vpt blocks and new print operands.
1252 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1254 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1255 8, 14 and 15 for Armv8.1-M Mainline.
1257 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1258 Michael Collison <michael.collison@arm.com>
1260 * arm-dis.c (enum mve_instructions): New enum.
1261 (enum mve_unpredictable): Likewise.
1262 (enum mve_undefined): Likewise.
1263 (struct mopcode32): New struct.
1264 (is_mve_okay_in_it): New function.
1265 (is_mve_architecture): Likewise.
1266 (arm_decode_field): Likewise.
1267 (arm_decode_field_multiple): Likewise.
1268 (is_mve_encoding_conflict): Likewise.
1269 (is_mve_undefined): Likewise.
1270 (is_mve_unpredictable): Likewise.
1271 (print_mve_undefined): Likewise.
1272 (print_mve_unpredictable): Likewise.
1273 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1274 (print_insn_mve): New function.
1275 (print_insn_thumb32): Handle MVE architecture.
1276 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1278 2019-05-10 Nick Clifton <nickc@redhat.com>
1281 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1282 end of the table prematurely.
1284 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1286 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1289 2019-05-11 Alan Modra <amodra@gmail.com>
1291 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1292 when -Mraw is in effect.
1294 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1296 * aarch64-dis-2.c: Regenerate.
1297 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1298 (OP_SVE_BBB): New variant set.
1299 (OP_SVE_DDDD): New variant set.
1300 (OP_SVE_HHH): New variant set.
1301 (OP_SVE_HHHU): New variant set.
1302 (OP_SVE_SSS): New variant set.
1303 (OP_SVE_SSSU): New variant set.
1304 (OP_SVE_SHH): New variant set.
1305 (OP_SVE_SBBU): New variant set.
1306 (OP_SVE_DSS): New variant set.
1307 (OP_SVE_DHHU): New variant set.
1308 (OP_SVE_VMV_HSD_BHS): New variant set.
1309 (OP_SVE_VVU_HSD_BHS): New variant set.
1310 (OP_SVE_VVVU_SD_BH): New variant set.
1311 (OP_SVE_VVVU_BHSD): New variant set.
1312 (OP_SVE_VVV_QHD_DBS): New variant set.
1313 (OP_SVE_VVV_HSD_BHS): New variant set.
1314 (OP_SVE_VVV_HSD_BHS2): New variant set.
1315 (OP_SVE_VVV_BHS_HSD): New variant set.
1316 (OP_SVE_VV_BHS_HSD): New variant set.
1317 (OP_SVE_VVV_SD): New variant set.
1318 (OP_SVE_VVU_BHS_HSD): New variant set.
1319 (OP_SVE_VZVV_SD): New variant set.
1320 (OP_SVE_VZVV_BH): New variant set.
1321 (OP_SVE_VZV_SD): New variant set.
1322 (aarch64_opcode_table): Add sve2 instructions.
1324 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1326 * aarch64-asm-2.c: Regenerated.
1327 * aarch64-dis-2.c: Regenerated.
1328 * aarch64-opc-2.c: Regenerated.
1329 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1330 for SVE_SHLIMM_UNPRED_22.
1331 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1332 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1335 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1337 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1338 sve_size_tsz_bhs iclass encode.
1339 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1340 sve_size_tsz_bhs iclass decode.
1342 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1344 * aarch64-asm-2.c: Regenerated.
1345 * aarch64-dis-2.c: Regenerated.
1346 * aarch64-opc-2.c: Regenerated.
1347 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1348 for SVE_Zm4_11_INDEX.
1349 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1350 (fields): Handle SVE_i2h field.
1351 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1352 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1354 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1356 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1357 sve_shift_tsz_bhsd iclass encode.
1358 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1359 sve_shift_tsz_bhsd iclass decode.
1361 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1363 * aarch64-asm-2.c: Regenerated.
1364 * aarch64-dis-2.c: Regenerated.
1365 * aarch64-opc-2.c: Regenerated.
1366 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1367 (aarch64_encode_variant_using_iclass): Handle
1368 sve_shift_tsz_hsd iclass encode.
1369 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1370 sve_shift_tsz_hsd iclass decode.
1371 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1372 for SVE_SHRIMM_UNPRED_22.
1373 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1374 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1377 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1379 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1380 sve_size_013 iclass encode.
1381 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1382 sve_size_013 iclass decode.
1384 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1386 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1387 sve_size_bh iclass encode.
1388 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1389 sve_size_bh iclass decode.
1391 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1393 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1394 sve_size_sd2 iclass encode.
1395 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1396 sve_size_sd2 iclass decode.
1397 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1398 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1400 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1402 * aarch64-asm-2.c: Regenerated.
1403 * aarch64-dis-2.c: Regenerated.
1404 * aarch64-opc-2.c: Regenerated.
1405 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1407 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1408 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1410 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1412 * aarch64-asm-2.c: Regenerated.
1413 * aarch64-dis-2.c: Regenerated.
1414 * aarch64-opc-2.c: Regenerated.
1415 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1416 for SVE_Zm3_11_INDEX.
1417 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1418 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1419 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1421 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1423 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1425 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1426 sve_size_hsd2 iclass encode.
1427 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1428 sve_size_hsd2 iclass decode.
1429 * aarch64-opc.c (fields): Handle SVE_size field.
1430 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1432 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1434 * aarch64-asm-2.c: Regenerated.
1435 * aarch64-dis-2.c: Regenerated.
1436 * aarch64-opc-2.c: Regenerated.
1437 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1439 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1440 (fields): Handle SVE_rot3 field.
1441 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1442 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1444 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1446 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1449 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1452 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1453 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1454 aarch64_feature_sve2bitperm): New feature sets.
1455 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1456 for feature set addresses.
1457 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1458 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1460 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1461 Faraz Shahbazker <fshahbazker@wavecomp.com>
1463 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1464 argument and set ASE_EVA_R6 appropriately.
1465 (set_default_mips_dis_options): Pass ISA to above.
1466 (parse_mips_dis_option): Likewise.
1467 * mips-opc.c (EVAR6): New macro.
1468 (mips_builtin_opcodes): Add llwpe, scwpe.
1470 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1472 * aarch64-asm-2.c: Regenerated.
1473 * aarch64-dis-2.c: Regenerated.
1474 * aarch64-opc-2.c: Regenerated.
1475 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1476 AARCH64_OPND_TME_UIMM16.
1477 (aarch64_print_operand): Likewise.
1478 * aarch64-tbl.h (QL_IMM_NIL): New.
1481 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1483 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1485 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1487 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1488 Faraz Shahbazker <fshahbazker@wavecomp.com>
1490 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1492 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1494 * s12z-opc.h: Add extern "C" bracketing to help
1495 users who wish to use this interface in c++ code.
1497 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1499 * s12z-opc.c (bm_decode): Handle bit map operations with the
1502 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1504 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1505 specifier. Add entries for VLDR and VSTR of system registers.
1506 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1507 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1508 of %J and %K format specifier.
1510 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1512 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1513 Add new entries for VSCCLRM instruction.
1514 (print_insn_coprocessor): Handle new %C format control code.
1516 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1518 * arm-dis.c (enum isa): New enum.
1519 (struct sopcode32): New structure.
1520 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1521 set isa field of all current entries to ANY.
1522 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1523 Only match an entry if its isa field allows the current mode.
1525 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1527 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1529 (print_insn_thumb32): Add logic to print %n CLRM register list.
1531 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1533 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1536 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1538 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1539 (print_insn_thumb32): Edit the switch case for %Z.
1541 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1543 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1545 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1547 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1549 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1551 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1553 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1555 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1556 Arm register with r13 and r15 unpredictable.
1557 (thumb32_opcodes): New instructions for bfx and bflx.
1559 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1561 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1563 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1565 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1567 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1569 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1571 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1573 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1575 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1577 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1578 "optr". ("operator" is a reserved word in c++).
1580 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1582 * aarch64-opc.c (aarch64_print_operand): Add case for
1584 (verify_constraints): Likewise.
1585 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1586 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1587 to accept Rt|SP as first operand.
1588 (AARCH64_OPERANDS): Add new Rt_SP.
1589 * aarch64-asm-2.c: Regenerated.
1590 * aarch64-dis-2.c: Regenerated.
1591 * aarch64-opc-2.c: Regenerated.
1593 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1595 * aarch64-asm-2.c: Regenerated.
1596 * aarch64-dis-2.c: Likewise.
1597 * aarch64-opc-2.c: Likewise.
1598 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1600 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1602 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1604 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1606 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1607 * i386-init.h: Regenerated.
1609 2019-04-07 Alan Modra <amodra@gmail.com>
1611 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1612 op_separator to control printing of spaces, comma and parens
1613 rather than need_comma, need_paren and spaces vars.
1615 2019-04-07 Alan Modra <amodra@gmail.com>
1618 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1619 (print_insn_neon, print_insn_arm): Likewise.
1621 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1623 * i386-dis-evex.h (evex_table): Updated to support BF16
1625 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1626 and EVEX_W_0F3872_P_3.
1627 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1628 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1629 * i386-opc.h (enum): Add CpuAVX512_BF16.
1630 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1631 * i386-opc.tbl: Add AVX512 BF16 instructions.
1632 * i386-init.h: Regenerated.
1633 * i386-tbl.h: Likewise.
1635 2019-04-05 Alan Modra <amodra@gmail.com>
1637 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1638 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1639 to favour printing of "-" branch hint when using the "y" bit.
1640 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1642 2019-04-05 Alan Modra <amodra@gmail.com>
1644 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1645 opcode until first operand is output.
1647 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1650 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1651 (valid_bo_post_v2): Add support for 'at' branch hints.
1652 (insert_bo): Only error on branch on ctr.
1653 (get_bo_hint_mask): New function.
1654 (insert_boe): Add new 'branch_taken' formal argument. Add support
1655 for inserting 'at' branch hints.
1656 (extract_boe): Add new 'branch_taken' formal argument. Add support
1657 for extracting 'at' branch hints.
1658 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1659 (BOE): Delete operand.
1660 (BOM, BOP): New operands.
1662 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1663 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1664 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1665 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1666 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1667 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1668 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1669 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1670 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1671 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1672 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1673 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1674 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1675 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1676 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1677 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1678 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1679 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1680 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1681 bttarl+>: New extended mnemonics.
1683 2019-03-28 Alan Modra <amodra@gmail.com>
1686 * ppc-opc.c (BTF): Define.
1687 (powerpc_opcodes): Use for mtfsb*.
1688 * ppc-dis.c (print_insn_powerpc): Print fields with both
1689 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1691 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1693 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1694 (mapping_symbol_for_insn): Implement new algorithm.
1695 (print_insn): Remove duplicate code.
1697 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1699 * aarch64-dis.c (print_insn_aarch64):
1702 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1704 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1707 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1709 * aarch64-dis.c (last_stop_offset): New.
1710 (print_insn_aarch64): Use stop_offset.
1712 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1715 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1717 * i386-init.h: Regenerated.
1719 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1722 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1723 vmovdqu16, vmovdqu32 and vmovdqu64.
1724 * i386-tbl.h: Regenerated.
1726 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1728 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1729 from vstrszb, vstrszh, and vstrszf.
1731 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1733 * s390-opc.txt: Add instruction descriptions.
1735 2019-02-08 Jim Wilson <jimw@sifive.com>
1737 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1740 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1742 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1744 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1747 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1748 * aarch64-opc.c (verify_elem_sd): New.
1749 (fields): Add FLD_sz entr.
1750 * aarch64-tbl.h (_SIMD_INSN): New.
1751 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1752 fmulx scalar and vector by element isns.
1754 2019-02-07 Nick Clifton <nickc@redhat.com>
1756 * po/sv.po: Updated Swedish translation.
1758 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1760 * s390-mkopc.c (main): Accept arch13 as cpu string.
1761 * s390-opc.c: Add new instruction formats and instruction opcode
1763 * s390-opc.txt: Add new arch13 instructions.
1765 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1767 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1768 (aarch64_opcode): Change encoding for stg, stzg
1770 * aarch64-asm-2.c: Regenerated.
1771 * aarch64-dis-2.c: Regenerated.
1772 * aarch64-opc-2.c: Regenerated.
1774 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1776 * aarch64-asm-2.c: Regenerated.
1777 * aarch64-dis-2.c: Likewise.
1778 * aarch64-opc-2.c: Likewise.
1779 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1781 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1782 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1784 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1785 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1786 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1787 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1788 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1789 case for ldstgv_indexed.
1790 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1791 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1792 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1793 * aarch64-asm-2.c: Regenerated.
1794 * aarch64-dis-2.c: Regenerated.
1795 * aarch64-opc-2.c: Regenerated.
1797 2019-01-23 Nick Clifton <nickc@redhat.com>
1799 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1801 2019-01-21 Nick Clifton <nickc@redhat.com>
1803 * po/de.po: Updated German translation.
1804 * po/uk.po: Updated Ukranian translation.
1806 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1807 * mips-dis.c (mips_arch_choices): Fix typo in
1808 gs464, gs464e and gs264e descriptors.
1810 2019-01-19 Nick Clifton <nickc@redhat.com>
1812 * configure: Regenerate.
1813 * po/opcodes.pot: Regenerate.
1815 2018-06-24 Nick Clifton <nickc@redhat.com>
1817 2.32 branch created.
1819 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1821 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1823 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1826 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1828 * configure: Regenerate.
1830 2019-01-07 Alan Modra <amodra@gmail.com>
1832 * configure: Regenerate.
1833 * po/POTFILES.in: Regenerate.
1835 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1837 * s12z-opc.c: New file.
1838 * s12z-opc.h: New file.
1839 * s12z-dis.c: Removed all code not directly related to display
1840 of instructions. Used the interface provided by the new files
1842 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1843 * Makefile.in: Regenerate.
1844 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1845 * configure: Regenerate.
1847 2019-01-01 Alan Modra <amodra@gmail.com>
1849 Update year range in copyright notice of all files.
1851 For older changes see ChangeLog-2018
1853 Copyright (C) 2019 Free Software Foundation, Inc.
1855 Copying and distribution of this file, with or without modification,
1856 are permitted in any medium without royalty provided the copyright
1857 notice and this notice are preserved.
1863 version-control: never