1 2019-10-16 Nick Clifton <nickc@redhat.com>
3 * rx-dis.c (get_register_name): New function. Provides safe
5 (get_condition_name, get_flag_name, get_double_register_name)
6 (get_double_register_high_name, get_double_register_low_name)
7 (get_double_control_register_name, get_double_condition_name):
9 (print_insn_rx): Use the accessor functions.
11 2019-10-09 Nick Clifton <nickc@redhat.com>
14 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
17 2019-10-07 Jan Beulich <jbeulich@suse.com>
19 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
20 (cmpsd): Likewise. Move EsSeg to other operand.
21 * opcodes/i386-tbl.h: Re-generate.
23 2019-09-23 Alan Modra <amodra@gmail.com>
25 * m68k-dis.c: Include cpu-m68k.h
27 2019-09-23 Alan Modra <amodra@gmail.com>
29 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
32 2018-09-20 Jan Beulich <jbeulich@suse.com>
35 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
37 * i386-tbl.h: Re-generate.
39 2019-09-18 Alan Modra <amodra@gmail.com>
41 * arc-ext.c: Update throughout for bfd section macro changes.
43 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
45 * Makefile.in: Re-generate.
46 * configure: Re-generate.
48 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
50 * riscv-opc.c (riscv_opcodes): Change subset field
51 to insn_class field for all instructions.
52 (riscv_insn_types): Likewise.
54 2019-09-16 Phil Blundell <pb@pbcl.net>
56 * configure: Regenerated.
58 2019-09-10 Miod Vallat <miod@online.fr>
61 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
63 2019-09-09 Phil Blundell <pb@pbcl.net>
65 binutils 2.33 branch created.
67 2019-09-03 Nick Clifton <nickc@redhat.com>
70 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
71 greater than zero before indexing via (bufcnt -1).
73 2019-09-03 Nick Clifton <nickc@redhat.com>
76 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
77 (MAX_SPEC_REG_NAME_LEN): Define.
78 (struct mmix_dis_info): Use defined constants for array lengths.
79 (get_reg_name): New function.
80 (get_sprec_reg_name): New function.
81 (print_insn_mmix): Use new functions.
83 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
85 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
86 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
87 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
89 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
91 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
92 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
93 (aarch64_sys_reg_supported_p): Update checks for the above.
95 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
97 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
98 cases MVE_SQRSHRL and MVE_UQRSHLL.
99 (print_insn_mve): Add case for specifier 'k' to check
100 specific bit of the instruction.
102 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
105 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
106 encountering an unknown machine type.
107 (print_insn_arc): Handle arc_insn_length returning 0. In error
108 cases return -1 rather than calling abort.
110 2019-08-07 Jan Beulich <jbeulich@suse.com>
112 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
113 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
115 * i386-tbl.h: Re-generate.
117 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
119 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
122 2019-07-30 Mel Chen <mel.chen@sifive.com>
124 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
125 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
127 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
130 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
132 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
133 and MPY class instructions.
134 (parse_option): Add nps400 option.
135 (print_arc_disassembler_options): Add nps400 info.
137 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
139 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
142 * arc-opc.c (RAD_CHK): Add.
143 * arc-tbl.h: Regenerate.
145 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
147 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
148 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
150 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
152 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
153 instructions as UNPREDICTABLE.
155 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
157 * bpf-desc.c: Regenerated.
159 2019-07-17 Jan Beulich <jbeulich@suse.com>
161 * i386-gen.c (static_assert): Define.
163 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
164 (Opcode_Modifier_Num): ... this.
167 2019-07-16 Jan Beulich <jbeulich@suse.com>
169 * i386-gen.c (operand_types): Move RegMem ...
170 (opcode_modifiers): ... here.
171 * i386-opc.h (RegMem): Move to opcode modifer enum.
172 (union i386_operand_type): Move regmem field ...
173 (struct i386_opcode_modifier): ... here.
174 * i386-opc.tbl (RegMem): Define.
175 (mov, movq): Move RegMem on segment, control, debug, and test
177 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
178 to non-SSE2AVX flavor.
179 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
180 Move RegMem on register only flavors. Drop IgnoreSize from
181 legacy encoding flavors.
182 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
184 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
185 register only flavors.
186 (vmovd): Move RegMem and drop IgnoreSize on register only
187 flavor. Change opcode and operand order to store form.
188 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
190 2019-07-16 Jan Beulich <jbeulich@suse.com>
192 * i386-gen.c (operand_type_init, operand_types): Replace SReg
194 * i386-opc.h (SReg2, SReg3): Replace by ...
196 (union i386_operand_type): Replace sreg fields.
197 * i386-opc.tbl (mov, ): Use SReg.
198 (push, pop): Likewies. Drop i386 and x86-64 specific segment
200 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
201 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
203 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
205 * bpf-desc.c: Regenerate.
206 * bpf-opc.c: Likewise.
207 * bpf-opc.h: Likewise.
209 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
211 * bpf-desc.c: Regenerate.
212 * bpf-opc.c: Likewise.
214 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
216 * arm-dis.c (print_insn_coprocessor): Rename index to
219 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
221 * riscv-opc.c (riscv_insn_types): Add r4 type.
223 * riscv-opc.c (riscv_insn_types): Add b and j type.
225 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
226 format for sb type and correct s type.
228 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
230 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
231 SVE FMOV alias of FCPY.
233 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
235 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
236 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
238 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
240 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
241 registers in an instruction prefixed by MOVPRFX.
243 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
245 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
246 sve_size_13 icode to account for variant behaviour of
248 * aarch64-dis-2.c: Regenerate.
249 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
250 sve_size_13 icode to account for variant behaviour of
252 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
253 (OP_SVE_VVV_Q_D): Add new qualifier.
254 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
255 (struct aarch64_opcode): Split pmull{t,b} into those requiring
258 2019-07-01 Jan Beulich <jbeulich@suse.com>
260 * opcodes/i386-gen.c (operand_type_init): Remove
261 OPERAND_TYPE_VEC_IMM4 entry.
262 (operand_types): Remove Vec_Imm4.
263 * opcodes/i386-opc.h (Vec_Imm4): Delete.
264 (union i386_operand_type): Remove vec_imm4.
265 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
266 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
268 2019-07-01 Jan Beulich <jbeulich@suse.com>
270 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
271 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
272 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
273 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
274 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
275 monitorx, mwaitx): Drop ImmExt from operand-less forms.
276 * i386-tbl.h: Re-generate.
278 2019-07-01 Jan Beulich <jbeulich@suse.com>
280 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
282 * i386-tbl.h: Re-generate.
284 2019-07-01 Jan Beulich <jbeulich@suse.com>
286 * i386-opc.tbl (C): New.
287 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
288 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
289 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
290 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
291 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
292 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
293 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
294 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
295 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
296 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
297 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
298 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
299 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
300 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
301 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
302 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
303 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
304 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
305 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
306 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
307 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
308 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
309 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
310 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
311 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
312 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
314 * i386-tbl.h: Re-generate.
316 2019-07-01 Jan Beulich <jbeulich@suse.com>
318 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
320 * i386-tbl.h: Re-generate.
322 2019-07-01 Jan Beulich <jbeulich@suse.com>
324 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
325 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
326 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
327 * i386-tbl.h: Re-generate.
329 2019-07-01 Jan Beulich <jbeulich@suse.com>
331 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
332 Disp8MemShift from register only templates.
333 * i386-tbl.h: Re-generate.
335 2019-07-01 Jan Beulich <jbeulich@suse.com>
337 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
338 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
339 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
340 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
341 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
342 EVEX_W_0F11_P_3_M_1): Delete.
343 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
344 EVEX_W_0F11_P_3): New.
345 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
346 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
347 MOD_EVEX_0F11_PREFIX_3 table entries.
348 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
349 PREFIX_EVEX_0F11 table entries.
350 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
351 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
352 EVEX_W_0F11_P_3_M_{0,1} table entries.
354 2019-07-01 Jan Beulich <jbeulich@suse.com>
356 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
359 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
362 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
363 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
364 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
365 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
366 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
367 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
368 EVEX_LEN_0F38C7_R_6_P_2_W_1.
369 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
370 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
371 PREFIX_EVEX_0F38C6_REG_6 entries.
372 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
373 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
374 EVEX_W_0F38C7_R_6_P_2 entries.
375 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
376 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
377 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
378 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
379 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
380 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
381 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
383 2019-06-27 Jan Beulich <jbeulich@suse.com>
385 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
386 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
387 VEX_LEN_0F2D_P_3): Delete.
388 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
389 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
390 (prefix_table): ... here.
392 2019-06-27 Jan Beulich <jbeulich@suse.com>
394 * i386-dis.c (Iq): Delete.
396 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
398 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
399 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
400 (OP_E_memory): Also honor needindex when deciding whether an
401 address size prefix needs printing.
402 (OP_I): Remove handling of q_mode. Add handling of d_mode.
404 2019-06-26 Jim Wilson <jimw@sifive.com>
407 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
408 Set info->display_endian to info->endian_code.
410 2019-06-25 Jan Beulich <jbeulich@suse.com>
412 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
413 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
414 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
415 OPERAND_TYPE_ACC64 entries.
416 * i386-init.h: Re-generate.
418 2019-06-25 Jan Beulich <jbeulich@suse.com>
420 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
422 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
424 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
426 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
427 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
429 2019-06-25 Jan Beulich <jbeulich@suse.com>
431 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
434 2019-06-25 Jan Beulich <jbeulich@suse.com>
436 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
437 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
439 * i386-opc.tbl (movnti): Add IgnoreSize.
440 * i386-tbl.h: Re-generate.
442 2019-06-25 Jan Beulich <jbeulich@suse.com>
444 * i386-opc.tbl (and): Mark Imm8S form for optimization.
445 * i386-tbl.h: Re-generate.
447 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-dis-evex.h: Break into ...
450 * i386-dis-evex-len.h: New file.
451 * i386-dis-evex-mod.h: Likewise.
452 * i386-dis-evex-prefix.h: Likewise.
453 * i386-dis-evex-reg.h: Likewise.
454 * i386-dis-evex-w.h: Likewise.
455 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
456 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
459 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
462 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
463 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
465 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
466 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
467 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
468 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
469 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
470 EVEX_LEN_0F385B_P_2_W_1.
471 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
472 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
473 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
474 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
475 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
476 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
477 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
478 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
479 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
480 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
482 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
485 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
486 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
487 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
488 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
489 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
490 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
491 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
492 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
493 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
494 EVEX_LEN_0F3A43_P_2_W_1.
495 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
496 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
497 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
498 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
499 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
500 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
501 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
502 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
503 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
504 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
505 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
506 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
508 2019-06-14 Nick Clifton <nickc@redhat.com>
510 * po/fr.po; Updated French translation.
512 2019-06-13 Stafford Horne <shorne@gmail.com>
514 * or1k-asm.c: Regenerated.
515 * or1k-desc.c: Regenerated.
516 * or1k-desc.h: Regenerated.
517 * or1k-dis.c: Regenerated.
518 * or1k-ibld.c: Regenerated.
519 * or1k-opc.c: Regenerated.
520 * or1k-opc.h: Regenerated.
521 * or1k-opinst.c: Regenerated.
523 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
525 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
527 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
531 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
532 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
533 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
534 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
535 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
536 EVEX_LEN_0F3A1B_P_2_W_1.
537 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
538 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
539 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
540 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
541 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
542 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
543 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
544 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
546 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
549 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
550 EVEX.vvvv when disassembling VEX and EVEX instructions.
551 (OP_VEX): Set vex.register_specifier to 0 after readding
552 vex.register_specifier.
553 (OP_Vex_2src_1): Likewise.
554 (OP_Vex_2src_2): Likewise.
555 (OP_LWP_E): Likewise.
556 (OP_EX_Vex): Don't check vex.register_specifier.
557 (OP_XMM_Vex): Likewise.
559 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
560 Lili Cui <lili.cui@intel.com>
562 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
563 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
565 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
566 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
567 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
568 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
569 (i386_cpu_flags): Add cpuavx512_vp2intersect.
570 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
571 * i386-init.h: Regenerated.
572 * i386-tbl.h: Likewise.
574 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
575 Lili Cui <lili.cui@intel.com>
577 * doc/c-i386.texi: Document enqcmd.
578 * testsuite/gas/i386/enqcmd-intel.d: New file.
579 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
580 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
581 * testsuite/gas/i386/enqcmd.d: Likewise.
582 * testsuite/gas/i386/enqcmd.s: Likewise.
583 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
584 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
585 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
586 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
587 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
588 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
589 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
592 2019-06-04 Alan Hayward <alan.hayward@arm.com>
594 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
596 2019-06-03 Alan Modra <amodra@gmail.com>
598 * ppc-dis.c (prefix_opcd_indices): Correct size.
600 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
603 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
605 * i386-tbl.h: Regenerated.
607 2019-05-24 Alan Modra <amodra@gmail.com>
609 * po/POTFILES.in: Regenerate.
611 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
612 Alan Modra <amodra@gmail.com>
614 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
615 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
616 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
617 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
618 XTOP>): Define and add entries.
619 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
620 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
621 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
622 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
624 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
625 Alan Modra <amodra@gmail.com>
627 * ppc-dis.c (ppc_opts): Add "future" entry.
628 (PREFIX_OPCD_SEGS): Define.
629 (prefix_opcd_indices): New array.
630 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
631 (lookup_prefix): New function.
632 (print_insn_powerpc): Handle 64-bit prefix instructions.
633 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
634 (PMRR, POWERXX): Define.
635 (prefix_opcodes): New instruction table.
636 (prefix_num_opcodes): New constant.
638 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
640 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
641 * configure: Regenerated.
642 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
644 (HFILES): Add bpf-desc.h and bpf-opc.h.
645 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
646 bpf-ibld.c and bpf-opc.c.
648 * Makefile.in: Regenerated.
649 * disassemble.c (ARCH_bpf): Define.
650 (disassembler): Add case for bfd_arch_bpf.
651 (disassemble_init_for_target): Likewise.
652 (enum epbf_isa_attr): Define.
653 * disassemble.h: extern print_insn_bpf.
654 * bpf-asm.c: Generated.
655 * bpf-opc.h: Likewise.
656 * bpf-opc.c: Likewise.
657 * bpf-ibld.c: Likewise.
658 * bpf-dis.c: Likewise.
659 * bpf-desc.h: Likewise.
660 * bpf-desc.c: Likewise.
662 2019-05-21 Sudakshina Das <sudi.das@arm.com>
664 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
665 and VMSR with the new operands.
667 2019-05-21 Sudakshina Das <sudi.das@arm.com>
669 * arm-dis.c (enum mve_instructions): New enum
670 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
672 (mve_opcodes): New instructions as above.
673 (is_mve_encoding_conflict): Add cases for csinc, csinv,
675 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
677 2019-05-21 Sudakshina Das <sudi.das@arm.com>
679 * arm-dis.c (emun mve_instructions): Updated for new instructions.
680 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
681 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
682 uqshl, urshrl and urshr.
683 (is_mve_okay_in_it): Add new instructions to TRUE list.
684 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
685 (print_insn_mve): Updated to accept new %j,
686 %<bitfield>m and %<bitfield>n patterns.
688 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
690 * mips-opc.c (mips_builtin_opcodes): Change source register
693 2019-05-20 Nick Clifton <nickc@redhat.com>
695 * po/fr.po: Updated French translation.
697 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
698 Michael Collison <michael.collison@arm.com>
700 * arm-dis.c (thumb32_opcodes): Add new instructions.
701 (enum mve_instructions): Likewise.
702 (enum mve_undefined): Add new reasons.
703 (is_mve_encoding_conflict): Handle new instructions.
704 (is_mve_undefined): Likewise.
705 (is_mve_unpredictable): Likewise.
706 (print_mve_undefined): Likewise.
707 (print_mve_size): Likewise.
709 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
710 Michael Collison <michael.collison@arm.com>
712 * arm-dis.c (thumb32_opcodes): Add new instructions.
713 (enum mve_instructions): Likewise.
714 (is_mve_encoding_conflict): Handle new instructions.
715 (is_mve_undefined): Likewise.
716 (is_mve_unpredictable): Likewise.
717 (print_mve_size): Likewise.
719 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
720 Michael Collison <michael.collison@arm.com>
722 * arm-dis.c (thumb32_opcodes): Add new instructions.
723 (enum mve_instructions): Likewise.
724 (is_mve_encoding_conflict): Likewise.
725 (is_mve_unpredictable): Likewise.
726 (print_mve_size): Likewise.
728 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
729 Michael Collison <michael.collison@arm.com>
731 * arm-dis.c (thumb32_opcodes): Add new instructions.
732 (enum mve_instructions): Likewise.
733 (is_mve_encoding_conflict): Handle new instructions.
734 (is_mve_undefined): Likewise.
735 (is_mve_unpredictable): Likewise.
736 (print_mve_size): Likewise.
738 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
739 Michael Collison <michael.collison@arm.com>
741 * arm-dis.c (thumb32_opcodes): Add new instructions.
742 (enum mve_instructions): Likewise.
743 (is_mve_encoding_conflict): Handle new instructions.
744 (is_mve_undefined): Likewise.
745 (is_mve_unpredictable): Likewise.
746 (print_mve_size): Likewise.
747 (print_insn_mve): Likewise.
749 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
750 Michael Collison <michael.collison@arm.com>
752 * arm-dis.c (thumb32_opcodes): Add new instructions.
753 (print_insn_thumb32): Handle new instructions.
755 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
756 Michael Collison <michael.collison@arm.com>
758 * arm-dis.c (enum mve_instructions): Add new instructions.
759 (enum mve_undefined): Add new reasons.
760 (is_mve_encoding_conflict): Handle new instructions.
761 (is_mve_undefined): Likewise.
762 (is_mve_unpredictable): Likewise.
763 (print_mve_undefined): Likewise.
764 (print_mve_size): Likewise.
765 (print_mve_shift_n): Likewise.
766 (print_insn_mve): Likewise.
768 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
769 Michael Collison <michael.collison@arm.com>
771 * arm-dis.c (enum mve_instructions): Add new instructions.
772 (is_mve_encoding_conflict): Handle new instructions.
773 (is_mve_unpredictable): Likewise.
774 (print_mve_rotate): Likewise.
775 (print_mve_size): Likewise.
776 (print_insn_mve): Likewise.
778 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
779 Michael Collison <michael.collison@arm.com>
781 * arm-dis.c (enum mve_instructions): Add new instructions.
782 (is_mve_encoding_conflict): Handle new instructions.
783 (is_mve_unpredictable): Likewise.
784 (print_mve_size): Likewise.
785 (print_insn_mve): Likewise.
787 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
788 Michael Collison <michael.collison@arm.com>
790 * arm-dis.c (enum mve_instructions): Add new instructions.
791 (enum mve_undefined): Add new reasons.
792 (is_mve_encoding_conflict): Handle new instructions.
793 (is_mve_undefined): Likewise.
794 (is_mve_unpredictable): Likewise.
795 (print_mve_undefined): Likewise.
796 (print_mve_size): Likewise.
797 (print_insn_mve): Likewise.
799 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
800 Michael Collison <michael.collison@arm.com>
802 * arm-dis.c (enum mve_instructions): Add new instructions.
803 (is_mve_encoding_conflict): Handle new instructions.
804 (is_mve_undefined): Likewise.
805 (is_mve_unpredictable): Likewise.
806 (print_mve_size): Likewise.
807 (print_insn_mve): Likewise.
809 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
810 Michael Collison <michael.collison@arm.com>
812 * arm-dis.c (enum mve_instructions): Add new instructions.
813 (enum mve_unpredictable): Add new reasons.
814 (enum mve_undefined): Likewise.
815 (is_mve_okay_in_it): Handle new isntructions.
816 (is_mve_encoding_conflict): Likewise.
817 (is_mve_undefined): Likewise.
818 (is_mve_unpredictable): Likewise.
819 (print_mve_vmov_index): Likewise.
820 (print_simd_imm8): Likewise.
821 (print_mve_undefined): Likewise.
822 (print_mve_unpredictable): Likewise.
823 (print_mve_size): Likewise.
824 (print_insn_mve): Likewise.
826 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
827 Michael Collison <michael.collison@arm.com>
829 * arm-dis.c (enum mve_instructions): Add new instructions.
830 (enum mve_unpredictable): Add new reasons.
831 (enum mve_undefined): Likewise.
832 (is_mve_encoding_conflict): Handle new instructions.
833 (is_mve_undefined): Likewise.
834 (is_mve_unpredictable): Likewise.
835 (print_mve_undefined): Likewise.
836 (print_mve_unpredictable): Likewise.
837 (print_mve_rounding_mode): Likewise.
838 (print_mve_vcvt_size): Likewise.
839 (print_mve_size): Likewise.
840 (print_insn_mve): Likewise.
842 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
843 Michael Collison <michael.collison@arm.com>
845 * arm-dis.c (enum mve_instructions): Add new instructions.
846 (enum mve_unpredictable): Add new reasons.
847 (enum mve_undefined): Likewise.
848 (is_mve_undefined): Handle new instructions.
849 (is_mve_unpredictable): Likewise.
850 (print_mve_undefined): Likewise.
851 (print_mve_unpredictable): Likewise.
852 (print_mve_size): Likewise.
853 (print_insn_mve): Likewise.
855 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
856 Michael Collison <michael.collison@arm.com>
858 * arm-dis.c (enum mve_instructions): Add new instructions.
859 (enum mve_undefined): Add new reasons.
860 (insns): Add new instructions.
861 (is_mve_encoding_conflict):
862 (print_mve_vld_str_addr): New print function.
863 (is_mve_undefined): Handle new instructions.
864 (is_mve_unpredictable): Likewise.
865 (print_mve_undefined): Likewise.
866 (print_mve_size): Likewise.
867 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
868 (print_insn_mve): Handle new operands.
870 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
871 Michael Collison <michael.collison@arm.com>
873 * arm-dis.c (enum mve_instructions): Add new instructions.
874 (enum mve_unpredictable): Add new reasons.
875 (is_mve_encoding_conflict): Handle new instructions.
876 (is_mve_unpredictable): Likewise.
877 (mve_opcodes): Add new instructions.
878 (print_mve_unpredictable): Handle new reasons.
879 (print_mve_register_blocks): New print function.
880 (print_mve_size): Handle new instructions.
881 (print_insn_mve): Likewise.
883 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
884 Michael Collison <michael.collison@arm.com>
886 * arm-dis.c (enum mve_instructions): Add new instructions.
887 (enum mve_unpredictable): Add new reasons.
888 (enum mve_undefined): Likewise.
889 (is_mve_encoding_conflict): Handle new instructions.
890 (is_mve_undefined): Likewise.
891 (is_mve_unpredictable): Likewise.
892 (coprocessor_opcodes): Move NEON VDUP from here...
893 (neon_opcodes): ... to here.
894 (mve_opcodes): Add new instructions.
895 (print_mve_undefined): Handle new reasons.
896 (print_mve_unpredictable): Likewise.
897 (print_mve_size): Handle new instructions.
898 (print_insn_neon): Handle vdup.
899 (print_insn_mve): Handle new operands.
901 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
902 Michael Collison <michael.collison@arm.com>
904 * arm-dis.c (enum mve_instructions): Add new instructions.
905 (enum mve_unpredictable): Add new values.
906 (mve_opcodes): Add new instructions.
907 (vec_condnames): New array with vector conditions.
908 (mve_predicatenames): New array with predicate suffixes.
909 (mve_vec_sizename): New array with vector sizes.
910 (enum vpt_pred_state): New enum with vector predication states.
911 (struct vpt_block): New struct type for vpt blocks.
912 (vpt_block_state): Global struct to keep track of state.
913 (mve_extract_pred_mask): New helper function.
914 (num_instructions_vpt_block): Likewise.
915 (mark_outside_vpt_block): Likewise.
916 (mark_inside_vpt_block): Likewise.
917 (invert_next_predicate_state): Likewise.
918 (update_next_predicate_state): Likewise.
919 (update_vpt_block_state): Likewise.
920 (is_vpt_instruction): Likewise.
921 (is_mve_encoding_conflict): Add entries for new instructions.
922 (is_mve_unpredictable): Likewise.
923 (print_mve_unpredictable): Handle new cases.
924 (print_instruction_predicate): Likewise.
925 (print_mve_size): New function.
926 (print_vec_condition): New function.
927 (print_insn_mve): Handle vpt blocks and new print operands.
929 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
931 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
932 8, 14 and 15 for Armv8.1-M Mainline.
934 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
935 Michael Collison <michael.collison@arm.com>
937 * arm-dis.c (enum mve_instructions): New enum.
938 (enum mve_unpredictable): Likewise.
939 (enum mve_undefined): Likewise.
940 (struct mopcode32): New struct.
941 (is_mve_okay_in_it): New function.
942 (is_mve_architecture): Likewise.
943 (arm_decode_field): Likewise.
944 (arm_decode_field_multiple): Likewise.
945 (is_mve_encoding_conflict): Likewise.
946 (is_mve_undefined): Likewise.
947 (is_mve_unpredictable): Likewise.
948 (print_mve_undefined): Likewise.
949 (print_mve_unpredictable): Likewise.
950 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
951 (print_insn_mve): New function.
952 (print_insn_thumb32): Handle MVE architecture.
953 (select_arm_features): Force thumb for Armv8.1-m Mainline.
955 2019-05-10 Nick Clifton <nickc@redhat.com>
958 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
959 end of the table prematurely.
961 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
963 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
966 2019-05-11 Alan Modra <amodra@gmail.com>
968 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
969 when -Mraw is in effect.
971 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
973 * aarch64-dis-2.c: Regenerate.
974 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
975 (OP_SVE_BBB): New variant set.
976 (OP_SVE_DDDD): New variant set.
977 (OP_SVE_HHH): New variant set.
978 (OP_SVE_HHHU): New variant set.
979 (OP_SVE_SSS): New variant set.
980 (OP_SVE_SSSU): New variant set.
981 (OP_SVE_SHH): New variant set.
982 (OP_SVE_SBBU): New variant set.
983 (OP_SVE_DSS): New variant set.
984 (OP_SVE_DHHU): New variant set.
985 (OP_SVE_VMV_HSD_BHS): New variant set.
986 (OP_SVE_VVU_HSD_BHS): New variant set.
987 (OP_SVE_VVVU_SD_BH): New variant set.
988 (OP_SVE_VVVU_BHSD): New variant set.
989 (OP_SVE_VVV_QHD_DBS): New variant set.
990 (OP_SVE_VVV_HSD_BHS): New variant set.
991 (OP_SVE_VVV_HSD_BHS2): New variant set.
992 (OP_SVE_VVV_BHS_HSD): New variant set.
993 (OP_SVE_VV_BHS_HSD): New variant set.
994 (OP_SVE_VVV_SD): New variant set.
995 (OP_SVE_VVU_BHS_HSD): New variant set.
996 (OP_SVE_VZVV_SD): New variant set.
997 (OP_SVE_VZVV_BH): New variant set.
998 (OP_SVE_VZV_SD): New variant set.
999 (aarch64_opcode_table): Add sve2 instructions.
1001 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1003 * aarch64-asm-2.c: Regenerated.
1004 * aarch64-dis-2.c: Regenerated.
1005 * aarch64-opc-2.c: Regenerated.
1006 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1007 for SVE_SHLIMM_UNPRED_22.
1008 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1009 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1012 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1014 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1015 sve_size_tsz_bhs iclass encode.
1016 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1017 sve_size_tsz_bhs iclass decode.
1019 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1021 * aarch64-asm-2.c: Regenerated.
1022 * aarch64-dis-2.c: Regenerated.
1023 * aarch64-opc-2.c: Regenerated.
1024 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1025 for SVE_Zm4_11_INDEX.
1026 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1027 (fields): Handle SVE_i2h field.
1028 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1029 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1031 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1033 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1034 sve_shift_tsz_bhsd iclass encode.
1035 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1036 sve_shift_tsz_bhsd iclass decode.
1038 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1040 * aarch64-asm-2.c: Regenerated.
1041 * aarch64-dis-2.c: Regenerated.
1042 * aarch64-opc-2.c: Regenerated.
1043 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1044 (aarch64_encode_variant_using_iclass): Handle
1045 sve_shift_tsz_hsd iclass encode.
1046 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1047 sve_shift_tsz_hsd iclass decode.
1048 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1049 for SVE_SHRIMM_UNPRED_22.
1050 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1051 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1054 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1056 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1057 sve_size_013 iclass encode.
1058 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1059 sve_size_013 iclass decode.
1061 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1063 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1064 sve_size_bh iclass encode.
1065 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1066 sve_size_bh iclass decode.
1068 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1070 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1071 sve_size_sd2 iclass encode.
1072 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1073 sve_size_sd2 iclass decode.
1074 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1075 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1077 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1079 * aarch64-asm-2.c: Regenerated.
1080 * aarch64-dis-2.c: Regenerated.
1081 * aarch64-opc-2.c: Regenerated.
1082 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1084 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1085 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1087 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1089 * aarch64-asm-2.c: Regenerated.
1090 * aarch64-dis-2.c: Regenerated.
1091 * aarch64-opc-2.c: Regenerated.
1092 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1093 for SVE_Zm3_11_INDEX.
1094 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1095 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1096 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1098 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1100 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1102 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1103 sve_size_hsd2 iclass encode.
1104 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1105 sve_size_hsd2 iclass decode.
1106 * aarch64-opc.c (fields): Handle SVE_size field.
1107 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1109 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1111 * aarch64-asm-2.c: Regenerated.
1112 * aarch64-dis-2.c: Regenerated.
1113 * aarch64-opc-2.c: Regenerated.
1114 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1116 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1117 (fields): Handle SVE_rot3 field.
1118 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1119 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1121 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1123 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1126 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1129 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1130 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1131 aarch64_feature_sve2bitperm): New feature sets.
1132 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1133 for feature set addresses.
1134 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1135 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1137 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1138 Faraz Shahbazker <fshahbazker@wavecomp.com>
1140 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1141 argument and set ASE_EVA_R6 appropriately.
1142 (set_default_mips_dis_options): Pass ISA to above.
1143 (parse_mips_dis_option): Likewise.
1144 * mips-opc.c (EVAR6): New macro.
1145 (mips_builtin_opcodes): Add llwpe, scwpe.
1147 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1149 * aarch64-asm-2.c: Regenerated.
1150 * aarch64-dis-2.c: Regenerated.
1151 * aarch64-opc-2.c: Regenerated.
1152 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1153 AARCH64_OPND_TME_UIMM16.
1154 (aarch64_print_operand): Likewise.
1155 * aarch64-tbl.h (QL_IMM_NIL): New.
1158 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1160 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1162 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1164 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1165 Faraz Shahbazker <fshahbazker@wavecomp.com>
1167 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1169 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1171 * s12z-opc.h: Add extern "C" bracketing to help
1172 users who wish to use this interface in c++ code.
1174 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1176 * s12z-opc.c (bm_decode): Handle bit map operations with the
1179 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1181 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1182 specifier. Add entries for VLDR and VSTR of system registers.
1183 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1184 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1185 of %J and %K format specifier.
1187 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1189 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1190 Add new entries for VSCCLRM instruction.
1191 (print_insn_coprocessor): Handle new %C format control code.
1193 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1195 * arm-dis.c (enum isa): New enum.
1196 (struct sopcode32): New structure.
1197 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1198 set isa field of all current entries to ANY.
1199 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1200 Only match an entry if its isa field allows the current mode.
1202 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1204 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1206 (print_insn_thumb32): Add logic to print %n CLRM register list.
1208 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1210 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1213 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1215 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1216 (print_insn_thumb32): Edit the switch case for %Z.
1218 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1220 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1222 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1224 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1226 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1228 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1230 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1232 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1233 Arm register with r13 and r15 unpredictable.
1234 (thumb32_opcodes): New instructions for bfx and bflx.
1236 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1238 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1240 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1242 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1244 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1246 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1248 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1250 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1252 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1254 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1255 "optr". ("operator" is a reserved word in c++).
1257 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1259 * aarch64-opc.c (aarch64_print_operand): Add case for
1261 (verify_constraints): Likewise.
1262 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1263 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1264 to accept Rt|SP as first operand.
1265 (AARCH64_OPERANDS): Add new Rt_SP.
1266 * aarch64-asm-2.c: Regenerated.
1267 * aarch64-dis-2.c: Regenerated.
1268 * aarch64-opc-2.c: Regenerated.
1270 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1272 * aarch64-asm-2.c: Regenerated.
1273 * aarch64-dis-2.c: Likewise.
1274 * aarch64-opc-2.c: Likewise.
1275 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1277 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1279 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1281 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1283 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1284 * i386-init.h: Regenerated.
1286 2019-04-07 Alan Modra <amodra@gmail.com>
1288 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1289 op_separator to control printing of spaces, comma and parens
1290 rather than need_comma, need_paren and spaces vars.
1292 2019-04-07 Alan Modra <amodra@gmail.com>
1295 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1296 (print_insn_neon, print_insn_arm): Likewise.
1298 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1300 * i386-dis-evex.h (evex_table): Updated to support BF16
1302 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1303 and EVEX_W_0F3872_P_3.
1304 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1305 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1306 * i386-opc.h (enum): Add CpuAVX512_BF16.
1307 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1308 * i386-opc.tbl: Add AVX512 BF16 instructions.
1309 * i386-init.h: Regenerated.
1310 * i386-tbl.h: Likewise.
1312 2019-04-05 Alan Modra <amodra@gmail.com>
1314 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1315 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1316 to favour printing of "-" branch hint when using the "y" bit.
1317 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1319 2019-04-05 Alan Modra <amodra@gmail.com>
1321 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1322 opcode until first operand is output.
1324 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1327 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1328 (valid_bo_post_v2): Add support for 'at' branch hints.
1329 (insert_bo): Only error on branch on ctr.
1330 (get_bo_hint_mask): New function.
1331 (insert_boe): Add new 'branch_taken' formal argument. Add support
1332 for inserting 'at' branch hints.
1333 (extract_boe): Add new 'branch_taken' formal argument. Add support
1334 for extracting 'at' branch hints.
1335 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1336 (BOE): Delete operand.
1337 (BOM, BOP): New operands.
1339 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1340 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1341 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1342 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1343 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1344 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1345 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1346 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1347 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1348 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1349 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1350 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1351 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1352 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1353 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1354 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1355 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1356 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1357 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1358 bttarl+>: New extended mnemonics.
1360 2019-03-28 Alan Modra <amodra@gmail.com>
1363 * ppc-opc.c (BTF): Define.
1364 (powerpc_opcodes): Use for mtfsb*.
1365 * ppc-dis.c (print_insn_powerpc): Print fields with both
1366 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1368 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1370 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1371 (mapping_symbol_for_insn): Implement new algorithm.
1372 (print_insn): Remove duplicate code.
1374 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1376 * aarch64-dis.c (print_insn_aarch64):
1379 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1381 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1384 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1386 * aarch64-dis.c (last_stop_offset): New.
1387 (print_insn_aarch64): Use stop_offset.
1389 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1392 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1394 * i386-init.h: Regenerated.
1396 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1399 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1400 vmovdqu16, vmovdqu32 and vmovdqu64.
1401 * i386-tbl.h: Regenerated.
1403 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1405 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1406 from vstrszb, vstrszh, and vstrszf.
1408 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1410 * s390-opc.txt: Add instruction descriptions.
1412 2019-02-08 Jim Wilson <jimw@sifive.com>
1414 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1417 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1419 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1421 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1424 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1425 * aarch64-opc.c (verify_elem_sd): New.
1426 (fields): Add FLD_sz entr.
1427 * aarch64-tbl.h (_SIMD_INSN): New.
1428 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1429 fmulx scalar and vector by element isns.
1431 2019-02-07 Nick Clifton <nickc@redhat.com>
1433 * po/sv.po: Updated Swedish translation.
1435 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1437 * s390-mkopc.c (main): Accept arch13 as cpu string.
1438 * s390-opc.c: Add new instruction formats and instruction opcode
1440 * s390-opc.txt: Add new arch13 instructions.
1442 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1444 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1445 (aarch64_opcode): Change encoding for stg, stzg
1447 * aarch64-asm-2.c: Regenerated.
1448 * aarch64-dis-2.c: Regenerated.
1449 * aarch64-opc-2.c: Regenerated.
1451 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1453 * aarch64-asm-2.c: Regenerated.
1454 * aarch64-dis-2.c: Likewise.
1455 * aarch64-opc-2.c: Likewise.
1456 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1458 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1459 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1461 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1462 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1463 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1464 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1465 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1466 case for ldstgv_indexed.
1467 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1468 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1469 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1470 * aarch64-asm-2.c: Regenerated.
1471 * aarch64-dis-2.c: Regenerated.
1472 * aarch64-opc-2.c: Regenerated.
1474 2019-01-23 Nick Clifton <nickc@redhat.com>
1476 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1478 2019-01-21 Nick Clifton <nickc@redhat.com>
1480 * po/de.po: Updated German translation.
1481 * po/uk.po: Updated Ukranian translation.
1483 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1484 * mips-dis.c (mips_arch_choices): Fix typo in
1485 gs464, gs464e and gs264e descriptors.
1487 2019-01-19 Nick Clifton <nickc@redhat.com>
1489 * configure: Regenerate.
1490 * po/opcodes.pot: Regenerate.
1492 2018-06-24 Nick Clifton <nickc@redhat.com>
1494 2.32 branch created.
1496 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1498 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1500 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1503 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1505 * configure: Regenerate.
1507 2019-01-07 Alan Modra <amodra@gmail.com>
1509 * configure: Regenerate.
1510 * po/POTFILES.in: Regenerate.
1512 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1514 * s12z-opc.c: New file.
1515 * s12z-opc.h: New file.
1516 * s12z-dis.c: Removed all code not directly related to display
1517 of instructions. Used the interface provided by the new files
1519 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1520 * Makefile.in: Regenerate.
1521 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1522 * configure: Regenerate.
1524 2019-01-01 Alan Modra <amodra@gmail.com>
1526 Update year range in copyright notice of all files.
1528 For older changes see ChangeLog-2018
1530 Copyright (C) 2019 Free Software Foundation, Inc.
1532 Copying and distribution of this file, with or without modification,
1533 are permitted in any medium without royalty provided the copyright
1534 notice and this notice are preserved.
1540 version-control: never