opcodes/ChangeLog

   1 2019-05-24  Alan Modra  <amodra@gmail.com>
   2
   3         * po/POTFILES.in: Regenerate.
   4
   5 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
   6             Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
   9         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
  10         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
  11         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
  12         XTOP>): Define and add entries.
  13         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
  14         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
  15         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
  16         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
  17
  18 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
  19             Alan Modra  <amodra@gmail.com>
  20
  21         * ppc-dis.c (ppc_opts): Add "future" entry.
  22         (PREFIX_OPCD_SEGS): Define.
  23         (prefix_opcd_indices): New array.
  24         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
  25         (lookup_prefix): New function.
  26         (print_insn_powerpc): Handle 64-bit prefix instructions.
  27         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
  28         (PMRR, POWERXX): Define.
  29         (prefix_opcodes): New instruction table.
  30         (prefix_num_opcodes): New constant.
  31
  32 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  33
  34         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
  35         * configure: Regenerated.
  36         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
  37         and cpu/bpf.opc.
  38         (HFILES): Add bpf-desc.h and bpf-opc.h.
  39         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
  40         bpf-ibld.c and bpf-opc.c.
  41         (BPF_DEPS): Define.
  42         * Makefile.in: Regenerated.
  43         * disassemble.c (ARCH_bpf): Define.
  44         (disassembler): Add case for bfd_arch_bpf.
  45         (disassemble_init_for_target): Likewise.
  46         (enum epbf_isa_attr): Define.
  47         * disassemble.h: extern print_insn_bpf.
  48         * bpf-asm.c: Generated.
  49         * bpf-opc.h: Likewise.
  50         * bpf-opc.c: Likewise.
  51         * bpf-ibld.c: Likewise.
  52         * bpf-dis.c: Likewise.
  53         * bpf-desc.h: Likewise.
  54         * bpf-desc.c: Likewise.
  55
  56 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  57
  58         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
  59         and VMSR with the new operands.
  60
  61 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  62
  63         * arm-dis.c (enum mve_instructions): New enum
  64         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
  65         and cneg.
  66         (mve_opcodes): New instructions as above.
  67         (is_mve_encoding_conflict): Add cases for csinc, csinv,
  68         csneg and csel.
  69         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
  70
  71 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * arm-dis.c (emun mve_instructions): Updated for new instructions.
  74         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
  75         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
  76         uqshl, urshrl and urshr.
  77         (is_mve_okay_in_it): Add new instructions to TRUE list.
  78         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
  79         (print_insn_mve): Updated to accept new %j,
  80         %<bitfield>m and %<bitfield>n patterns.
  81
  82 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
  83
  84         * mips-opc.c (mips_builtin_opcodes): Change source register
  85         constraint for DAUI.
  86
  87 2019-05-20  Nick Clifton  <nickc@redhat.com>
  88
  89         * po/fr.po: Updated French translation.
  90
  91 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  92             Michael Collison <michael.collison@arm.com>
  93
  94         * arm-dis.c (thumb32_opcodes): Add new instructions.
  95         (enum mve_instructions): Likewise.
  96         (enum mve_undefined): Add new reasons.
  97         (is_mve_encoding_conflict): Handle new instructions.
  98         (is_mve_undefined): Likewise.
  99         (is_mve_unpredictable): Likewise.
 100         (print_mve_undefined): Likewise.
 101         (print_mve_size): Likewise.
 102
 103 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 104             Michael Collison <michael.collison@arm.com>
 105
 106         * arm-dis.c (thumb32_opcodes): Add new instructions.
 107         (enum mve_instructions): Likewise.
 108         (is_mve_encoding_conflict): Handle new instructions.
 109         (is_mve_undefined): Likewise.
 110         (is_mve_unpredictable): Likewise.
 111         (print_mve_size): Likewise.
 112
 113 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 114             Michael Collison <michael.collison@arm.com>
 115
 116         * arm-dis.c (thumb32_opcodes): Add new instructions.
 117         (enum mve_instructions): Likewise.
 118         (is_mve_encoding_conflict): Likewise.
 119         (is_mve_unpredictable): Likewise.
 120         (print_mve_size): Likewise.
 121
 122 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 123             Michael Collison <michael.collison@arm.com>
 124
 125         * arm-dis.c (thumb32_opcodes): Add new instructions.
 126         (enum mve_instructions): Likewise.
 127         (is_mve_encoding_conflict): Handle new instructions.
 128         (is_mve_undefined): Likewise.
 129         (is_mve_unpredictable): Likewise.
 130         (print_mve_size): Likewise.
 131
 132 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 133             Michael Collison <michael.collison@arm.com>
 134
 135         * arm-dis.c (thumb32_opcodes): Add new instructions.
 136         (enum mve_instructions): Likewise.
 137         (is_mve_encoding_conflict): Handle new instructions.
 138         (is_mve_undefined): Likewise.
 139         (is_mve_unpredictable): Likewise.
 140         (print_mve_size): Likewise.
 141         (print_insn_mve): Likewise.
 142
 143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 144             Michael Collison <michael.collison@arm.com>
 145
 146         * arm-dis.c (thumb32_opcodes): Add new instructions.
 147         (print_insn_thumb32): Handle new instructions.
 148
 149 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 150             Michael Collison <michael.collison@arm.com>
 151
 152         * arm-dis.c (enum mve_instructions): Add new instructions.
 153         (enum mve_undefined): Add new reasons.
 154         (is_mve_encoding_conflict): Handle new instructions.
 155         (is_mve_undefined): Likewise.
 156         (is_mve_unpredictable): Likewise.
 157         (print_mve_undefined): Likewise.
 158         (print_mve_size): Likewise.
 159         (print_mve_shift_n): Likewise.
 160         (print_insn_mve): Likewise.
 161
 162 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 163             Michael Collison <michael.collison@arm.com>
 164
 165         * arm-dis.c (enum mve_instructions): Add new instructions.
 166         (is_mve_encoding_conflict): Handle new instructions.
 167         (is_mve_unpredictable): Likewise.
 168         (print_mve_rotate): Likewise.
 169         (print_mve_size): Likewise.
 170         (print_insn_mve): Likewise.
 171
 172 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 173             Michael Collison <michael.collison@arm.com>
 174
 175         * arm-dis.c (enum mve_instructions): Add new instructions.
 176         (is_mve_encoding_conflict): Handle new instructions.
 177         (is_mve_unpredictable): Likewise.
 178         (print_mve_size): Likewise.
 179         (print_insn_mve): Likewise.
 180
 181 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 182             Michael Collison <michael.collison@arm.com>
 183
 184         * arm-dis.c (enum mve_instructions): Add new instructions.
 185         (enum mve_undefined): Add new reasons.
 186         (is_mve_encoding_conflict): Handle new instructions.
 187         (is_mve_undefined): Likewise.
 188         (is_mve_unpredictable): Likewise.
 189         (print_mve_undefined): Likewise.
 190         (print_mve_size): Likewise.
 191         (print_insn_mve): Likewise.
 192
 193 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 194             Michael Collison <michael.collison@arm.com>
 195
 196         * arm-dis.c (enum mve_instructions): Add new instructions.
 197         (is_mve_encoding_conflict): Handle new instructions.
 198         (is_mve_undefined): Likewise.
 199         (is_mve_unpredictable): Likewise.
 200         (print_mve_size): Likewise.
 201         (print_insn_mve): Likewise.
 202
 203 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 204             Michael Collison <michael.collison@arm.com>
 205
 206         * arm-dis.c (enum mve_instructions): Add new instructions.
 207         (enum mve_unpredictable): Add new reasons.
 208         (enum mve_undefined): Likewise.
 209         (is_mve_okay_in_it): Handle new isntructions.
 210         (is_mve_encoding_conflict): Likewise.
 211         (is_mve_undefined): Likewise.
 212         (is_mve_unpredictable): Likewise.
 213         (print_mve_vmov_index): Likewise.
 214         (print_simd_imm8): Likewise.
 215         (print_mve_undefined): Likewise.
 216         (print_mve_unpredictable): Likewise.
 217         (print_mve_size): Likewise.
 218         (print_insn_mve): Likewise.
 219
 220 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 221             Michael Collison <michael.collison@arm.com>
 222
 223         * arm-dis.c (enum mve_instructions): Add new instructions.
 224         (enum mve_unpredictable): Add new reasons.
 225         (enum mve_undefined): Likewise.
 226         (is_mve_encoding_conflict): Handle new instructions.
 227         (is_mve_undefined): Likewise.
 228         (is_mve_unpredictable): Likewise.
 229         (print_mve_undefined): Likewise.
 230         (print_mve_unpredictable): Likewise.
 231         (print_mve_rounding_mode): Likewise.
 232         (print_mve_vcvt_size): Likewise.
 233         (print_mve_size): Likewise.
 234         (print_insn_mve): Likewise.
 235
 236 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 237             Michael Collison <michael.collison@arm.com>
 238
 239         * arm-dis.c (enum mve_instructions): Add new instructions.
 240         (enum mve_unpredictable): Add new reasons.
 241         (enum mve_undefined): Likewise.
 242         (is_mve_undefined): Handle new instructions.
 243         (is_mve_unpredictable): Likewise.
 244         (print_mve_undefined): Likewise.
 245         (print_mve_unpredictable): Likewise.
 246         (print_mve_size): Likewise.
 247         (print_insn_mve): Likewise.
 248
 249 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 250             Michael Collison <michael.collison@arm.com>
 251
 252         * arm-dis.c (enum mve_instructions): Add new instructions.
 253         (enum mve_undefined): Add new reasons.
 254         (insns): Add new instructions.
 255         (is_mve_encoding_conflict):
 256         (print_mve_vld_str_addr): New print function.
 257         (is_mve_undefined): Handle new instructions.
 258         (is_mve_unpredictable): Likewise.
 259         (print_mve_undefined): Likewise.
 260         (print_mve_size): Likewise.
 261         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 262         (print_insn_mve):  Handle new operands.
 263
 264 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 265             Michael Collison <michael.collison@arm.com>
 266
 267         * arm-dis.c (enum mve_instructions): Add new instructions.
 268         (enum mve_unpredictable): Add new reasons.
 269         (is_mve_encoding_conflict): Handle new instructions.
 270         (is_mve_unpredictable): Likewise.
 271         (mve_opcodes): Add new instructions.
 272         (print_mve_unpredictable): Handle new reasons.
 273         (print_mve_register_blocks): New print function.
 274         (print_mve_size): Handle new instructions.
 275         (print_insn_mve): Likewise.
 276
 277 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 278             Michael Collison <michael.collison@arm.com>
 279
 280         * arm-dis.c (enum mve_instructions): Add new instructions.
 281         (enum mve_unpredictable): Add new reasons.
 282         (enum mve_undefined): Likewise.
 283         (is_mve_encoding_conflict): Handle new instructions.
 284         (is_mve_undefined): Likewise.
 285         (is_mve_unpredictable): Likewise.
 286         (coprocessor_opcodes): Move NEON VDUP from here...
 287         (neon_opcodes): ... to here.
 288         (mve_opcodes): Add new instructions.
 289         (print_mve_undefined):  Handle new reasons.
 290         (print_mve_unpredictable): Likewise.
 291         (print_mve_size): Handle new instructions.
 292         (print_insn_neon): Handle vdup.
 293         (print_insn_mve): Handle new operands.
 294
 295 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 296             Michael Collison <michael.collison@arm.com>
 297
 298         * arm-dis.c (enum mve_instructions): Add new instructions.
 299         (enum mve_unpredictable): Add new values.
 300         (mve_opcodes): Add new instructions.
 301         (vec_condnames): New array with vector conditions.
 302         (mve_predicatenames): New array with predicate suffixes.
 303         (mve_vec_sizename): New array with vector sizes.
 304         (enum vpt_pred_state): New enum with vector predication states.
 305         (struct vpt_block): New struct type for vpt blocks.
 306         (vpt_block_state): Global struct to keep track of state.
 307         (mve_extract_pred_mask): New helper function.
 308         (num_instructions_vpt_block): Likewise.
 309         (mark_outside_vpt_block): Likewise.
 310         (mark_inside_vpt_block): Likewise.
 311         (invert_next_predicate_state): Likewise.
 312         (update_next_predicate_state): Likewise.
 313         (update_vpt_block_state): Likewise.
 314         (is_vpt_instruction): Likewise.
 315         (is_mve_encoding_conflict): Add entries for new instructions.
 316         (is_mve_unpredictable): Likewise.
 317         (print_mve_unpredictable): Handle new cases.
 318         (print_instruction_predicate): Likewise.
 319         (print_mve_size): New function.
 320         (print_vec_condition): New function.
 321         (print_insn_mve): Handle vpt blocks and new print operands.
 322
 323 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 324
 325         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 326         8, 14 and 15 for Armv8.1-M Mainline.
 327
 328 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 329             Michael Collison <michael.collison@arm.com>
 330
 331         * arm-dis.c (enum mve_instructions): New enum.
 332         (enum mve_unpredictable): Likewise.
 333         (enum mve_undefined): Likewise.
 334         (struct mopcode32): New struct.
 335         (is_mve_okay_in_it): New function.
 336         (is_mve_architecture): Likewise.
 337         (arm_decode_field): Likewise.
 338         (arm_decode_field_multiple): Likewise.
 339         (is_mve_encoding_conflict): Likewise.
 340         (is_mve_undefined): Likewise.
 341         (is_mve_unpredictable): Likewise.
 342         (print_mve_undefined): Likewise.
 343         (print_mve_unpredictable): Likewise.
 344         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 345         (print_insn_mve): New function.
 346         (print_insn_thumb32): Handle MVE architecture.
 347         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 348
 349 2019-05-10  Nick Clifton  <nickc@redhat.com>
 350
 351         PR 24538
 352         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 353         end of the table prematurely.
 354
 355 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 356
 357         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 358         macros for R6.
 359
 360 2019-05-11  Alan Modra  <amodra@gmail.com>
 361
 362         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 363         when -Mraw is in effect.
 364
 365 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 366
 367         * aarch64-dis-2.c: Regenerate.
 368         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 369         (OP_SVE_BBB): New variant set.
 370         (OP_SVE_DDDD): New variant set.
 371         (OP_SVE_HHH): New variant set.
 372         (OP_SVE_HHHU): New variant set.
 373         (OP_SVE_SSS): New variant set.
 374         (OP_SVE_SSSU): New variant set.
 375         (OP_SVE_SHH): New variant set.
 376         (OP_SVE_SBBU): New variant set.
 377         (OP_SVE_DSS): New variant set.
 378         (OP_SVE_DHHU): New variant set.
 379         (OP_SVE_VMV_HSD_BHS): New variant set.
 380         (OP_SVE_VVU_HSD_BHS): New variant set.
 381         (OP_SVE_VVVU_SD_BH): New variant set.
 382         (OP_SVE_VVVU_BHSD): New variant set.
 383         (OP_SVE_VVV_QHD_DBS): New variant set.
 384         (OP_SVE_VVV_HSD_BHS): New variant set.
 385         (OP_SVE_VVV_HSD_BHS2): New variant set.
 386         (OP_SVE_VVV_BHS_HSD): New variant set.
 387         (OP_SVE_VV_BHS_HSD): New variant set.
 388         (OP_SVE_VVV_SD): New variant set.
 389         (OP_SVE_VVU_BHS_HSD): New variant set.
 390         (OP_SVE_VZVV_SD): New variant set.
 391         (OP_SVE_VZVV_BH): New variant set.
 392         (OP_SVE_VZV_SD): New variant set.
 393         (aarch64_opcode_table): Add sve2 instructions.
 394
 395 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 396
 397         * aarch64-asm-2.c: Regenerated.
 398         * aarch64-dis-2.c: Regenerated.
 399         * aarch64-opc-2.c: Regenerated.
 400         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 401         for SVE_SHLIMM_UNPRED_22.
 402         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 403         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 404         operand.
 405
 406 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 407
 408         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 409         sve_size_tsz_bhs iclass encode.
 410         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 411         sve_size_tsz_bhs iclass decode.
 412
 413 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 414
 415         * aarch64-asm-2.c: Regenerated.
 416         * aarch64-dis-2.c: Regenerated.
 417         * aarch64-opc-2.c: Regenerated.
 418         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 419         for SVE_Zm4_11_INDEX.
 420         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 421         (fields): Handle SVE_i2h field.
 422         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 423         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 424
 425 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 426
 427         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 428         sve_shift_tsz_bhsd iclass encode.
 429         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 430         sve_shift_tsz_bhsd iclass decode.
 431
 432 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 433
 434         * aarch64-asm-2.c: Regenerated.
 435         * aarch64-dis-2.c: Regenerated.
 436         * aarch64-opc-2.c: Regenerated.
 437         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 438         (aarch64_encode_variant_using_iclass): Handle
 439         sve_shift_tsz_hsd iclass encode.
 440         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 441         sve_shift_tsz_hsd iclass decode.
 442         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 443         for SVE_SHRIMM_UNPRED_22.
 444         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 445         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 446         operand.
 447
 448 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 449
 450         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 451         sve_size_013 iclass encode.
 452         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 453         sve_size_013 iclass decode.
 454
 455 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 456
 457         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 458         sve_size_bh iclass encode.
 459         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 460         sve_size_bh iclass decode.
 461
 462 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 463
 464         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 465         sve_size_sd2 iclass encode.
 466         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 467         sve_size_sd2 iclass decode.
 468         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 469         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 470
 471 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 472
 473         * aarch64-asm-2.c: Regenerated.
 474         * aarch64-dis-2.c: Regenerated.
 475         * aarch64-opc-2.c: Regenerated.
 476         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 477         for SVE_ADDR_ZX.
 478         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 479         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 480
 481 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 482
 483         * aarch64-asm-2.c: Regenerated.
 484         * aarch64-dis-2.c: Regenerated.
 485         * aarch64-opc-2.c: Regenerated.
 486         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 487         for SVE_Zm3_11_INDEX.
 488         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 489         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 490         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 491         fields.
 492         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 493
 494 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 495
 496         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 497         sve_size_hsd2 iclass encode.
 498         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 499         sve_size_hsd2 iclass decode.
 500         * aarch64-opc.c (fields): Handle SVE_size field.
 501         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 502
 503 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 504
 505         * aarch64-asm-2.c: Regenerated.
 506         * aarch64-dis-2.c: Regenerated.
 507         * aarch64-opc-2.c: Regenerated.
 508         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 509         for SVE_IMM_ROT3.
 510         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 511         (fields): Handle SVE_rot3 field.
 512         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 513         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 514
 515 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 516
 517         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 518         instructions.
 519
 520 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 521
 522         * aarch64-tbl.h
 523         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 524         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 525         aarch64_feature_sve2bitperm): New feature sets.
 526         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 527         for feature set addresses.
 528         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 529         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 530
 531 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 532             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 533
 534         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 535         argument and set ASE_EVA_R6 appropriately.
 536         (set_default_mips_dis_options): Pass ISA to above.
 537         (parse_mips_dis_option): Likewise.
 538         * mips-opc.c (EVAR6): New macro.
 539         (mips_builtin_opcodes): Add llwpe, scwpe.
 540
 541 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 542
 543         * aarch64-asm-2.c: Regenerated.
 544         * aarch64-dis-2.c: Regenerated.
 545         * aarch64-opc-2.c: Regenerated.
 546         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 547         AARCH64_OPND_TME_UIMM16.
 548         (aarch64_print_operand): Likewise.
 549         * aarch64-tbl.h (QL_IMM_NIL): New.
 550         (TME): New.
 551         (_TME_INSN): New.
 552         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 553
 554 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 555
 556         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 557
 558 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 559             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 560
 561         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 562
 563 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 564
 565         * s12z-opc.h: Add extern "C" bracketing to help
 566         users who wish to use this interface in c++ code.
 567
 568 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 569
 570         * s12z-opc.c (bm_decode): Handle bit map operations with the
 571         "reserved0" mode.
 572
 573 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 574
 575         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 576         specifier.  Add entries for VLDR and VSTR of system registers.
 577         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 578         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 579         of %J and %K format specifier.
 580
 581 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 582
 583         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 584         Add new entries for VSCCLRM instruction.
 585         (print_insn_coprocessor): Handle new %C format control code.
 586
 587 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 588
 589         * arm-dis.c (enum isa): New enum.
 590         (struct sopcode32): New structure.
 591         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 592         set isa field of all current entries to ANY.
 593         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 594         Only match an entry if its isa field allows the current mode.
 595
 596 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 597
 598         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 599         CLRM.
 600         (print_insn_thumb32): Add logic to print %n CLRM register list.
 601
 602 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 603
 604         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 605         and %Q patterns.
 606
 607 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 608
 609         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 610         (print_insn_thumb32): Edit the switch case for %Z.
 611
 612 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 613
 614         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 615
 616 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 617
 618         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 619
 620 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 621
 622         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 623
 624 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 625
 626         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 627         Arm register with r13 and r15 unpredictable.
 628         (thumb32_opcodes): New instructions for bfx and bflx.
 629
 630 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 631
 632         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 633
 634 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 635
 636         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 637
 638 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 639
 640         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 641
 642 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 643
 644         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 645
 646 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 647
 648         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 649         "optr". ("operator" is a reserved word in c++).
 650
 651 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 652
 653         * aarch64-opc.c (aarch64_print_operand): Add case for
 654         AARCH64_OPND_Rt_SP.
 655         (verify_constraints): Likewise.
 656         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 657         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 658         to accept Rt|SP as first operand.
 659         (AARCH64_OPERANDS): Add new Rt_SP.
 660         * aarch64-asm-2.c: Regenerated.
 661         * aarch64-dis-2.c: Regenerated.
 662         * aarch64-opc-2.c: Regenerated.
 663
 664 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 665
 666         * aarch64-asm-2.c: Regenerated.
 667         * aarch64-dis-2.c: Likewise.
 668         * aarch64-opc-2.c: Likewise.
 669         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 670
 671 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 672
 673         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 674
 675 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 676
 677         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 678         * i386-init.h: Regenerated.
 679
 680 2019-04-07  Alan Modra  <amodra@gmail.com>
 681
 682         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 683         op_separator to control printing of spaces, comma and parens
 684         rather than need_comma, need_paren and spaces vars.
 685
 686 2019-04-07  Alan Modra  <amodra@gmail.com>
 687
 688         PR 24421
 689         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 690         (print_insn_neon, print_insn_arm): Likewise.
 691
 692 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 693
 694         * i386-dis-evex.h (evex_table): Updated to support BF16
 695         instructions.
 696         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 697         and EVEX_W_0F3872_P_3.
 698         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 699         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 700         * i386-opc.h (enum): Add CpuAVX512_BF16.
 701         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 702         * i386-opc.tbl: Add AVX512 BF16 instructions.
 703         * i386-init.h: Regenerated.
 704         * i386-tbl.h: Likewise.
 705
 706 2019-04-05  Alan Modra  <amodra@gmail.com>
 707
 708         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 709         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 710         to favour printing of "-" branch hint when using the "y" bit.
 711         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 712
 713 2019-04-05  Alan Modra  <amodra@gmail.com>
 714
 715         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 716         opcode until first operand is output.
 717
 718 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 719
 720         PR gas/24349
 721         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 722         (valid_bo_post_v2): Add support for 'at' branch hints.
 723         (insert_bo): Only error on branch on ctr.
 724         (get_bo_hint_mask): New function.
 725         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 726         for inserting 'at' branch hints.
 727         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 728         for extracting 'at' branch hints.
 729         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 730         (BOE): Delete operand.
 731         (BOM, BOP): New operands.
 732         (RM): Update value.
 733         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 734         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 735         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 736         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 737         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 738         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 739         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 740         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 741         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 742         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 743         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 744         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 745         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 746         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 747         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 748         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 749         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 750         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 751         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 752         bttarl+>: New extended mnemonics.
 753
 754 2019-03-28  Alan Modra  <amodra@gmail.com>
 755
 756         PR 24390
 757         * ppc-opc.c (BTF): Define.
 758         (powerpc_opcodes): Use for mtfsb*.
 759         * ppc-dis.c (print_insn_powerpc): Print fields with both
 760         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 761
 762 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 763
 764         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 765         (mapping_symbol_for_insn): Implement new algorithm.
 766         (print_insn): Remove duplicate code.
 767
 768 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 769
 770         * aarch64-dis.c (print_insn_aarch64):
 771         Implement override.
 772
 773 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 774
 775         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 776         order.
 777
 778 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 779
 780         * aarch64-dis.c (last_stop_offset): New.
 781         (print_insn_aarch64): Use stop_offset.
 782
 783 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 784
 785         PR gas/24359
 786         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 787         CPU_ANY_AVX2_FLAGS.
 788         * i386-init.h: Regenerated.
 789
 790 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 791
 792         PR gas/24348
 793         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 794         vmovdqu16, vmovdqu32 and vmovdqu64.
 795         * i386-tbl.h: Regenerated.
 796
 797 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 798
 799         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 800         from vstrszb, vstrszh, and vstrszf.
 801
 802 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 803
 804         * s390-opc.txt: Add instruction descriptions.
 805
 806 2019-02-08  Jim Wilson  <jimw@sifive.com>
 807
 808         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 809         <bne>: Likewise.
 810
 811 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 812
 813         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 814
 815 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 816
 817         PR binutils/23212
 818         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 819         * aarch64-opc.c (verify_elem_sd): New.
 820         (fields): Add FLD_sz entr.
 821         * aarch64-tbl.h (_SIMD_INSN): New.
 822         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 823         fmulx scalar and vector by element isns.
 824
 825 2019-02-07  Nick Clifton  <nickc@redhat.com>
 826
 827         * po/sv.po: Updated Swedish translation.
 828
 829 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 830
 831         * s390-mkopc.c (main): Accept arch13 as cpu string.
 832         * s390-opc.c: Add new instruction formats and instruction opcode
 833         masks.
 834         * s390-opc.txt: Add new arch13 instructions.
 835
 836 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 837
 838         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 839         (aarch64_opcode): Change encoding for stg, stzg
 840         st2g and st2zg.
 841         * aarch64-asm-2.c: Regenerated.
 842         * aarch64-dis-2.c: Regenerated.
 843         * aarch64-opc-2.c: Regenerated.
 844
 845 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 846
 847         * aarch64-asm-2.c: Regenerated.
 848         * aarch64-dis-2.c: Likewise.
 849         * aarch64-opc-2.c: Likewise.
 850         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 851
 852 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 853             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 854
 855         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 856         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 857         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 858         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 859         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 860         case for ldstgv_indexed.
 861         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 862         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 863         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 864         * aarch64-asm-2.c: Regenerated.
 865         * aarch64-dis-2.c: Regenerated.
 866         * aarch64-opc-2.c: Regenerated.
 867
 868 2019-01-23  Nick Clifton  <nickc@redhat.com>
 869
 870         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 871
 872 2019-01-21  Nick Clifton  <nickc@redhat.com>
 873
 874         * po/de.po: Updated German translation.
 875         * po/uk.po: Updated Ukranian translation.
 876
 877 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 878         * mips-dis.c (mips_arch_choices): Fix typo in
 879         gs464, gs464e and gs264e descriptors.
 880
 881 2019-01-19  Nick Clifton  <nickc@redhat.com>
 882
 883         * configure: Regenerate.
 884         * po/opcodes.pot: Regenerate.
 885
 886 2018-06-24  Nick Clifton  <nickc@redhat.com>
 887
 888         2.32 branch created.
 889
 890 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 891
 892         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 893         if it is null.
 894         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 895         zero.
 896
 897 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 898
 899         * configure: Regenerate.
 900
 901 2019-01-07  Alan Modra  <amodra@gmail.com>
 902
 903         * configure: Regenerate.
 904         * po/POTFILES.in: Regenerate.
 905
 906 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 907
 908         * s12z-opc.c: New file.
 909         * s12z-opc.h: New file.
 910         * s12z-dis.c: Removed all code not directly related to display
 911         of instructions.  Used the interface provided by the new files
 912         instead.
 913         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 914         * Makefile.in: Regenerate.
 915         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 916         * configure: Regenerate.
 917
 918 2019-01-01  Alan Modra  <amodra@gmail.com>
 919
 920         Update year range in copyright notice of all files.
 921
 922 For older changes see ChangeLog-2018
 923 \f
 924 Copyright (C) 2019 Free Software Foundation, Inc.
 925
 926 Copying and distribution of this file, with or without modification,
 927 are permitted in any medium without royalty provided the copyright
 928 notice and this notice are preserved.
 929
 930 Local Variables:
 931 mode: change-log
 932 left-margin: 8
 933 fill-column: 74
 934 version-control: never
 935 End: