opcodes/ChangeLog

   1 2005-02-15  Nick Clifton  <nickc@redhat.com>
   2
   3         * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
   4         compile time warnings.
   5         (print_keyword): Likewise.
   6         (default_print_insn): Likewise.
   7
   8         * fr30-desc.c: Regenerated.
   9         * fr30-desc.h: Regenerated.
  10         * fr30-dis.c: Regenerated.
  11         * fr30-opc.c: Regenerated.
  12         * fr30-opc.h: Regenerated.
  13         * frv-desc.c: Regenerated.
  14         * frv-dis.c: Regenerated.
  15         * frv-opc.c: Regenerated.
  16         * ip2k-asm.c: Regenerated.
  17         * ip2k-desc.c: Regenerated.
  18         * ip2k-desc.h: Regenerated.
  19         * ip2k-dis.c: Regenerated.
  20         * ip2k-opc.c: Regenerated.
  21         * ip2k-opc.h: Regenerated.
  22         * iq2000-desc.c: Regenerated.
  23         * iq2000-dis.c: Regenerated.
  24         * iq2000-opc.c: Regenerated.
  25         * m32r-asm.c: Regenerated.
  26         * m32r-desc.c: Regenerated.
  27         * m32r-desc.h: Regenerated.
  28         * m32r-dis.c: Regenerated.
  29         * m32r-opc.c: Regenerated.
  30         * m32r-opc.h: Regenerated.
  31         * m32r-opinst.c: Regenerated.
  32         * openrisc-desc.c: Regenerated.
  33         * openrisc-desc.h: Regenerated.
  34         * openrisc-dis.c: Regenerated.
  35         * openrisc-opc.c: Regenerated.
  36         * openrisc-opc.h: Regenerated.
  37         * xstormy16-desc.c: Regenerated.
  38         * xstormy16-desc.h: Regenerated.
  39         * xstormy16-dis.c: Regenerated.
  40         * xstormy16-opc.c: Regenerated.
  41         * xstormy16-opc.h: Regenerated.
  42
  43 2005-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  44
  45         * dis-buf.c (perror_memory): Use sprintf_vma to print out
  46         address.
  47
  48 2005-02-11  Nick Clifton  <nickc@redhat.com>
  49
  50         * iq2000-asm.c: Regenerate.
  51
  52         * frv-dis.c: Regenerate.
  53
  54 2005-02-07  Jim Blandy  <jimb@redhat.com>
  55
  56         * Makefile.am (CGEN): Load guile.scm before calling the main
  57         application script.
  58         * Makefile.in: Regenerated.
  59         * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
  60         Simply pass the cgen-opc.scm path to ${cgen} as its first
  61         argument; ${cgen} itself now contains the '-s', or whatever is
  62         appropriate for the Scheme being used.
  63
  64 2005-01-31  Andrew Cagney  <cagney@gnu.org>
  65
  66         * configure: Regenerate to track ../gettext.m4.
  67
  68 2005-01-31  Jan Beulich  <jbeulich@novell.com>
  69
  70         * ia64-gen.c (NELEMS): Define.
  71         (shrink): Generate alias with missing second predicate register when
  72         opcode has two outputs and these are both predicates.
  73         * ia64-opc-i.c (FULL17): Define.
  74         (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
  75         here to generate output template.
  76         (TBITCM, TNATCM): Undefine after use.
  77         * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
  78         first input. Add ld16 aliases without ar.csd as second output. Add
  79         st16 aliases without ar.csd as second input. Add cmpxchg aliases
  80         without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
  81         ar.ccv as third/fourth inputs. Consolidate through...
  82         (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
  83         CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
  84         * ia64-asmtab.c: Regenerate.
  85
  86 2005-01-27  Andrew Cagney  <cagney@gnu.org>
  87
  88         * configure: Regenerate to track ../gettext.m4 change.
  89
  90 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  91
  92         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  93         * frv-asm.c: Rebuilt.
  94         * frv-desc.c: Rebuilt.
  95         * frv-desc.h: Rebuilt.
  96         * frv-dis.c: Rebuilt.
  97         * frv-ibld.c: Rebuilt.
  98         * frv-opc.c: Rebuilt.
  99         * frv-opc.h: Rebuilt.
 100
 101 2005-01-24  Andrew Cagney  <cagney@gnu.org>
 102
 103         * configure: Regenerate, ../gettext.m4 was updated.
 104
 105 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 106
 107         * mips-opc.c:  Change INSN_ALIAS to INSN2_ALIAS.
 108         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 109         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 110         * mips-dis.c: Ditto.
 111
 112 2005-01-20  Alan Modra  <amodra@bigpond.net.au>
 113
 114         * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
 115
 116 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 117
 118         * mips-dis.c (no_aliases): New disassembly option flag.
 119         (set_default_mips_dis_options): Init no_aliases to zero.
 120         (parse_mips_dis_option): Handle no-aliases option.
 121         (print_insn_mips): Ignore table entries that are aliases
 122         if no_aliases is set.
 123         (print_insn_mips16): Ditto.
 124         * mips-opc.c (mips_builtin_opcodes): Add initializer column for
 125         new pinfo2 member and add INSN_ALIAS initializers as needed.  Also
 126         move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
 127         * mips16-opc.c (mips16_opcodes): Ditto.
 128
 129 2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
 130
 131         * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
 132         (inheritance diagram): Add missing edge.
 133         (arch_sh1_up): Rename arch_sh_up to match external name to make life
 134         easier for the testsuite.
 135         (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
 136         (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
 137         (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
 138         arch_sh2a_or_sh4_up child.
 139         (sh_table): Do renaming as above.
 140         Correct comment for ldc.l for gas testsuite to read.
 141         Remove rogue mul.l from sh1 (duplicate of the one for sh2).
 142         Correct comments for movy.w and movy.l for gas testsuite to read.
 143         Correct comments for fmov.d and fmov.s for gas testsuite to read.
 144
 145 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 146
 147         * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
 148
 149 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
 152
 153 2005-01-10  Andreas Schwab  <schwab@suse.de>
 154
 155         * disassemble.c (disassemble_init_for_target) <case
 156         bfd_arch_ia64>: Set skip_zeroes to 16.
 157         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
 158
 159 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
 160
 161         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
 162
 163 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
 164
 165         * avr-dis.c: Prettyprint. Added printing of symbol names in all
 166         memory references. Convert avr_operand() to C90 formatting.
 167
 168 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
 169
 170         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
 171
 172 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 173
 174         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
 175         (no_op_insn): Initialize array with instructions that have no
 176         operands.
 177         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
 178
 179 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
 180
 181         * arm-dis.c: Correct top-level comment.
 182
 183 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
 184
 185         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
 186         architecuture defining the insn.
 187         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
 188         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
 189         field.
 190         Also include opcode/arm.h.
 191         * Makefile.am (arm-dis.lo): Update dependency list.
 192         * Makefile.in: Regenerate.
 193
 194 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 195
 196         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
 197         reflect the change to the short immediate syntax.
 198
 199 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 200
 201         * or32-opc.c (debug): Warning fix.
 202         * po/POTFILES.in: Regenerate.
 203
 204         * maxq-dis.c: Formatting.
 205         (print_insn): Warning fix.
 206
 207 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
 208
 209         * arm-dis.c (WORD_ADDRESS): Define.
 210         (print_insn): Use it.  Correct big-endian end-of-section handling.
 211
 212 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 213             Vineet Sharma      <vineets@noida.hcltech.com>
 214
 215         * maxq-dis.c: New file.
 216         * disassemble.c (ARCH_maxq): Define.
 217         (disassembler): Add 'print_insn_maxq_little' for handling maxq
 218         instructions..
 219         * configure.in: Add case for bfd_maxq_arch.
 220         * configure: Regenerate.
 221         * Makefile.am: Add support for maxq-dis.c
 222         * Makefile.in: Regenerate.
 223         * aclocal.m4: Regenerate.
 224
 225 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 226
 227         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
 228         mode.
 229         * crx-dis.c: Likewise.
 230
 231 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 232
 233         Generally, handle CRISv32.
 234         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
 235         (struct cris_disasm_data): New type.
 236         (format_reg, format_hex, cris_constraint, print_flags)
 237         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
 238         callers changed.
 239         (format_sup_reg, print_insn_crisv32_with_register_prefix)
 240         (print_insn_crisv32_without_register_prefix)
 241         (print_insn_crisv10_v32_with_register_prefix)
 242         (print_insn_crisv10_v32_without_register_prefix)
 243         (cris_parse_disassembler_options): New functions.
 244         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
 245         parameter.  All callers changed.
 246         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
 247         failure.
 248         (cris_constraint) <case 'Y', 'U'>: New cases.
 249         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
 250         for constraint 'n'.
 251         (print_with_operands) <case 'Y'>: New case.
 252         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 253         <case 'N', 'Y', 'Q'>: New cases.
 254         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 255         (print_insn_cris_with_register_prefix)
 256         (print_insn_cris_without_register_prefix): Call
 257         cris_parse_disassembler_options.
 258         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 259         for CRISv32 and the size of immediate operands.  New v32-only
 260         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 261         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 262         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 263         Change brp to be v3..v10.
 264         (cris_support_regs): New vector.
 265         (cris_opcodes): Update head comment.  New format characters '[',
 266         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 267         Add new opcodes for v32 and adjust existing opcodes to accommodate
 268         differences to earlier variants.
 269         (cris_cond15s): New vector.
 270
 271 2004-11-04 Jan Beulich <jbeulich@novell.com>
 272
 273         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 274         (indirEb): Remove.
 275         (Mp): Use f_mode rather than none at all.
 276         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 277         replaces what previously was x_mode; x_mode now means 128-bit SSE
 278         operands.
 279         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 280         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 281         pinsrw's second operand is Edqw.
 282         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 283         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 284         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 285         mode when an operand size override is present or always suffixing.
 286         More instructions will need to be added to this group.
 287         (putop): Handle new macro chars 'C' (short/long suffix selector),
 288         'I' (Intel mode override for following macro char), and 'J' (for
 289         adding the 'l' prefix to far branches in AT&T mode). When an
 290         alternative was specified in the template, honor macro character when
 291         specified for Intel mode.
 292         (OP_E): Handle new *_mode values. Correct pointer specifications for
 293         memory operands. Consolidate output of index register.
 294         (OP_G): Handle new *_mode values.
 295         (OP_I): Handle const_1_mode.
 296         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 297         respective opcode prefix bits have been consumed.
 298         (OP_EM, OP_EX): Provide some default handling for generating pointer
 299         specifications.
 300
 301 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 302
 303         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 304         COP_INST macro.
 305
 306 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 307
 308         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 309         (getregliststring): Support HI/LO and user registers.
 310         * crx-opc.c (crx_instruction): Update data structure according to the
 311         rearrangement done in CRX opcode header file.
 312         (crx_regtab):  Likewise.
 313         (crx_optab):  Likewise.
 314         (crx_instruction): Reorder load/stor instructions, remove unsupported
 315         formats.
 316         support new Co-Processor instruction 'cpi'.
 317
 318 2004-10-27  Nick Clifton  <nickc@redhat.com>
 319
 320         * opcodes/iq2000-asm.c: Regenerate.
 321         * opcodes/iq2000-desc.c: Regenerate.
 322         * opcodes/iq2000-desc.h: Regenerate.
 323         * opcodes/iq2000-dis.c: Regenerate.
 324         * opcodes/iq2000-ibld.c: Regenerate.
 325         * opcodes/iq2000-opc.c: Regenerate.
 326         * opcodes/iq2000-opc.h: Regenerate.
 327
 328 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 329
 330         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 331         us4, us5 (respectively).
 332         Remove unsupported 'popa' instruction.
 333         Reverse operands order in store co-processor instructions.
 334
 335 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 336
 337         * Makefile.am: Run "make dep-am"
 338         * Makefile.in: Regenerate.
 339
 340 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 341
 342         * xtensa-dis.c: Use ISO C90 formatting.
 343
 344 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 345
 346         * ppc-opc.c: Revert 2004-09-09 change.
 347
 348 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 349
 350         * xtensa-dis.c (state_names): Delete.
 351         (fetch_data): Use xtensa_isa_maxlength.
 352         (print_xtensa_operand): Replace operand parameter with opcode/operand
 353         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 354         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 355         instruction bundles.  Use xmalloc instead of malloc.
 356
 357 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 358
 359         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 360         initializers.
 361
 362 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 363
 364         * crx-opc.c (crx_instruction): Support Co-processor insns.
 365         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 366         (getregliststring): Change function to use the above enum.
 367         (print_arg): Handle CO-Processor insns.
 368         (crx_cinvs): Add 'b' option to invalidate the branch-target
 369         cache.
 370
 371 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 372
 373         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 374         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 375         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 376         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 377         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 378
 379 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 380
 381         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 382         rather than add it.
 383
 384 2004-09-30  Paul Brook  <paul@codesourcery.com>
 385
 386         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 387         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 388
 389 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 390
 391         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 392         (CONFIG_STATUS_DEPENDENCIES): New.
 393         (Makefile): Removed.
 394         (config.status): Likewise.
 395         * Makefile.in: Regenerated.
 396
 397 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 398
 399         * Makefile.am: Run "make dep-am".
 400         * Makefile.in: Regenerate.
 401         * aclocal.m4: Regenerate.
 402         * configure: Regenerate.
 403         * po/POTFILES.in: Regenerate.
 404         * po/opcodes.pot: Regenerate.
 405
 406 2004-09-11  Andreas Schwab  <schwab@suse.de>
 407
 408         * configure: Rebuild.
 409
 410 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 411
 412         * ppc-opc.c (L): Make this field not optional.
 413
 414 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 415
 416         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 417         Fix parameter to 'm[t|f]csr' insns.
 418
 419 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 420
 421         * configure.in: Autoupdate to autoconf 2.59.
 422         * aclocal.m4: Rebuild with aclocal 1.4p6.
 423         * configure: Rebuild with autoconf 2.59.
 424         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 425         bfd changes for autoconf 2.59 on the way).
 426         * config.in: Rebuild with autoheader 2.59.
 427
 428 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 429
 430         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 431
 432 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 433
 434         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 435         (GRPPADLCK2): New define.
 436         (twobyte_has_modrm): True for 0xA6.
 437         (grps): GRPPADLCK2 for opcode 0xA6.
 438
 439 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 440
 441         Introduce SH2a support.
 442         * sh-opc.h (arch_sh2a_base): Renumber.
 443         (arch_sh2a_nofpu_base): Remove.
 444         (arch_sh_base_mask): Adjust.
 445         (arch_opann_mask): New.
 446         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 447         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 448         (sh_table): Adjust whitespace.
 449         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 450         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 451         instruction list throughout.
 452         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 453         of arch_sh2a in instruction list throughout.
 454         (arch_sh2e_up): Accomodate above changes.
 455         (arch_sh2_up): Ditto.
 456         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 457         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 458         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 459         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 460         * sh-opc.h (arch_sh2a_nofpu): New.
 461         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 462         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 463         instruction.
 464         2004-01-20  DJ Delorie  <dj@redhat.com>
 465         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 466         2003-12-29  DJ Delorie  <dj@redhat.com>
 467         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 468         sh_opcode_info, sh_table): Add sh2a support.
 469         (arch_op32): New, to tag 32-bit opcodes.
 470         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 471         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 472         * sh-opc.h (arch_sh2a): Add.
 473         * sh-dis.c (arch_sh2a): Handle.
 474         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 475
 476 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 477
 478         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 479
 480 2004-07-22  Nick Clifton  <nickc@redhat.com>
 481
 482         PR/280
 483         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 484         insns - this is done by objdump itself.
 485         * h8500-dis.c (print_insn_h8500): Likewise.
 486
 487 2004-07-21  Jan Beulich <jbeulich@novell.com>
 488
 489         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 490         regardless of address size prefix in effect.
 491         (ptr_reg): Size or address registers does not depend on rex64, but
 492         on the presence of an address size override.
 493         (OP_MMX): Use rex.x only for xmm registers.
 494         (OP_EM): Use rex.z only for xmm registers.
 495
 496 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 497
 498         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 499         move/branch operations to the bottom so that VR5400 multimedia
 500         instructions take precedence in disassembly.
 501
 502 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 503
 504         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 505         ISA-specific "break" encoding.
 506
 507 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 508
 509         * arm-opc.h: Fix typo in comment.
 510
 511 2004-07-11  Andreas Schwab  <schwab@suse.de>
 512
 513         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 514
 515 2004-07-09  Andreas Schwab  <schwab@suse.de>
 516
 517         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 518
 519 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 520
 521         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 522         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 523         (crx-dis.lo): New target.
 524         (crx-opc.lo): Likewise.
 525         * Makefile.in: Regenerate.
 526         * configure.in: Handle bfd_crx_arch.
 527         * configure: Regenerate.
 528         * crx-dis.c: New file.
 529         * crx-opc.c: New file.
 530         * disassemble.c (ARCH_crx): Define.
 531         (disassembler): Handle ARCH_crx.
 532
 533 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 534
 535         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 536         * ia64-asmtab.c: Regnerate.
 537
 538 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 539
 540         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 541         (extract_fxm): Don't test dialect.
 542         (XFXFXM_MASK): Include the power4 bit.
 543         (XFXM): Add p4 param.
 544         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 545
 546 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 547
 548         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 549         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 550
 551 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 552
 553         * ppc-opc.c (BH, XLBH_MASK): Define.
 554         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 555
 556 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 557
 558         * i386-dis.c (x_mode): Comment.
 559         (two_source_ops): File scope.
 560         (float_mem): Correct fisttpll and fistpll.
 561         (float_mem_mode): New table.
 562         (dofloat): Use it.
 563         (OP_E): Correct intel mode PTR output.
 564         (ptr_reg): Use open_char and close_char.
 565         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 566         operands.  Set two_source_ops.
 567
 568 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 569
 570         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 571         instead of _raw_size.
 572
 573 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 574
 575         * ia64-gen.c (in_iclass): Handle more postinc st
 576         and ld variants.
 577         * ia64-asmtab.c: Rebuilt.
 578
 579 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 580
 581         * s390-opc.txt: Correct architecture mask for some opcodes.
 582         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 583         in the esa mode as well.
 584
 585 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 586
 587         * sh-dis.c (target_arch): Make unsigned.
 588         (print_insn_sh): Replace (most of) switch with a call to
 589         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 590         * sh-opc.h: Redefine architecture flags values.
 591         Add sh3-nommu architecture.
 592         Reorganise <arch>_up macros so they make more visual sense.
 593         (SH_MERGE_ARCH_SET): Define new macro.
 594         (SH_VALID_BASE_ARCH_SET): Likewise.
 595         (SH_VALID_MMU_ARCH_SET): Likewise.
 596         (SH_VALID_CO_ARCH_SET): Likewise.
 597         (SH_VALID_ARCH_SET): Likewise.
 598         (SH_MERGE_ARCH_SET_VALID): Likewise.
 599         (SH_ARCH_SET_HAS_FPU): Likewise.
 600         (SH_ARCH_SET_HAS_DSP): Likewise.
 601         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 602         (sh_get_arch_from_bfd_mach): Add prototype.
 603         (sh_get_arch_up_from_bfd_mach): Likewise.
 604         (sh_get_bfd_mach_from_arch_set): Likewise.
 605         (sh_merge_bfd_arc): Likewise.
 606
 607 2004-05-24  Peter Barada  <peter@the-baradas.com>
 608
 609         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 610         into new match_insn_m68k function.  Loop over canidate
 611         matches and select first that completely matches.
 612         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 613         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 614         to verify addressing for MAC/EMAC.
 615         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 616         reigster halves since 'fpu' and 'spl' look misleading.
 617         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 618         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 619         first, tighten up match masks.
 620         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 621         'size' from special case code in print_insn_m68k to
 622         determine decode size of insns.
 623
 624 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 625
 626         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 627         well as when -mpower4.
 628
 629 2004-05-13  Nick Clifton  <nickc@redhat.com>
 630
 631         * po/fr.po: Updated French translation.
 632
 633 2004-05-05  Peter Barada  <peter@the-baradas.com>
 634
 635         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 636         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 637         * m68k-op.c: Switch from ColdFire chips to core variants.
 638
 639 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 640
 641         PR 147.
 642         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 643
 644 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 645
 646         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 647         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 648
 649 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 650
 651         * sh-dis.c (print_insn_sh): Print the value in constant pool
 652         as a symbol if it looks like a symbol.
 653
 654 2004-04-22  Peter Barada <peter@the-baradas.com>
 655
 656         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 657         appropriate ColdFire architectures.
 658         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 659         mask addressing.
 660         Add EMAC instructions, fix MAC instructions. Remove
 661         macmw/macml/msacmw/msacml instructions since mask addressing now
 662         supported.
 663
 664 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 665
 666         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 667         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 668         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 669         macro.  Adjust all users.
 670
 671 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 672
 673         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 674         separately.
 675
 676 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 677
 678         * m32r-asm.c: Regenerate.
 679
 680 2004-03-29  Stan Shebs  <shebs@apple.com>
 681
 682         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 683         used.
 684
 685 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 686
 687         * aclocal.m4: Regenerate.
 688         * config.in: Regenerate.
 689         * configure: Regenerate.
 690         * po/POTFILES.in: Regenerate.
 691         * po/opcodes.pot: Regenerate.
 692
 693 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 694
 695         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 696         PPC_OPERANDS_GPR_0.
 697         * ppc-opc.c (RA0): Define.
 698         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 699         (RAOPT): Rename from RAO.  Update all uses.
 700         (powerpc_opcodes): Use RA0 as appropriate.
 701
 702 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 703
 704         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 705
 706 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 707
 708         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 709
 710 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 711
 712         * i386-dis.c (GRPPLOCK): Delete.
 713         (grps): Delete GRPPLOCK entry.
 714
 715 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 716
 717         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 718         (M, Mp): Use OP_M.
 719         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 720         (GRPPADLCK): Define.
 721         (dis386): Use NOP_Fixup on "nop".
 722         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 723         (twobyte_has_modrm): Set for 0xa7.
 724         (padlock_table): Delete.  Move to..
 725         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 726         and clflush.
 727         (print_insn): Revert PADLOCK_SPECIAL code.
 728         (OP_E): Delete sfence, lfence, mfence checks.
 729
 730 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 731
 732         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 733         (INVLPG_Fixup): New function.
 734         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 735
 736 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 737
 738         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 739         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 740         (padlock_table): New struct with PadLock instructions.
 741         (print_insn): Handle PADLOCK_SPECIAL.
 742
 743 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 744
 745         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 746         (OP_E): Twiddle clflush to sfence here.
 747
 748 2004-03-08  Nick Clifton  <nickc@redhat.com>
 749
 750         * po/de.po: Updated German translation.
 751
 752 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 753
 754         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 755         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 756         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 757         accordingly.
 758
 759 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 760
 761         * frv-asm.c: Regenerate.
 762         * frv-desc.c: Regenerate.
 763         * frv-desc.h: Regenerate.
 764         * frv-dis.c: Regenerate.
 765         * frv-ibld.c: Regenerate.
 766         * frv-opc.c: Regenerate.
 767         * frv-opc.h: Regenerate.
 768
 769 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 770
 771         * frv-desc.c, frv-opc.c: Regenerate.
 772
 773 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 774
 775         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 776
 777 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 778
 779         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 780         Also correct mistake in the comment.
 781
 782 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 783
 784         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 785         ensure that double registers have even numbers.
 786         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 787         that reserved instruction 0xfffd does not decode the same
 788         as 0xfdfd (ftrv).
 789         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 790         REG_N refers to a double register.
 791         Add REG_N_B01 nibble type and use it instead of REG_NM
 792         in ftrv.
 793         Adjust the bit patterns in a few comments.
 794
 795 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 796
 797         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 798
 799 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 800
 801         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 802
 803 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 804
 805         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 806
 807 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 808
 809         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 810         mtivor32, mtivor33, mtivor34.
 811
 812 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 813
 814         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 815
 816 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 817
 818         * arm-opc.h Maverick accumulator register opcode fixes.
 819
 820 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 821
 822         * m32r-dis.c: Regenerate.
 823
 824 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 825
 826         * sh-opc.h (sh_table): "fsrra", not "fssra".
 827
 828 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 829
 830         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 831         contraints.
 832
 833 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 834
 835         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 836
 837 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 838
 839         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 840         1.  Don't print scale factor on AT&T mode when index missing.
 841
 842 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 843
 844         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 845         when loaded into XR registers.
 846
 847 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 848
 849         * frv-desc.h: Regenerate.
 850         * frv-desc.c: Regenerate.
 851         * frv-opc.c: Regenerate.
 852
 853 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 854
 855         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 856
 857 2004-01-09  Paul Brook  <paul@codesourcery.com>
 858
 859         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 860         specific opcodes.
 861
 862 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 863
 864         * Makefile.am (libopcodes_la_DEPENDENCIES)
 865         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 866         comment about the problem.
 867         * Makefile.in: Regenerate.
 868
 869 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 870
 871         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 872         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 873         cut&paste errors in shifting/truncating numerical operands.
 874         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 875         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 876         (parse_uslo16): Likewise.
 877         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 878         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 879         (parse_s12): Likewise.
 880         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 881         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 882         (parse_uslo16): Likewise.
 883         (parse_uhi16): Parse gothi and gotfuncdeschi.
 884         (parse_d12): Parse got12 and gotfuncdesc12.
 885         (parse_s12): Likewise.
 886
 887 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 888
 889         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 890         instruction which looks similar to an 'rla' instruction.
 891
 892 For older changes see ChangeLog-0203
 893 \f
 894 Local Variables:
 895 mode: change-log
 896 left-margin: 8
 897 fill-column: 74
 898 version-control: never
 899 End: