1 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
3 * aarch64-asm.c: Include libiberty.h.
4 (insert_fields): New function.
5 (aarch64_ins_imm): Use it.
6 * aarch64-dis.c (extract_fields): New function.
7 (aarch64_ext_imm): Use it.
9 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
11 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
12 with an esize parameter.
13 (operand_general_constraint_met_p): Update accordingly.
15 * aarch64-asm.c (aarch64_ins_limm): Update call to
16 aarch64_logical_immediate_p.
18 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
20 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
22 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
24 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
26 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
28 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
30 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
32 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
33 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
34 xor3>: Delete mnemonics.
35 <cp_abort>: Rename mnemonic from ...
36 <cpabort>: ...to this.
37 <setb>: Change to a X form instruction.
38 <sync>: Change to 1 operand form.
39 <copy>: Delete mnemonic.
40 <copy_first>: Rename mnemonic from ...
42 <paste, paste.>: Delete mnemonics.
43 <paste_last>: Rename mnemonic from ...
46 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
48 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
50 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
52 * s390-mkopc.c (main): Support alternate arch strings.
54 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
56 * s390-opc.txt: Fix kmctr instruction type.
58 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
60 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
61 * i386-init.h: Regenerated.
63 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
65 * opcodes/arc-dis.c (print_insn_arc): Changed.
67 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
69 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
72 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
74 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
75 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
76 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
78 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
80 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
81 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
82 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
83 PREFIX_MOD_3_0FAE_REG_4.
84 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
85 PREFIX_MOD_3_0FAE_REG_4.
86 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
87 (cpu_flags): Add CpuPTWRITE.
88 * i386-opc.h (CpuPTWRITE): New.
89 (i386_cpu_flags): Add cpuptwrite.
90 * i386-opc.tbl: Add ptwrite instruction.
91 * i386-init.h: Regenerated.
92 * i386-tbl.h: Likewise.
94 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
96 * arc-dis.h: Wrap around in extern "C".
98 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
100 * aarch64-tbl.h (V8_2_INSN): New macro.
101 (aarch64_opcode_table): Use it.
103 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
105 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
106 CORE_INSN, __FP_INSN and SIMD_INSN.
108 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
110 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
111 (aarch64_opcode_table): Update uses accordingly.
113 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
114 Kwok Cheung Yeung <kcy@codesourcery.com>
117 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
118 'e_cmplwi' to 'e_cmpli' instead.
119 (OPVUPRT, OPVUPRT_MASK): Define.
120 (powerpc_opcodes): Add E200Z4 insns.
121 (vle_opcodes): Add context save/restore insns.
123 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
125 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
126 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
129 2016-07-27 Graham Markall <graham.markall@embecosm.com>
131 * arc-nps400-tbl.h: Change block comments to GNU format.
132 * arc-dis.c: Add new globals addrtypenames,
133 addrtypenames_max, and addtypeunknown.
134 (get_addrtype): New function.
135 (print_insn_arc): Print colons and address types when
137 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
138 define insert and extract functions for all address types.
139 (arc_operands): Add operands for colon and all address
141 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
142 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
143 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
144 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
145 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
146 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
148 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
150 * configure: Regenerated.
152 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
154 * arc-dis.c (skipclass): New structure.
155 (decodelist): New variable.
156 (is_compatible_p): New function.
157 (new_element): Likewise.
158 (skip_class_p): Likewise.
159 (find_format_from_table): Use skip_class_p function.
160 (find_format): Decode first the extension instructions.
161 (print_insn_arc): Select either ARCEM or ARCHS based on elf
163 (parse_option): New function.
164 (parse_disassembler_options): Likewise.
165 (print_arc_disassembler_options): Likewise.
166 (print_insn_arc): Use parse_disassembler_options function. Proper
167 select ARCv2 cpu variant.
168 * disassemble.c (disassembler_usage): Add ARC disassembler
171 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
173 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
174 annotation from the "nal" entry and reorder it beyond "bltzal".
176 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
178 * sparc-opc.c (ldtxa): New macro.
179 (sparc_opcodes): Use the macro defined above to add entries for
180 the LDTXA instructions.
181 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
184 2016-07-07 James Bowman <james.bowman@ftdichip.com>
186 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
189 2016-07-01 Jan Beulich <jbeulich@suse.com>
191 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
192 (movzb): Adjust to cover all permitted suffixes.
194 * i386-tbl.h: Re-generate.
196 2016-07-01 Jan Beulich <jbeulich@suse.com>
198 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
199 (lgdt): Remove Tbyte from non-64-bit variant.
200 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
201 xsaves64, xsavec64): Remove Disp16.
202 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
203 Remove Disp32S from non-64-bit variants. Remove Disp16 from
205 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
206 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
207 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
209 * i386-tbl.h: Re-generate.
211 2016-07-01 Jan Beulich <jbeulich@suse.com>
213 * i386-opc.tbl (xlat): Remove RepPrefixOk.
214 * i386-tbl.h: Re-generate.
216 2016-06-30 Yao Qi <yao.qi@linaro.org>
218 * arm-dis.c (print_insn): Fix typo in comment.
220 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
222 * aarch64-opc.c (operand_general_constraint_met_p): Check the
223 range of ldst_elemlist operands.
224 (print_register_list): Use PRIi64 to print the index.
225 (aarch64_print_operand): Likewise.
227 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
229 * mcore-opc.h: Remove sentinal.
230 * mcore-dis.c (print_insn_mcore): Adjust.
232 2016-06-23 Graham Markall <graham.markall@embecosm.com>
234 * arc-opc.c: Correct description of availability of NPS400
237 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
239 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
240 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
241 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
242 xor3>: New mnemonics.
243 <setb>: Change to a VX form instruction.
244 (insert_sh6): Add support for rldixor.
245 (extract_sh6): Likewise.
247 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
249 * arc-ext.h: Wrap in extern C.
251 2016-06-21 Graham Markall <graham.markall@embecosm.com>
253 * arc-dis.c (arc_insn_length): Add comment on instruction length.
254 Use same method for determining instruction length on ARC700 and
256 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
257 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
258 with the NPS400 subclass.
259 * arc-opc.c: Likewise.
261 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
263 * sparc-opc.c (rdasr): New macro.
269 (sparc_opcodes): Use the macros above to fix and expand the
270 definition of read/write instructions from/to
271 asr/privileged/hyperprivileged instructions.
272 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
273 %hva_mask_nz. Prefer softint_set and softint_clear over
274 set_softint and clear_softint.
275 (print_insn_sparc): Support %ver in Rd.
277 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
279 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
280 architecture according to the hardware capabilities they require.
282 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
284 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
285 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
286 bfd_mach_sparc_v9{c,d,e,v,m}.
287 * sparc-opc.c (MASK_V9C): Define.
288 (MASK_V9D): Likewise.
289 (MASK_V9E): Likewise.
290 (MASK_V9V): Likewise.
291 (MASK_V9M): Likewise.
292 (v6): Add MASK_V9{C,D,E,V,M}.
293 (v6notlet): Likewise.
297 (v9andleon): Likewise.
305 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
307 2016-06-15 Nick Clifton <nickc@redhat.com>
309 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
310 constants to match expected behaviour.
311 (nds32_parse_opcode): Likewise. Also for whitespace.
313 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
315 * arc-opc.c (extract_rhv1): Extract value from insn.
317 2016-06-14 Graham Markall <graham.markall@embecosm.com>
319 * arc-nps400-tbl.h: Add ldbit instruction.
320 * arc-opc.c: Add flag classes required for ldbit.
322 2016-06-14 Graham Markall <graham.markall@embecosm.com>
324 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
325 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
326 support the above instructions.
328 2016-06-14 Graham Markall <graham.markall@embecosm.com>
330 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
331 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
332 csma, cbba, zncv, and hofs.
333 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
334 support the above instructions.
336 2016-06-06 Graham Markall <graham.markall@embecosm.com>
338 * arc-nps400-tbl.h: Add andab and orab instructions.
340 2016-06-06 Graham Markall <graham.markall@embecosm.com>
342 * arc-nps400-tbl.h: Add addl-like instructions.
344 2016-06-06 Graham Markall <graham.markall@embecosm.com>
346 * arc-nps400-tbl.h: Add mxb and imxb instructions.
348 2016-06-06 Graham Markall <graham.markall@embecosm.com>
350 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
353 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
355 * s390-dis.c (option_use_insn_len_bits_p): New file scope
357 (init_disasm): Handle new command line option "insnlength".
358 (print_s390_disassembler_options): Mention new option in help
360 (print_insn_s390): Use the encoded insn length when dumping
361 unknown instructions.
363 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
365 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
366 to the address and set as symbol address for LDS/ STS immediate operands.
368 2016-06-07 Alan Modra <amodra@gmail.com>
370 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
371 cpu for "vle" to e500.
372 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
373 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
374 (PPCNONE): Delete, substitute throughout.
375 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
376 except for major opcode 4 and 31.
377 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
379 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
381 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
382 ARM_EXT_RAS in relevant entries.
384 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
387 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
390 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
395 Add comments for '&'.
396 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
398 (intel_operand_size): Handle indir_v_mode.
399 (OP_E_register): Likewise.
400 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
401 64-bit indirect call/jmp for AMD64.
402 * i386-tbl.h: Regenerated
404 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
406 * arc-dis.c (struct arc_operand_iterator): New structure.
407 (find_format_from_table): All the old content from find_format,
408 with some minor adjustments, and parameter renaming.
409 (find_format_long_instructions): New function.
410 (find_format): Rewritten.
411 (arc_insn_length): Add LSB parameter.
412 (extract_operand_value): New function.
413 (operand_iterator_next): New function.
414 (print_insn_arc): Use new functions to find opcode, and iterator
416 * arc-opc.c (insert_nps_3bit_dst_short): New function.
417 (extract_nps_3bit_dst_short): New function.
418 (insert_nps_3bit_src2_short): New function.
419 (extract_nps_3bit_src2_short): New function.
420 (insert_nps_bitop1_size): New function.
421 (extract_nps_bitop1_size): New function.
422 (insert_nps_bitop2_size): New function.
423 (extract_nps_bitop2_size): New function.
424 (insert_nps_bitop_mod4_msb): New function.
425 (extract_nps_bitop_mod4_msb): New function.
426 (insert_nps_bitop_mod4_lsb): New function.
427 (extract_nps_bitop_mod4_lsb): New function.
428 (insert_nps_bitop_dst_pos3_pos4): New function.
429 (extract_nps_bitop_dst_pos3_pos4): New function.
430 (insert_nps_bitop_ins_ext): New function.
431 (extract_nps_bitop_ins_ext): New function.
432 (arc_operands): Add new operands.
433 (arc_long_opcodes): New global array.
434 (arc_num_long_opcodes): New global.
435 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
437 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
439 * nds32-asm.h: Add extern "C".
440 * sh-opc.h: Likewise.
442 2016-06-01 Graham Markall <graham.markall@embecosm.com>
444 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
445 0,b,limm to the rflt instruction.
447 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
449 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
452 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
455 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
456 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
457 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
458 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
459 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
460 * i386-init.h: Regenerated.
462 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
465 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
466 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
467 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
468 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
469 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
470 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
471 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
472 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
473 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
474 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
475 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
476 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
477 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
478 CpuRegMask for AVX512.
479 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
481 (set_bitfield_from_cpu_flag_init): New function.
482 (set_bitfield): Remove const on f. Call
483 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
484 * i386-opc.h (CpuRegMMX): New.
485 (CpuRegXMM): Likewise.
486 (CpuRegYMM): Likewise.
487 (CpuRegZMM): Likewise.
488 (CpuRegMask): Likewise.
489 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
491 * i386-init.h: Regenerated.
492 * i386-tbl.h: Likewise.
494 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
498 (opcode_modifiers): Add AMD64 and Intel64.
499 (main): Properly verify CpuMax.
500 * i386-opc.h (CpuAMD64): Removed.
501 (CpuIntel64): Likewise.
502 (CpuMax): Set to CpuNo64.
503 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
506 (i386_opcode_modifier): Add amd64 and intel64.
507 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
509 * i386-init.h: Regenerated.
510 * i386-tbl.h: Likewise.
512 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
515 * i386-gen.c (main): Fail if CpuMax is incorrect.
516 * i386-opc.h (CpuMax): Set to CpuIntel64.
517 * i386-tbl.h: Regenerated.
519 2016-05-27 Nick Clifton <nickc@redhat.com>
522 * msp430-dis.c (msp430dis_read_two_bytes): New function.
523 (msp430dis_opcode_unsigned): New function.
524 (msp430dis_opcode_signed): New function.
525 (msp430_singleoperand): Use the new opcode reading functions.
526 Only disassenmble bytes if they were successfully read.
527 (msp430_doubleoperand): Likewise.
528 (msp430_branchinstr): Likewise.
529 (msp430x_callx_instr): Likewise.
530 (print_insn_msp430): Check that it is safe to read bytes before
531 attempting disassembly. Use the new opcode reading functions.
533 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
535 * ppc-opc.c (CY): New define. Document it.
536 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
538 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
540 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
541 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
542 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
543 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
545 * i386-init.h: Regenerated.
547 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
550 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
551 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
552 * i386-init.h: Regenerated.
554 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
556 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
557 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
558 * i386-init.h: Regenerated.
560 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
562 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
564 (print_insn_arc): Set insn_type information.
565 * arc-opc.c (C_CC): Add F_CLASS_COND.
566 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
567 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
568 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
569 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
570 (brne, brne_s, jeq_s, jne_s): Likewise.
572 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
574 * arc-tbl.h (neg): New instruction variant.
576 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
578 * arc-dis.c (find_format, find_format, get_auxreg)
579 (print_insn_arc): Changed.
580 * arc-ext.h (INSERT_XOP): Likewise.
582 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
584 * tic54x-dis.c (sprint_mmr): Adjust.
585 * tic54x-opc.c: Likewise.
587 2016-05-19 Alan Modra <amodra@gmail.com>
589 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
591 2016-05-19 Alan Modra <amodra@gmail.com>
593 * ppc-opc.c: Formatting.
594 (NSISIGNOPT): Define.
595 (powerpc_opcodes <subis>): Use NSISIGNOPT.
597 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
599 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
600 replacing references to `micromips_ase' throughout.
601 (_print_insn_mips): Don't use file-level microMIPS annotation to
602 determine the disassembly mode with the symbol table.
604 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
606 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
608 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
610 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
612 * mips-opc.c (D34): New macro.
613 (mips_builtin_opcodes): Define bposge32c for DSPr3.
615 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
617 * i386-dis.c (prefix_table): Add RDPID instruction.
618 * i386-gen.c (cpu_flag_init): Add RDPID flag.
619 (cpu_flags): Add RDPID bitfield.
620 * i386-opc.h (enum): Add RDPID element.
621 (i386_cpu_flags): Add RDPID field.
622 * i386-opc.tbl: Add RDPID instruction.
623 * i386-init.h: Regenerate.
624 * i386-tbl.h: Regenerate.
626 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
628 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
629 branch type of a symbol.
630 (print_insn): Likewise.
632 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
634 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
635 Mainline Security Extensions instructions.
636 (thumb_opcodes): Add entries for narrow ARMv8-M Security
637 Extensions instructions.
638 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
640 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
643 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
645 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
647 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
649 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
650 (arcExtMap_genOpcode): Likewise.
651 * arc-opc.c (arg_32bit_rc): Define new variable.
652 (arg_32bit_u6): Likewise.
653 (arg_32bit_limm): Likewise.
655 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
657 * aarch64-gen.c (VERIFIER): Define.
658 * aarch64-opc.c (VERIFIER): Define.
659 (verify_ldpsw): Use static linkage.
660 * aarch64-opc.h (verify_ldpsw): Remove.
661 * aarch64-tbl.h: Use VERIFIER for verifiers.
663 2016-04-28 Nick Clifton <nickc@redhat.com>
666 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
667 * aarch64-opc.c (verify_ldpsw): New function.
668 * aarch64-opc.h (verify_ldpsw): New prototype.
669 * aarch64-tbl.h: Add initialiser for verifier field.
670 (LDPSW): Set verifier to verify_ldpsw.
672 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
676 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
677 smaller than address size.
679 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
681 * alpha-dis.c: Regenerate.
682 * crx-dis.c: Likewise.
683 * disassemble.c: Likewise.
684 * epiphany-opc.c: Likewise.
685 * fr30-opc.c: Likewise.
686 * frv-opc.c: Likewise.
687 * ip2k-opc.c: Likewise.
688 * iq2000-opc.c: Likewise.
689 * lm32-opc.c: Likewise.
690 * lm32-opinst.c: Likewise.
691 * m32c-opc.c: Likewise.
692 * m32r-opc.c: Likewise.
693 * m32r-opinst.c: Likewise.
694 * mep-opc.c: Likewise.
695 * mt-opc.c: Likewise.
696 * or1k-opc.c: Likewise.
697 * or1k-opinst.c: Likewise.
698 * tic80-opc.c: Likewise.
699 * xc16x-opc.c: Likewise.
700 * xstormy16-opc.c: Likewise.
702 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
704 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
705 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
706 calcsd, and calcxd instructions.
707 * arc-opc.c (insert_nps_bitop_size): Delete.
708 (extract_nps_bitop_size): Delete.
709 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
710 (extract_nps_qcmp_m3): Define.
711 (extract_nps_qcmp_m2): Define.
712 (extract_nps_qcmp_m1): Define.
713 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
714 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
715 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
716 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
717 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
720 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
722 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
724 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
726 * Makefile.in: Regenerated with automake 1.11.6.
727 * aclocal.m4: Likewise.
729 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
731 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
733 * arc-opc.c (insert_nps_cmem_uimm16): New function.
734 (extract_nps_cmem_uimm16): New function.
735 (arc_operands): Add NPS_XLDST_UIMM16 operand.
737 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
739 * arc-dis.c (arc_insn_length): New function.
740 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
741 (find_format): Change insnLen parameter to unsigned.
743 2016-04-13 Nick Clifton <nickc@redhat.com>
746 * v850-opc.c (v850_opcodes): Correct masks for long versions of
747 the LD.B and LD.BU instructions.
749 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
751 * arc-dis.c (find_format): Check for extension flags.
752 (print_flags): New function.
753 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
755 * arc-ext.c (arcExtMap_coreRegName): Use
756 LAST_EXTENSION_CORE_REGISTER.
757 (arcExtMap_coreReadWrite): Likewise.
758 (dump_ARC_extmap): Update printing.
759 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
760 (arc_aux_regs): Add cpu field.
761 * arc-regs.h: Add cpu field, lower case name aux registers.
763 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
765 * arc-tbl.h: Add rtsc, sleep with no arguments.
767 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
769 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
771 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
772 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
773 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
774 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
775 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
776 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
777 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
778 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
779 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
780 (arc_opcode arc_opcodes): Null terminate the array.
781 (arc_num_opcodes): Remove.
782 * arc-ext.h (INSERT_XOP): Define.
783 (extInstruction_t): Likewise.
784 (arcExtMap_instName): Delete.
785 (arcExtMap_insn): New function.
786 (arcExtMap_genOpcode): Likewise.
787 * arc-ext.c (ExtInstruction): Remove.
788 (create_map): Zero initialize instruction fields.
789 (arcExtMap_instName): Remove.
790 (arcExtMap_insn): New function.
791 (dump_ARC_extmap): More info while debuging.
792 (arcExtMap_genOpcode): New function.
793 * arc-dis.c (find_format): New function.
794 (print_insn_arc): Use find_format.
795 (arc_get_disassembler): Enable dump_ARC_extmap only when
798 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
800 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
801 instruction bits out.
803 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
805 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
806 * arc-opc.c (arc_flag_operands): Add new flags.
807 (arc_flag_classes): Add new classes.
809 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
811 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
813 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
815 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
816 encode1, rflt, crc16, and crc32 instructions.
817 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
818 (arc_flag_classes): Add C_NPS_R.
819 (insert_nps_bitop_size_2b): New function.
820 (extract_nps_bitop_size_2b): Likewise.
821 (insert_nps_bitop_uimm8): Likewise.
822 (extract_nps_bitop_uimm8): Likewise.
823 (arc_operands): Add new operand entries.
825 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
827 * arc-regs.h: Add a new subclass field. Add double assist
828 accumulator register values.
829 * arc-tbl.h: Use DPA subclass to mark the double assist
830 instructions. Use DPX/SPX subclas to mark the FPX instructions.
831 * arc-opc.c (RSP): Define instead of SP.
832 (arc_aux_regs): Add the subclass field.
834 2016-04-05 Jiong Wang <jiong.wang@arm.com>
836 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
838 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
840 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
843 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
845 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
846 issues. No functional changes.
848 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
850 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
851 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
852 (RTT): Remove duplicate.
853 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
854 (PCT_CONFIG*): Remove.
855 (D1L, D1H, D2H, D2L): Define.
857 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
859 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
861 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
863 * arc-tbl.h (invld07): Remove.
864 * arc-ext-tbl.h: New file.
865 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
866 * arc-opc.c (arc_opcodes): Add ext-tbl include.
868 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
870 Fix -Wstack-usage warnings.
871 * aarch64-dis.c (print_operands): Substitute size.
872 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
874 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
876 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
877 to get a proper diagnostic when an invalid ASR register is used.
879 2016-03-22 Nick Clifton <nickc@redhat.com>
881 * configure: Regenerate.
883 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
885 * arc-nps400-tbl.h: New file.
886 * arc-opc.c: Add top level comment.
887 (insert_nps_3bit_dst): New function.
888 (extract_nps_3bit_dst): New function.
889 (insert_nps_3bit_src2): New function.
890 (extract_nps_3bit_src2): New function.
891 (insert_nps_bitop_size): New function.
892 (extract_nps_bitop_size): New function.
893 (arc_flag_operands): Add nps400 entries.
894 (arc_flag_classes): Add nps400 entries.
895 (arc_operands): Add nps400 entries.
896 (arc_opcodes): Add nps400 include.
898 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
900 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
901 the new class enum values.
903 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
905 * arc-dis.c (print_insn_arc): Handle nps400.
907 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
909 * arc-opc.c (BASE): Delete.
911 2016-03-18 Nick Clifton <nickc@redhat.com>
914 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
915 of MOV insn that aliases an ORR insn.
917 2016-03-16 Jiong Wang <jiong.wang@arm.com>
919 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
921 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
923 * mcore-opc.h: Add const qualifiers.
924 * microblaze-opc.h (struct op_code_struct): Likewise.
925 * sh-opc.h: Likewise.
926 * tic4x-dis.c (tic4x_print_indirect): Likewise.
927 (tic4x_print_op): Likewise.
929 2016-03-02 Alan Modra <amodra@gmail.com>
931 * or1k-desc.h: Regenerate.
932 * fr30-ibld.c: Regenerate.
933 * rl78-decode.c: Regenerate.
935 2016-03-01 Nick Clifton <nickc@redhat.com>
938 * rl78-dis.c (print_insn_rl78_common): Fix typo.
940 2016-02-24 Renlin Li <renlin.li@arm.com>
942 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
943 (print_insn_coprocessor): Support fp16 instructions.
945 2016-02-24 Renlin Li <renlin.li@arm.com>
947 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
950 2016-02-24 Renlin Li <renlin.li@arm.com>
952 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
953 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
955 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
957 * i386-dis.c (print_insn): Parenthesize expression to prevent
961 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
962 Janek van Oirschot <jvanoirs@synopsys.com>
964 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
967 2016-02-04 Nick Clifton <nickc@redhat.com>
970 * msp430-dis.c (print_insn_msp430): Add a special case for
971 decoding an RRC instruction with the ZC bit set in the extension
974 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
976 * cgen-ibld.in (insert_normal): Rework calculation of shift.
977 * epiphany-ibld.c: Regenerate.
978 * fr30-ibld.c: Regenerate.
979 * frv-ibld.c: Regenerate.
980 * ip2k-ibld.c: Regenerate.
981 * iq2000-ibld.c: Regenerate.
982 * lm32-ibld.c: Regenerate.
983 * m32c-ibld.c: Regenerate.
984 * m32r-ibld.c: Regenerate.
985 * mep-ibld.c: Regenerate.
986 * mt-ibld.c: Regenerate.
987 * or1k-ibld.c: Regenerate.
988 * xc16x-ibld.c: Regenerate.
989 * xstormy16-ibld.c: Regenerate.
991 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
993 * epiphany-dis.c: Regenerated from latest cpu files.
995 2016-02-01 Michael McConville <mmcco@mykolab.com>
997 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1000 2016-01-25 Renlin Li <renlin.li@arm.com>
1002 * arm-dis.c (mapping_symbol_for_insn): New function.
1003 (find_ifthen_state): Call mapping_symbol_for_insn().
1005 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1007 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1008 of MSR UAO immediate operand.
1010 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1012 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1013 instruction support.
1015 2016-01-17 Alan Modra <amodra@gmail.com>
1017 * configure: Regenerate.
1019 2016-01-14 Nick Clifton <nickc@redhat.com>
1021 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1022 instructions that can support stack pointer operations.
1023 * rl78-decode.c: Regenerate.
1024 * rl78-dis.c: Fix display of stack pointer in MOVW based
1027 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1029 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1030 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1031 erxtatus_el1 and erxaddr_el1.
1033 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1035 * arm-dis.c (arm_opcodes): Add "esb".
1036 (thumb_opcodes): Likewise.
1038 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1040 * ppc-opc.c <xscmpnedp>: Delete.
1041 <xvcmpnedp>: Likewise.
1042 <xvcmpnedp.>: Likewise.
1043 <xvcmpnesp>: Likewise.
1044 <xvcmpnesp.>: Likewise.
1046 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1049 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1052 2016-01-01 Alan Modra <amodra@gmail.com>
1054 Update year range in copyright notice of all files.
1056 For older changes see ChangeLog-2015
1058 Copyright (C) 2016 Free Software Foundation, Inc.
1060 Copying and distribution of this file, with or without modification,
1061 are permitted in any medium without royalty provided the copyright
1062 notice and this notice are preserved.
1068 version-control: never