opcodes/ChangeLog

   1 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * mips16-opc.c: Add entries for argumentless "entry" and "exit"
   4         instructions.
   5
   6 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   7
   8         * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
   9         MDMX-like instructions.
  10         * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
  11         printing "Q" operands for INSN_5400 instructions.
  12
  13 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  14
  15         * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
  16         "+S" for "cins".
  17         * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
  18         Combine cases.
  19
  20 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  21
  22         * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
  23         "jalx".
  24         * mips16-opc.c (mips16_opcodes): Likewise.
  25         * micromips-opc.c (micromips_opcodes): Likewise.
  26         * mips-dis.c (print_insn_args, print_mips16_insn_arg)
  27         (print_insn_mips16): Handle "+i".
  28         (print_insn_micromips): Likewise.  Conditionally preserve the
  29         ISA bit for "a" but not for "+i".
  30
  31 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  32
  33         * micromips-opc.c (WR_mhi): Rename to..
  34         (WR_mh): ...this.
  35         (micromips_opcodes): Update "movep" entry accordingly.  Replace
  36         "mh,mi" with "mh".
  37         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
  38         (micromips_to_32_reg_h_map1): ...this.
  39         (micromips_to_32_reg_i_map): Rename to...
  40         (micromips_to_32_reg_h_map2): ...this.
  41         (print_micromips_insn): Remove "mi" case.  Print both registers
  42         in the pair for "mh".
  43
  44 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  45
  46         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
  47         * micromips-opc.c (micromips_opcodes): Likewise.
  48         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
  49         and "+T" handling.  Check for a "0" suffix when deciding whether to
  50         use coprocessor 0 names.  In that case, also check for ",H" selectors.
  51
  52 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  53
  54         * s390-opc.c (J12_12, J24_24): New macros.
  55         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
  56         (MASK_MII_UPI): Rename to MASK_MII_UPP.
  57         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
  58
  59 2013-07-04  Alan Modra  <amodra@gmail.com>
  60
  61         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
  62
  63 2013-06-26  Nick Clifton  <nickc@redhat.com>
  64
  65         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
  66         field when checking for type 2 nop.
  67         * rx-decode.c: Regenerate.
  68
  69 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  70
  71         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
  72         and "movep" macros.
  73
  74 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
  75
  76         * mips-dis.c (is_mips16_plt_tail): New function.
  77         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
  78         word.
  79         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
  80
  81 2013-06-21  DJ Delorie  <dj@redhat.com>
  82
  83         * msp430-decode.opc: New.
  84         * msp430-decode.c: New/generated.
  85         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
  86         (MAINTAINER_CLEANFILES): Likewise.
  87         Add rule to build msp430-decode.c frommsp430decode.opc
  88         using the opc2c program.
  89         * Makefile.in: Regenerate.
  90         * configure.in: Add msp430-decode.lo to msp430 architecture files.
  91         * configure: Regenerate.
  92
  93 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  94
  95         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
  96         (SYMTAB_AVAILABLE): Removed.
  97         (#include "elf/aarch64.h): Ditto.
  98
  99 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 100             Maciej W. Rozycki  <macro@codesourcery.com>
 101             Chao-Ying Fu  <fu@mips.com>
 102
 103         * micromips-opc.c (EVA): Define.
 104         (TLBINV): Define.
 105         (micromips_opcodes): Add EVA opcodes.
 106         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
 107         (print_insn_args): Handle EVA offsets.
 108         (print_insn_micromips): Likewise.
 109         * mips-opc.c (EVA): Define.
 110         (TLBINV): Define.
 111         (mips_builtin_opcodes): Add EVA opcodes.
 112
 113 2013-06-17  Alan Modra  <amodra@gmail.com>
 114
 115         * Makefile.am (mips-opc.lo): Add rules to create automatic
 116         dependency files.  Pass archdefs.
 117         (micromips-opc.lo, mips16-opc.lo): Likewise.
 118         * Makefile.in: Regenerate.
 119
 120 2013-06-14  DJ Delorie  <dj@redhat.com>
 121
 122         * rx-decode.opc (rx_decode_opcode): Bit operations on
 123         registers are 32-bit operations, not 8-bit operations.
 124         * rx-decode.c: Regenerate.
 125
 126 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 127
 128         * micromips-opc.c (IVIRT): New define.
 129         (IVIRT64): New define.
 130         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 131         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 132
 133         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 134         dmtgc0 to print cp0 names.
 135
 136 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 137
 138         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 139         argument.
 140
 141 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 142             Richard Sandiford  <rdsandiford@googlemail.com>
 143
 144         * micromips-opc.c (D32, D33, MC): Update definitions.
 145         (micromips_opcodes):  Initialize ase field.
 146         * mips-dis.c (mips_arch_choice): Add ase field.
 147         (mips_arch_choices): Initialize ase field.
 148         (set_default_mips_dis_options): Declare and setup mips_ase.
 149         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 150         MT32, MC): Update definitions.
 151         (mips_builtin_opcodes): Initialize ase field.
 152
 153 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 154
 155         * s390-opc.txt (flogr): Require a register pair destination.
 156
 157 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 158
 159         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 160         instruction format.
 161
 162 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 163
 164         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 165
 166 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 167
 168         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 169         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 170         XLS_MASK, PPCVSX2): New defines.
 171         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 172         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 173         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 174         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 175         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 176         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 177         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 178         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 179         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 180         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 181         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 182         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 183         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 184         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 185         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 186         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 187         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 188         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 189         <lxvx, stxvx>: New extended mnemonics.
 190
 191 2013-05-17  Alan Modra  <amodra@gmail.com>
 192
 193         * ia64-raw.tbl: Replace non-ASCII char.
 194         * ia64-waw.tbl: Likewise.
 195         * ia64-asmtab.c: Regenerate.
 196
 197 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 198
 199         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 200         * i386-init.h: Regenerated.
 201
 202 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 203
 204         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 205         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 206         check from [0, 255] to [-128, 255].
 207
 208 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 209
 210         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 211         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 212         (parse_mips_dis_option): Handle the virt option.
 213         (print_insn_args): Handle "+J".
 214         (print_mips_disassembler_options): Print out message about virt64.
 215         * mips-opc.c (IVIRT): New define.
 216         (IVIRT64): New define.
 217         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 218         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 219         Move rfe to the bottom as it conflicts with tlbgp.
 220
 221 2013-05-09  Alan Modra  <amodra@gmail.com>
 222
 223         * ppc-opc.c (extract_vlesi): Properly sign extend.
 224         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 225
 226 2013-05-02  Nick Clifton  <nickc@redhat.com>
 227
 228         * msp430-dis.c: Add support for MSP430X instructions.
 229
 230 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 231
 232         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 233         to "eccinj".
 234
 235 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 236
 237         PR binutils/15369
 238         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 239         of CGEN_CPU_ENDIAN.
 240         (hash_insns_list): Likewise.
 241
 242 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 243
 244         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 245         warning workaround.
 246
 247 2013-04-08  Jan Beulich <jbeulich@suse.com>
 248
 249         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 250         * i386-tbl.h: Re-generate.
 251
 252 2013-04-06  David S. Miller  <davem@davemloft.net>
 253
 254         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 255         of an opcode, prefer the one with F_PREFERRED set.
 256         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 257         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 258         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 259         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 260         instructions generating condition codes, mark existing mnenomics
 261         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 262         existing mnenomics as aliases.
 263
 264 2013-04-03  Nick Clifton  <nickc@redhat.com>
 265
 266         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 267         destination address by subtracting the operand from the current
 268         address.
 269         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 270         a positive value in the insn.
 271         (extract_u16_loop): Do not negate the returned value.
 272         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 273
 274         (ceilf.sw): Remove duplicate entry.
 275         (cvtf.hs): New entry.
 276         (cvtf.sh): Likewise.
 277         (fmaf.s): Likewise.
 278         (fmsf.s): Likewise.
 279         (fnmaf.s): Likewise.
 280         (fnmsf.s): Likewise.
 281         (maddf.s): Restrict to E3V5 architectures.
 282         (msubf.s): Likewise.
 283         (nmaddf.s): Likewise.
 284         (nmsubf.s): Likewise.
 285
 286 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 289         check address mode.
 290         (print_insn): Pass sizeflag to get_sib.
 291
 292 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 293
 294         PR binutils/15068
 295         * tic6x-dis.c: Add support for displaying 16-bit insns.
 296
 297 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 298
 299         PR gas/15095
 300         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 301         individual msb and lsb halves in src1 & src2 fields.  Discard the
 302         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 303         follow what Ti SDK does in that case as any value in the src1
 304         field yields the same output with SDK disassembler.
 305
 306 2013-03-12  Michael Eager <eager@eagercon.com>
 307
 308         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 309
 310 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 311
 312         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 313
 314 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 315
 316         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 317
 318 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 319
 320         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 321
 322 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 323
 324         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 325         (thumb32_opcodes): Likewise.
 326         (print_insn_thumb32): Handle 'S' control char.
 327
 328 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 329
 330         * lm32-desc.c: Regenerate.
 331
 332 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-reg.tbl (riz): Add RegRex64.
 335         * i386-tbl.h: Regenerated.
 336
 337 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 338
 339         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 340         (aarch64_feature_crc): New static.
 341         (CRC): New macro.
 342         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 343         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 344         * aarch64-asm-2.c: Re-generate.
 345         * aarch64-dis-2.c: Ditto.
 346         * aarch64-opc-2.c: Ditto.
 347
 348 2013-02-27  Alan Modra  <amodra@gmail.com>
 349
 350         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 351         * rl78-decode.c: Regenerate.
 352
 353 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 354
 355         * rl78-decode.opc: Fix encoding of DIVWU insn.
 356         * rl78-decode.c: Regenerate.
 357
 358 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 359
 360         PR gas/15159
 361         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 362
 363         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 364         (cpu_flags): Add CpuSMAP.
 365
 366         * i386-opc.h (CpuSMAP): New.
 367         (i386_cpu_flags): Add cpusmap.
 368
 369         * i386-opc.tbl: Add clac and stac.
 370
 371         * i386-init.h: Regenerated.
 372         * i386-tbl.h: Likewise.
 373
 374 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 375
 376         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 377         which also makes the disassembler output be in little
 378         endian like it should be.
 379
 380 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 381
 382         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 383         fields to NULL.
 384         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 385
 386 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 387
 388         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 389         section disassembled.
 390
 391 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 392
 393         * arm-dis.c: Update strht pattern.
 394
 395 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 396
 397         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 398         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 399         trunc.w.s macro for EE.
 400
 401 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 402             Andrew Jenner <andrew@codesourcery.com>
 403
 404         Based on patches from Altera Corporation.
 405
 406         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 407         nios2-opc.c.
 408         * Makefile.in: Regenerated.
 409         * configure.in: Add case for bfd_nios2_arch.
 410         * configure: Regenerated.
 411         * disassemble.c (ARCH_nios2): Define.
 412         (disassembler): Add case for bfd_arch_nios2.
 413         * nios2-dis.c: New file.
 414         * nios2-opc.c: New file.
 415
 416 2013-02-04  Alan Modra  <amodra@gmail.com>
 417
 418         * po/POTFILES.in: Regenerate.
 419         * rl78-decode.c: Regenerate.
 420         * rx-decode.c: Regenerate.
 421
 422 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 423
 424         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 425         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 426         * aarch64-asm.c (convert_xtl_to_shll): New function.
 427         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 428         calling convert_xtl_to_shll.
 429         * aarch64-dis.c (convert_shll_to_xtl): New function.
 430         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 431         calling convert_shll_to_xtl.
 432         * aarch64-gen.c: Update copyright year.
 433         * aarch64-asm-2.c: Re-generate.
 434         * aarch64-dis-2.c: Re-generate.
 435         * aarch64-opc-2.c: Re-generate.
 436
 437 2013-01-24  Nick Clifton  <nickc@redhat.com>
 438
 439         * v850-dis.c: Add support for e3v5 architecture.
 440         * v850-opc.c: Likewise.
 441
 442 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 443
 444         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 445         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 446         * aarch64-opc.c (operand_general_constraint_met_p): For
 447         AARCH64_MOD_LSL, move the range check on the shift amount before the
 448         alignment check; change to call set_sft_amount_out_of_range_error
 449         instead of set_imm_out_of_range_error.
 450         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 451         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 452         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 453         SIMD_IMM_SFT.
 454
 455 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 458
 459         * i386-init.h: Regenerated.
 460         * i386-tbl.h: Likewise.
 461
 462 2013-01-15  Nick Clifton  <nickc@redhat.com>
 463
 464         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 465         values.
 466         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 467
 468 2013-01-14  Will Newton <will.newton@imgtec.com>
 469
 470         * metag-dis.c (REG_WIDTH): Increase to 64.
 471
 472 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 473
 474         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 475         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 476         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 477         (SH6): Update.
 478         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 479         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 480         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 481         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 482
 483 2013-01-10  Will Newton <will.newton@imgtec.com>
 484
 485         * Makefile.am: Add Meta.
 486         * configure.in: Add Meta.
 487         * disassemble.c: Add Meta support.
 488         * metag-dis.c: New file.
 489         * Makefile.in: Regenerate.
 490         * configure: Regenerate.
 491
 492 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 493
 494         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 495         (match_opcode): Rename to cr16_match_opcode.
 496
 497 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 498
 499         * mips-dis.c: Add names for CP0 registers of r5900.
 500         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 501         instructions sq and lq.
 502         Add support for MIPS r5900 CPU.
 503         Add support for 128 bit MMI (Multimedia Instructions).
 504         Add support for EE instructions (Emotion Engine).
 505         Disable unsupported floating point instructions (64 bit and
 506         undefined compare operations).
 507         Enable instructions of MIPS ISA IV which are supported by r5900.
 508         Disable 64 bit co processor instructions.
 509         Disable 64 bit multiplication and division instructions.
 510         Disable instructions for co-processor 2 and 3, because these are
 511         not supported (preparation for later VU0 support (Vector Unit)).
 512         Disable cvt.w.s because this behaves like trunc.w.s and the
 513         correct execution can't be ensured on r5900.
 514         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 515         will confuse less developers and compilers.
 516
 517 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 518
 519         * aarch64-opc.c (aarch64_print_operand): Change to print
 520         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 521         in comment.
 522         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 523         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 524         OP_MOV_IMM_WIDE.
 525
 526 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 527
 528         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 529         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 530
 531 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         * i386-gen.c (process_copyright): Update copyright year to 2013.
 534
 535 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 536
 537         * cr16-dis.c (match_opcode,make_instruction): Remove static
 538         declaration.
 539         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 540         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 541
 542 For older changes see ChangeLog-2012
 543 \f
 544 Copyright (C) 2013 Free Software Foundation, Inc.
 545
 546 Copying and distribution of this file, with or without modification,
 547 are permitted in any medium without royalty provided the copyright
 548 notice and this notice are preserved.
 549
 550 Local Variables:
 551 mode: change-log
 552 left-margin: 8
 553 fill-column: 74
 554 version-control: never
 555 End: