1 2017-03-29 Alan Modra <amodra@gmail.com>
3 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
5 (lookup_powerpc): Don't special case -1 dialect. Handle
7 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
8 lookup_powerpc call, pass it on second.
10 2017-03-27 Alan Modra <amodra@gmail.com>
13 * ppc-dis.c (struct ppc_mopt): Comment.
14 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
16 2017-03-27 Rinat Zelig <rinat@mellanox.com>
18 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
19 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
20 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
21 (insert_nps_misc_imm_offset): New function.
22 (extract_nps_misc imm_offset): New function.
23 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
24 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
26 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
28 * s390-mkopc.c (main): Remove vx2 check.
29 * s390-opc.txt: Remove vx2 instruction flags.
31 2017-03-21 Rinat Zelig <rinat@mellanox.com>
33 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
34 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
35 (insert_nps_imm_offset): New function.
36 (extract_nps_imm_offset): New function.
37 (insert_nps_imm_entry): New function.
38 (extract_nps_imm_entry): New function.
40 2017-03-17 Alan Modra <amodra@gmail.com>
43 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
44 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
45 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
47 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
49 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
53 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
55 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
57 2017-03-13 Andrew Waterman <andrew@sifive.com>
59 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
64 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
66 * i386-gen.c (opcode_modifiers): Replace S with Load.
67 * i386-opc.h (S): Removed.
69 (i386_opcode_modifier): Replace s with load.
70 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
71 and {evex}. Replace S with Load.
72 * i386-tbl.h: Regenerated.
74 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
76 * i386-opc.tbl: Use CpuCET on rdsspq.
77 * i386-tbl.h: Regenerated.
79 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
81 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
82 <vsx>: Do not use PPC_OPCODE_VSX3;
84 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
86 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
88 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
90 * i386-dis.c (REG_0F1E_MOD_3): New enum.
91 (MOD_0F1E_PREFIX_1): Likewise.
92 (MOD_0F38F5_PREFIX_2): Likewise.
93 (MOD_0F38F6_PREFIX_0): Likewise.
94 (RM_0F1E_MOD_3_REG_7): Likewise.
95 (PREFIX_MOD_0_0F01_REG_5): Likewise.
96 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
97 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
98 (PREFIX_0F1E): Likewise.
99 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
100 (PREFIX_0F38F5): Likewise.
101 (dis386_twobyte): Use PREFIX_0F1E.
102 (reg_table): Add REG_0F1E_MOD_3.
103 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
104 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
105 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
106 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
107 (three_byte_table): Use PREFIX_0F38F5.
108 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
109 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
110 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
111 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
112 PREFIX_MOD_3_0F01_REG_5_RM_2.
113 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
114 (cpu_flags): Add CpuCET.
115 * i386-opc.h (CpuCET): New enum.
116 (CpuUnused): Commented out.
117 (i386_cpu_flags): Add cpucet.
118 * i386-opc.tbl: Add Intel CET instructions.
119 * i386-init.h: Regenerated.
120 * i386-tbl.h: Likewise.
122 2017-03-06 Alan Modra <amodra@gmail.com>
125 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
126 (extract_raq, extract_ras, extract_rbx): New functions.
127 (powerpc_operands): Use opposite corresponding insert function.
129 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
130 register restriction.
132 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
134 * disassemble.c Include "safe-ctype.h".
135 (disassemble_init_for_target): Handle s390 init.
136 (remove_whitespace_and_extra_commas): New function.
137 (disassembler_options_cmp): Likewise.
138 * arm-dis.c: Include "libiberty.h".
140 (regnames): Use long disassembler style names.
141 Add force-thumb and no-force-thumb options.
142 (NUM_ARM_REGNAMES): Rename from this...
143 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
144 (get_arm_regname_num_options): Delete.
145 (set_arm_regname_option): Likewise.
146 (get_arm_regnames): Likewise.
147 (parse_disassembler_options): Likewise.
148 (parse_arm_disassembler_option): Rename from this...
149 (parse_arm_disassembler_options): ...to this. Make static.
150 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
151 (print_insn): Use parse_arm_disassembler_options.
152 (disassembler_options_arm): New function.
153 (print_arm_disassembler_options): Handle updated regnames.
154 * ppc-dis.c: Include "libiberty.h".
155 (ppc_opts): Add "32" and "64" entries.
156 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
157 (powerpc_init_dialect): Add break to switch statement.
158 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
159 (disassembler_options_powerpc): New function.
160 (print_ppc_disassembler_options): Use ARRAY_SIZE.
161 Remove printing of "32" and "64".
162 * s390-dis.c: Include "libiberty.h".
163 (init_flag): Remove unneeded variable.
164 (struct s390_options_t): New structure type.
165 (options): New structure.
166 (init_disasm): Rename from this...
167 (disassemble_init_s390): ...to this. Add initializations for
168 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
169 (print_insn_s390): Delete call to init_disasm.
170 (disassembler_options_s390): New function.
171 (print_s390_disassembler_options): Print using information from
173 * po/opcodes.pot: Regenerate.
175 2017-02-28 Jan Beulich <jbeulich@suse.com>
177 * i386-dis.c (PCMPESTR_Fixup): New.
178 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
179 (prefix_table): Use PCMPESTR_Fixup.
180 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
182 (vex_w_table): Delete VPCMPESTR{I,M} entries.
183 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
184 Split 64-bit and non-64-bit variants.
185 * opcodes/i386-tbl.h: Re-generate.
187 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
189 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
190 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
191 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
192 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
193 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
194 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
195 (OP_SVE_V_HSD): New macros.
196 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
197 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
198 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
199 (aarch64_opcode_table): Add new SVE instructions.
200 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
201 for rotation operands. Add new SVE operands.
202 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
203 (ins_sve_quad_index): Likewise.
204 (ins_imm_rotate): Split into...
205 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
206 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
207 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
209 (aarch64_ins_sve_addr_ri_s4): New function.
210 (aarch64_ins_sve_quad_index): Likewise.
211 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
212 * aarch64-asm-2.c: Regenerate.
213 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
214 (ext_sve_quad_index): Likewise.
215 (ext_imm_rotate): Split into...
216 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
217 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
218 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
220 (aarch64_ext_sve_addr_ri_s4): New function.
221 (aarch64_ext_sve_quad_index): Likewise.
222 (aarch64_ext_sve_index): Allow quad indices.
223 (do_misc_decoding): Likewise.
224 * aarch64-dis-2.c: Regenerate.
225 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
227 (OPD_F_OD_MASK): Widen by one bit.
228 (OPD_F_NO_ZR): Bump accordingly.
229 (get_operand_field_width): New function.
230 * aarch64-opc.c (fields): Add new SVE fields.
231 (operand_general_constraint_met_p): Handle new SVE operands.
232 (aarch64_print_operand): Likewise.
233 * aarch64-opc-2.c: Regenerate.
235 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
237 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
238 (aarch64_feature_compnum): ...this.
239 (SIMD_V8_3): Replace with...
241 (CNUM_INSN): New macro.
242 (aarch64_opcode_table): Use it for the complex number instructions.
244 2017-02-24 Jan Beulich <jbeulich@suse.com>
246 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
248 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
250 Add support for associating SPARC ASIs with an architecture level.
251 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
252 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
253 decoding of SPARC ASIs.
255 2017-02-23 Jan Beulich <jbeulich@suse.com>
257 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
258 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
260 2017-02-21 Jan Beulich <jbeulich@suse.com>
262 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
263 1 (instead of to itself). Correct typo.
265 2017-02-14 Andrew Waterman <andrew@sifive.com>
267 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
270 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
272 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
273 (aarch64_sys_reg_supported_p): Handle them.
275 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
277 * arc-opc.c (UIMM6_20R): Define.
278 (SIMM12_20): Use above.
279 (SIMM12_20R): Define.
280 (SIMM3_5_S): Use above.
281 (UIMM7_A32_11R_S): Define.
282 (UIMM7_9_S): Use above.
283 (UIMM3_13R_S): Define.
284 (SIMM11_A32_7_S): Use above.
286 (UIMM10_A32_8_S): Use above.
287 (UIMM8_8R_S): Define.
289 (arc_relax_opcodes): Use all above defines.
291 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
293 * arc-regs.h: Distinguish some of the registers different on
294 ARC700 and HS38 cpus.
296 2017-02-14 Alan Modra <amodra@gmail.com>
299 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
300 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
302 2017-02-11 Stafford Horne <shorne@gmail.com>
303 Alan Modra <amodra@gmail.com>
305 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
306 Use insn_bytes_value and insn_int_value directly instead. Don't
307 free allocated memory until function exit.
309 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
311 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
313 2017-02-03 Nick Clifton <nickc@redhat.com>
316 * aarch64-opc.c (print_register_list): Ensure that the register
317 list index will fir into the tb buffer.
318 (print_register_offset_address): Likewise.
319 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
321 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
324 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
325 instructions when the previous fetch packet ends with a 32-bit
328 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
330 * pru-opc.c: Remove vague reference to a future GDB port.
332 2017-01-20 Nick Clifton <nickc@redhat.com>
334 * po/ga.po: Updated Irish translation.
336 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
338 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
340 2017-01-13 Yao Qi <yao.qi@linaro.org>
342 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
343 if FETCH_DATA returns 0.
344 (m68k_scan_mask): Likewise.
345 (print_insn_m68k): Update code to handle -1 return value.
347 2017-01-13 Yao Qi <yao.qi@linaro.org>
349 * m68k-dis.c (enum print_insn_arg_error): New.
350 (NEXTBYTE): Replace -3 with
351 PRINT_INSN_ARG_MEMORY_ERROR.
352 (NEXTULONG): Likewise.
353 (NEXTSINGLE): Likewise.
354 (NEXTDOUBLE): Likewise.
355 (NEXTDOUBLE): Likewise.
356 (NEXTPACKED): Likewise.
357 (FETCH_ARG): Likewise.
358 (FETCH_DATA): Update comments.
359 (print_insn_arg): Update comments. Replace magic numbers with
361 (match_insn_m68k): Likewise.
363 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
365 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
366 * i386-dis-evex.h (evex_table): Updated.
367 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
368 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
369 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
370 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
371 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
372 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
373 * i386-init.h: Regenerate.
376 2017-01-12 Yao Qi <yao.qi@linaro.org>
378 * msp430-dis.c (msp430_singleoperand): Return -1 if
379 msp430dis_opcode_signed returns false.
380 (msp430_doubleoperand): Likewise.
381 (msp430_branchinstr): Return -1 if
382 msp430dis_opcode_unsigned returns false.
383 (msp430x_calla_instr): Likewise.
384 (print_insn_msp430): Likewise.
386 2017-01-05 Nick Clifton <nickc@redhat.com>
389 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
390 could not be matched.
391 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
394 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
396 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
397 (aarch64_opcode_table): Use RCPC_INSN.
399 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
401 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
403 * riscv-opcodes/all-opcodes: Likewise.
405 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
407 * riscv-dis.c (print_insn_args): Add fall through comment.
409 2017-01-03 Nick Clifton <nickc@redhat.com>
411 * po/sr.po: New Serbian translation.
412 * configure.ac (ALL_LINGUAS): Add sr.
413 * configure: Regenerate.
415 2017-01-02 Alan Modra <amodra@gmail.com>
417 * epiphany-desc.h: Regenerate.
418 * epiphany-opc.h: Regenerate.
419 * fr30-desc.h: Regenerate.
420 * fr30-opc.h: Regenerate.
421 * frv-desc.h: Regenerate.
422 * frv-opc.h: Regenerate.
423 * ip2k-desc.h: Regenerate.
424 * ip2k-opc.h: Regenerate.
425 * iq2000-desc.h: Regenerate.
426 * iq2000-opc.h: Regenerate.
427 * lm32-desc.h: Regenerate.
428 * lm32-opc.h: Regenerate.
429 * m32c-desc.h: Regenerate.
430 * m32c-opc.h: Regenerate.
431 * m32r-desc.h: Regenerate.
432 * m32r-opc.h: Regenerate.
433 * mep-desc.h: Regenerate.
434 * mep-opc.h: Regenerate.
435 * mt-desc.h: Regenerate.
436 * mt-opc.h: Regenerate.
437 * or1k-desc.h: Regenerate.
438 * or1k-opc.h: Regenerate.
439 * xc16x-desc.h: Regenerate.
440 * xc16x-opc.h: Regenerate.
441 * xstormy16-desc.h: Regenerate.
442 * xstormy16-opc.h: Regenerate.
444 2017-01-02 Alan Modra <amodra@gmail.com>
446 Update year range in copyright notice of all files.
448 For older changes see ChangeLog-2016
450 Copyright (C) 2017 Free Software Foundation, Inc.
452 Copying and distribution of this file, with or without modification,
453 are permitted in any medium without royalty provided the copyright
454 notice and this notice are preserved.
460 version-control: never