1 2018-06-01 Alan Modra <amodra@gmail.com>
3 * sysdep.h (_bfd_error_handler): Don't declare.
4 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
5 * rl78-decode.opc: Likewise.
6 * msp430-decode.c: Regenerate.
7 * rl78-decode.c: Regenerate.
9 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
11 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
12 * i386-init.h : Regenerated.
14 2018-05-25 Alan Modra <amodra@gmail.com>
16 * Makefile.in: Regenerate.
17 * po/POTFILES.in: Regenerate.
19 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
21 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
22 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
23 (insert_bab, extract_bab, insert_btab, extract_btab,
24 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
25 (BAT, BBA VBA RBS XB6S): Delete macros.
26 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
27 (BB, BD, RBX, XC6): Update for new macros.
28 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
29 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
30 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
31 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
33 2018-05-18 John Darrington <john@darrington.wattle.id.au>
35 * Makefile.am: Add support for s12z architecture.
36 * configure.ac: Likewise.
37 * disassemble.c: Likewise.
38 * disassemble.h: Likewise.
39 * Makefile.in: Regenerate.
40 * configure: Regenerate.
41 * s12z-dis.c: New file.
44 2018-05-18 Alan Modra <amodra@gmail.com>
46 * nfp-dis.c: Don't #include libbfd.h.
47 (init_nfp3200_priv): Use bfd_get_section_contents.
48 (nit_nfp6000_mecsr_sec): Likewise.
50 2018-05-17 Nick Clifton <nickc@redhat.com>
52 * po/zh_CN.po: Updated simplified Chinese translation.
54 2018-05-16 Tamar Christina <tamar.christina@arm.com>
57 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
58 * aarch64-dis-2.c: Regenerate.
60 2018-05-15 Tamar Christina <tamar.christina@arm.com>
63 * aarch64-asm.c (opintl.h): Include.
64 (aarch64_ins_sysreg): Enforce read/write constraints.
65 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
66 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
67 (F_REG_READ, F_REG_WRITE): New.
68 * aarch64-opc.c (aarch64_print_operand): Generate notes for
70 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
71 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
72 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
73 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
74 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
75 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
76 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
77 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
78 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
79 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
80 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
81 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
82 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
83 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
84 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
85 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
86 msr (F_SYS_WRITE), mrs (F_SYS_READ).
88 2018-05-15 Tamar Christina <tamar.christina@arm.com>
91 * aarch64-dis.c (no_notes: New.
92 (parse_aarch64_dis_option): Support notes.
93 (aarch64_decode_insn, print_operands): Likewise.
94 (print_aarch64_disassembler_options): Document notes.
95 * aarch64-opc.c (aarch64_print_operand): Support notes.
97 2018-05-15 Tamar Christina <tamar.christina@arm.com>
100 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
101 and take error struct.
102 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
103 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
104 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
105 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
106 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
107 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
108 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
109 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
110 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
111 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
112 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
113 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
114 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
115 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
116 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
117 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
118 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
119 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
120 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
121 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
122 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
123 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
124 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
125 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
126 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
127 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
128 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
129 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
130 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
131 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
132 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
133 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
134 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
135 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
136 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
137 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
138 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
139 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
140 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
141 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
142 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
143 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
144 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
145 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
146 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
147 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
148 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
149 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
150 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
151 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
152 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
153 (determine_disassembling_preference, aarch64_decode_insn,
154 print_insn_aarch64_word, print_insn_data): Take errors struct.
155 (print_insn_aarch64): Use errors.
156 * aarch64-asm-2.c: Regenerate.
157 * aarch64-dis-2.c: Regenerate.
158 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
159 boolean in aarch64_insert_operan.
160 (print_operand_extractor): Likewise.
161 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
163 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
165 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
167 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
169 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
171 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
173 * cr16-opc.c (cr16_instruction): Comment typo fix.
174 * hppa-dis.c (print_insn_hppa): Likewise.
176 2018-05-08 Jim Wilson <jimw@sifive.com>
178 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
179 (match_c_slli64, match_srxi_as_c_srxi): New.
180 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
181 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
182 <c.slli, c.srli, c.srai>: Use match_s_slli.
183 <c.slli64, c.srli64, c.srai64>: New.
185 2018-05-08 Alan Modra <amodra@gmail.com>
187 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
188 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
189 partition opcode space for index lookup.
191 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
193 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
194 <insn_length>: ...with this. Update usage.
195 Remove duplicate call to *info->memory_error_func.
197 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
198 H.J. Lu <hongjiu.lu@intel.com>
200 * i386-dis.c (Gva): New.
201 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
202 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
203 (prefix_table): New instructions (see prefix above).
204 (mod_table): New instructions (see prefix above).
205 (OP_G): Handle va_mode.
206 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
208 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
209 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
210 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
211 * i386-opc.tbl: Add movidir{i,64b}.
212 * i386-init.h: Regenerated.
213 * i386-tbl.h: Likewise.
215 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
217 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
219 * i386-opc.h (AddrPrefixOp0): Renamed to ...
220 (AddrPrefixOpReg): This.
221 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
222 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
224 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
226 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
227 (vle_num_opcodes): Likewise.
228 (spe2_num_opcodes): Likewise.
229 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
231 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
232 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
235 2018-05-01 Tamar Christina <tamar.christina@arm.com>
237 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
239 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
241 Makefile.am: Added nfp-dis.c.
242 configure.ac: Added bfd_nfp_arch.
243 disassemble.h: Added print_insn_nfp prototype.
244 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
245 nfp-dis.c: New, for NFP support.
246 po/POTFILES.in: Added nfp-dis.c to the list.
247 Makefile.in: Regenerate.
248 configure: Regenerate.
250 2018-04-26 Jan Beulich <jbeulich@suse.com>
252 * i386-opc.tbl: Fold various non-memory operand AVX512VL
253 templates into their base ones.
254 * i386-tlb.h: Re-generate.
256 2018-04-26 Jan Beulich <jbeulich@suse.com>
258 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
259 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
260 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
261 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
262 * i386-init.h: Re-generate.
264 2018-04-26 Jan Beulich <jbeulich@suse.com>
266 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
267 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
268 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
269 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
271 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
273 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
275 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
276 cpuregzmm, and cpuregmask.
277 * i386-init.h: Re-generate.
278 * i386-tbl.h: Re-generate.
280 2018-04-26 Jan Beulich <jbeulich@suse.com>
282 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
283 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
284 * i386-init.h: Re-generate.
286 2018-04-26 Jan Beulich <jbeulich@suse.com>
288 * i386-gen.c (VexImmExt): Delete.
289 * i386-opc.h (VexImmExt, veximmext): Delete.
290 * i386-opc.tbl: Drop all VexImmExt uses.
291 * i386-tlb.h: Re-generate.
293 2018-04-25 Jan Beulich <jbeulich@suse.com>
295 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
297 * i386-tlb.h: Re-generate.
299 2018-04-25 Tamar Christina <tamar.christina@arm.com>
301 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
303 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
305 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
307 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
308 (cpu_flags): Add CpuCLDEMOTE.
309 * i386-init.h: Regenerate.
310 * i386-opc.h (enum): Add CpuCLDEMOTE,
311 (i386_cpu_flags): Add cpucldemote.
312 * i386-opc.tbl: Add cldemote.
313 * i386-tbl.h: Regenerate.
315 2018-04-16 Alan Modra <amodra@gmail.com>
317 * Makefile.am: Remove sh5 and sh64 support.
318 * configure.ac: Likewise.
319 * disassemble.c: Likewise.
320 * disassemble.h: Likewise.
321 * sh-dis.c: Likewise.
322 * sh64-dis.c: Delete.
323 * sh64-opc.c: Delete.
324 * sh64-opc.h: Delete.
325 * Makefile.in: Regenerate.
326 * configure: Regenerate.
327 * po/POTFILES.in: Regenerate.
329 2018-04-16 Alan Modra <amodra@gmail.com>
331 * Makefile.am: Remove w65 support.
332 * configure.ac: Likewise.
333 * disassemble.c: Likewise.
334 * disassemble.h: Likewise.
337 * Makefile.in: Regenerate.
338 * configure: Regenerate.
339 * po/POTFILES.in: Regenerate.
341 2018-04-16 Alan Modra <amodra@gmail.com>
343 * configure.ac: Remove we32k support.
344 * configure: Regenerate.
346 2018-04-16 Alan Modra <amodra@gmail.com>
348 * Makefile.am: Remove m88k support.
349 * configure.ac: Likewise.
350 * disassemble.c: Likewise.
351 * disassemble.h: Likewise.
352 * m88k-dis.c: Delete.
353 * Makefile.in: Regenerate.
354 * configure: Regenerate.
355 * po/POTFILES.in: Regenerate.
357 2018-04-16 Alan Modra <amodra@gmail.com>
359 * Makefile.am: Remove i370 support.
360 * configure.ac: Likewise.
361 * disassemble.c: Likewise.
362 * disassemble.h: Likewise.
363 * i370-dis.c: Delete.
364 * i370-opc.c: Delete.
365 * Makefile.in: Regenerate.
366 * configure: Regenerate.
367 * po/POTFILES.in: Regenerate.
369 2018-04-16 Alan Modra <amodra@gmail.com>
371 * Makefile.am: Remove h8500 support.
372 * configure.ac: Likewise.
373 * disassemble.c: Likewise.
374 * disassemble.h: Likewise.
375 * h8500-dis.c: Delete.
376 * h8500-opc.h: Delete.
377 * Makefile.in: Regenerate.
378 * configure: Regenerate.
379 * po/POTFILES.in: Regenerate.
381 2018-04-16 Alan Modra <amodra@gmail.com>
383 * configure.ac: Remove tahoe support.
384 * configure: Regenerate.
386 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
388 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
390 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
392 * i386-tbl.h: Regenerated.
394 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
396 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
397 PREFIX_MOD_1_0FAE_REG_6.
399 (OP_E_register): Use va_mode.
400 * i386-dis-evex.h (prefix_table):
401 New instructions (see prefixes above).
402 * i386-gen.c (cpu_flag_init): Add WAITPKG.
403 (cpu_flags): Likewise.
404 * i386-opc.h (enum): Likewise.
405 (i386_cpu_flags): Likewise.
406 * i386-opc.tbl: Add umonitor, umwait, tpause.
407 * i386-init.h: Regenerate.
408 * i386-tbl.h: Likewise.
410 2018-04-11 Alan Modra <amodra@gmail.com>
412 * opcodes/i860-dis.c: Delete.
413 * opcodes/i960-dis.c: Delete.
414 * Makefile.am: Remove i860 and i960 support.
415 * configure.ac: Likewise.
416 * disassemble.c: Likewise.
417 * disassemble.h: Likewise.
418 * Makefile.in: Regenerate.
419 * configure: Regenerate.
420 * po/POTFILES.in: Regenerate.
422 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
425 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
427 (print_insn): Clear vex instead of vex.evex.
429 2018-04-04 Nick Clifton <nickc@redhat.com>
431 * po/es.po: Updated Spanish translation.
433 2018-03-28 Jan Beulich <jbeulich@suse.com>
435 * i386-gen.c (opcode_modifiers): Delete VecESize.
436 * i386-opc.h (VecESize): Delete.
437 (struct i386_opcode_modifier): Delete vecesize.
438 * i386-opc.tbl: Drop VecESize.
439 * i386-tlb.h: Re-generate.
441 2018-03-28 Jan Beulich <jbeulich@suse.com>
443 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
444 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
445 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
446 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
447 * i386-tlb.h: Re-generate.
449 2018-03-28 Jan Beulich <jbeulich@suse.com>
451 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
453 * i386-tlb.h: Re-generate.
455 2018-03-28 Jan Beulich <jbeulich@suse.com>
457 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
458 (vex_len_table): Drop Y for vcvt*2si.
459 (putop): Replace plain 'Y' handling by abort().
461 2018-03-28 Nick Clifton <nickc@redhat.com>
464 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
465 instructions with only a base address register.
466 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
467 handle AARHC64_OPND_SVE_ADDR_R.
468 (aarch64_print_operand): Likewise.
469 * aarch64-asm-2.c: Regenerate.
470 * aarch64_dis-2.c: Regenerate.
471 * aarch64-opc-2.c: Regenerate.
473 2018-03-22 Jan Beulich <jbeulich@suse.com>
475 * i386-opc.tbl: Drop VecESize from register only insn forms and
476 memory forms not allowing broadcast.
477 * i386-tlb.h: Re-generate.
479 2018-03-22 Jan Beulich <jbeulich@suse.com>
481 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
482 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
483 sha256*): Drop Disp<N>.
485 2018-03-22 Jan Beulich <jbeulich@suse.com>
487 * i386-dis.c (EbndS, bnd_swap_mode): New.
488 (prefix_table): Use EbndS.
489 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
490 * i386-opc.tbl (bndmov): Move misplaced Load.
491 * i386-tlb.h: Re-generate.
493 2018-03-22 Jan Beulich <jbeulich@suse.com>
495 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
496 templates allowing memory operands and folded ones for register
498 * i386-tlb.h: Re-generate.
500 2018-03-22 Jan Beulich <jbeulich@suse.com>
502 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
503 256-bit templates. Drop redundant leftover Disp<N>.
504 * i386-tlb.h: Re-generate.
506 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
508 * riscv-opc.c (riscv_insn_types): New.
510 2018-03-13 Nick Clifton <nickc@redhat.com>
512 * po/pt_BR.po: Updated Brazilian Portuguese translation.
514 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
516 * i386-opc.tbl: Add Optimize to clr.
517 * i386-tbl.h: Regenerated.
519 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-gen.c (opcode_modifiers): Remove OldGcc.
522 * i386-opc.h (OldGcc): Removed.
523 (i386_opcode_modifier): Remove oldgcc.
524 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
525 instructions for old (<= 2.8.1) versions of gcc.
526 * i386-tbl.h: Regenerated.
528 2018-03-08 Jan Beulich <jbeulich@suse.com>
530 * i386-opc.h (EVEXDYN): New.
531 * i386-opc.tbl: Fold various AVX512VL templates.
532 * i386-tlb.h: Re-generate.
534 2018-03-08 Jan Beulich <jbeulich@suse.com>
536 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
537 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
538 vpexpandd, vpexpandq): Fold AFX512VF templates.
539 * i386-tlb.h: Re-generate.
541 2018-03-08 Jan Beulich <jbeulich@suse.com>
543 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
544 Fold 128- and 256-bit VEX-encoded templates.
545 * i386-tlb.h: Re-generate.
547 2018-03-08 Jan Beulich <jbeulich@suse.com>
549 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
550 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
551 vpexpandd, vpexpandq): Fold AVX512F templates.
552 * i386-tlb.h: Re-generate.
554 2018-03-08 Jan Beulich <jbeulich@suse.com>
556 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
557 64-bit templates. Drop Disp<N>.
558 * i386-tlb.h: Re-generate.
560 2018-03-08 Jan Beulich <jbeulich@suse.com>
562 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
563 and 256-bit templates.
564 * i386-tlb.h: Re-generate.
566 2018-03-08 Jan Beulich <jbeulich@suse.com>
568 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
569 * i386-tlb.h: Re-generate.
571 2018-03-08 Jan Beulich <jbeulich@suse.com>
573 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
575 * i386-tlb.h: Re-generate.
577 2018-03-08 Jan Beulich <jbeulich@suse.com>
579 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
580 * i386-tlb.h: Re-generate.
582 2018-03-08 Jan Beulich <jbeulich@suse.com>
584 * i386-gen.c (opcode_modifiers): Delete FloatD.
585 * i386-opc.h (FloatD): Delete.
586 (struct i386_opcode_modifier): Delete floatd.
587 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
589 * i386-tlb.h: Re-generate.
591 2018-03-08 Jan Beulich <jbeulich@suse.com>
593 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
595 2018-03-08 Jan Beulich <jbeulich@suse.com>
597 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
598 * i386-tlb.h: Re-generate.
600 2018-03-08 Jan Beulich <jbeulich@suse.com>
602 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
604 * i386-tlb.h: Re-generate.
606 2018-03-07 Alan Modra <amodra@gmail.com>
608 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
610 * disassemble.h (print_insn_rs6000): Delete.
611 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
612 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
613 (print_insn_rs6000): Delete.
615 2018-03-03 Alan Modra <amodra@gmail.com>
617 * sysdep.h (opcodes_error_handler): Define.
618 (_bfd_error_handler): Declare.
619 * Makefile.am: Remove stray #.
620 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
622 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
623 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
624 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
625 opcodes_error_handler to print errors. Standardize error messages.
626 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
627 and include opintl.h.
628 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
629 * i386-gen.c: Standardize error messages.
630 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
631 * Makefile.in: Regenerate.
632 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
633 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
634 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
635 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
636 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
637 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
638 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
639 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
640 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
641 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
642 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
643 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
644 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
646 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
648 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
649 vpsub[bwdq] instructions.
650 * i386-tbl.h: Regenerated.
652 2018-03-01 Alan Modra <amodra@gmail.com>
654 * configure.ac (ALL_LINGUAS): Sort.
655 * configure: Regenerate.
657 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
659 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
660 macro by assignements.
662 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
665 * i386-gen.c (opcode_modifiers): Add Optimize.
666 * i386-opc.h (Optimize): New enum.
667 (i386_opcode_modifier): Add optimize.
668 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
669 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
670 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
671 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
672 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
674 * i386-tbl.h: Regenerated.
676 2018-02-26 Alan Modra <amodra@gmail.com>
678 * crx-dis.c (getregliststring): Allocate a large enough buffer
679 to silence false positive gcc8 warning.
681 2018-02-22 Shea Levy <shea@shealevy.com>
683 * disassemble.c (ARCH_riscv): Define if ARCH_all.
685 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
687 * i386-opc.tbl: Add {rex},
688 * i386-tbl.h: Regenerated.
690 2018-02-20 Maciej W. Rozycki <macro@mips.com>
692 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
693 (mips16_opcodes): Replace `M' with `m' for "restore".
695 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
697 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
699 2018-02-13 Maciej W. Rozycki <macro@mips.com>
701 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
702 variable to `function_index'.
704 2018-02-13 Nick Clifton <nickc@redhat.com>
707 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
708 about truncation of printing.
710 2018-02-12 Henry Wong <henry@stuffedcow.net>
712 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
714 2018-02-05 Nick Clifton <nickc@redhat.com>
716 * po/pt_BR.po: Updated Brazilian Portuguese translation.
718 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
720 * i386-dis.c (enum): Add pconfig.
721 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
722 (cpu_flags): Add CpuPCONFIG.
723 * i386-opc.h (enum): Add CpuPCONFIG.
724 (i386_cpu_flags): Add cpupconfig.
725 * i386-opc.tbl: Add PCONFIG instruction.
726 * i386-init.h: Regenerate.
727 * i386-tbl.h: Likewise.
729 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
731 * i386-dis.c (enum): Add PREFIX_0F09.
732 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
733 (cpu_flags): Add CpuWBNOINVD.
734 * i386-opc.h (enum): Add CpuWBNOINVD.
735 (i386_cpu_flags): Add cpuwbnoinvd.
736 * i386-opc.tbl: Add WBNOINVD instruction.
737 * i386-init.h: Regenerate.
738 * i386-tbl.h: Likewise.
740 2018-01-17 Jim Wilson <jimw@sifive.com>
742 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
744 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
746 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
747 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
748 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
749 (cpu_flags): Add CpuIBT, CpuSHSTK.
750 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
751 (i386_cpu_flags): Add cpuibt, cpushstk.
752 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
753 * i386-init.h: Regenerate.
754 * i386-tbl.h: Likewise.
756 2018-01-16 Nick Clifton <nickc@redhat.com>
758 * po/pt_BR.po: Updated Brazilian Portugese translation.
759 * po/de.po: Updated German translation.
761 2018-01-15 Jim Wilson <jimw@sifive.com>
763 * riscv-opc.c (match_c_nop): New.
764 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
766 2018-01-15 Nick Clifton <nickc@redhat.com>
768 * po/uk.po: Updated Ukranian translation.
770 2018-01-13 Nick Clifton <nickc@redhat.com>
772 * po/opcodes.pot: Regenerated.
774 2018-01-13 Nick Clifton <nickc@redhat.com>
776 * configure: Regenerate.
778 2018-01-13 Nick Clifton <nickc@redhat.com>
782 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
784 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
785 * i386-tbl.h: Regenerate.
787 2018-01-10 Jan Beulich <jbeulich@suse.com>
789 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
790 * i386-tbl.h: Re-generate.
792 2018-01-10 Jan Beulich <jbeulich@suse.com>
794 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
795 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
796 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
797 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
798 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
799 Disp8MemShift of AVX512VL forms.
800 * i386-tbl.h: Re-generate.
802 2018-01-09 Jim Wilson <jimw@sifive.com>
804 * riscv-dis.c (maybe_print_address): If base_reg is zero,
805 then the hi_addr value is zero.
807 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
809 * arm-dis.c (arm_opcodes): Add csdb.
810 (thumb32_opcodes): Add csdb.
812 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
814 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
815 * aarch64-asm-2.c: Regenerate.
816 * aarch64-dis-2.c: Regenerate.
817 * aarch64-opc-2.c: Regenerate.
819 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
822 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
823 Remove AVX512 vmovd with 64-bit operands.
824 * i386-tbl.h: Regenerated.
826 2018-01-05 Jim Wilson <jimw@sifive.com>
828 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
831 2018-01-03 Alan Modra <amodra@gmail.com>
833 Update year range in copyright notice of all files.
835 2018-01-02 Jan Beulich <jbeulich@suse.com>
837 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
838 and OPERAND_TYPE_REGZMM entries.
840 For older changes see ChangeLog-2017
842 Copyright (C) 2018 Free Software Foundation, Inc.
844 Copying and distribution of this file, with or without modification,
845 are permitted in any medium without royalty provided the copyright
846 notice and this notice are preserved.
852 version-control: never