opcodes/ChangeLog

   1 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
   2            Michael Meissner             <michael.meissner@amd.com>
   3
   4         * i386-dis.c (dis386): Add support for 4 operand instructions. Add
   5         support for amdfam10 SSE4a/ABM instructions. Modify all
   6         initializer macros to have additional arguments. Disallow REP
   7         prefix for non-string instructions.
   8         (print_insn): Ditto.
   9
  10
  11 2006-07-05  Julian Brown  <julian@codesourcery.com>
  12
  13         * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
  14
  15 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  16
  17         * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
  18         (twobyte_has_modrm): Set 1 for 0x1f.
  19
  20 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         * i386-dis.c (NOP_Fixup): Removed.
  23         (NOP_Fixup1): New.
  24         (NOP_Fixup2): Likewise.
  25         (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
  26
  27 2006-06-12  Julian Brown  <julian@codesourcery.com>
  28
  29         * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
  30         on 64-bit hosts.
  31
  32 2006-06-10  H.J. Lu  <hongjiu.lu@intel.com>
  33
  34         * i386.c (GRP10): Renamed to ...
  35         (GRP12): This.
  36         (GRP11): Renamed to ...
  37         (GRP13): This.
  38         (GRP12): Renamed to ...
  39         (GRP14): This.
  40         (GRP13): Renamed to ...
  41         (GRP15): This.
  42         (GRP14): Renamed to ...
  43         (GRP16): This.
  44         (dis386_twobyte): Updated.
  45         (grps): Likewise.
  46
  47 2006-06-09  Nick Clifton  <nickc@redhat.com>
  48
  49         * po/fi.po: Updated Finnish translation.
  50
  51 2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
  52
  53         * po/Make-in (pdf, ps): New dummy targets.
  54
  55 2006-06-06  Paul Brook  <paul@codesourcery.com>
  56
  57         * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
  58         instructions.
  59         (neon_opcodes): Add conditional execution specifiers.
  60         (thumb_opcodes): Ditto.
  61         (thumb32_opcodes): Ditto.
  62         (arm_conditional): Change 0xe to "al" and add "" to end.
  63         (ifthen_state, ifthen_next_state, ifthen_address): New.
  64         (IFTHEN_COND): Define.
  65         (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
  66         (print_insn_arm): Change %c to use new values of arm_conditional.
  67         (print_insn_thumb16): Print thumb conditions.  Add %I.
  68         (print_insn_thumb32): Print thumb conditions.
  69         (find_ifthen_state): New function.
  70         (print_insn): Track IT block state.
  71
  72 2006-06-06  Ben Elliston  <bje@au.ibm.com>
  73             Anton Blanchard  <anton@samba.org>
  74             Peter Bergner  <bergner@vnet.ibm.com>
  75
  76         * ppc-dis.c (powerpc_dialect): Handle power6 option.
  77         (print_ppc_disassembler_options): Mention power6.
  78
  79 2006-06-06  Thiemo Seufer  <ths@mips.com>
  80             Chao-ying Fu  <fu@mips.com>
  81
  82         * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
  83         * mips-opc.c: Add DSP64 instructions.
  84
  85 2006-06-06  Alan Modra  <amodra@bigpond.net.au>
  86
  87         * m68hc11-dis.c (print_insn): Warning fix.
  88
  89 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
  90
  91         * po/Make-in (top_builddir): Define.
  92
  93 2006-06-05  Alan Modra  <amodra@bigpond.net.au>
  94
  95         * Makefile.am: Run "make dep-am".
  96         * Makefile.in: Regenerate.
  97         * config.in: Regenerate.
  98
  99 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 100
 101         * Makefile.am (INCLUDES): Use @INCINTL@.
 102         * acinclude.m4: Include new gettext macros.
 103         * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
 104         Remove local code for po/Makefile.
 105         * Makefile.in, aclocal.m4, configure: Regenerated.
 106
 107 2006-05-30  Nick Clifton  <nickc@redhat.com>
 108
 109         * po/es.po: Updated Spanish translation.
 110
 111 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 112
 113         * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
 114         and fmovem entries.  Put register list entries before immediate
 115         mask entries.  Use "l" rather than "L" in the fmovem entries.
 116         * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
 117         out from INFO.
 118         (m68k_scan_mask): New function, split out from...
 119         (print_insn_m68k): ...here.  If no architecture has been set,
 120         first try printing an m680x0 instruction, then try a Coldfire one.
 121
 122 2006-05-24  Nick Clifton  <nickc@redhat.com>
 123
 124         * po/ga.po: Updated Irish translation.
 125
 126 2006-05-22  Nick Clifton  <nickc@redhat.com>
 127
 128         * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
 129
 130 2006-05-22  Nick Clifton  <nickc@redhat.com>
 131
 132         * po/nl.po: Updated translation.
 133
 134 2006-05-18  Alan Modra  <amodra@bigpond.net.au>
 135
 136         * avr-dis.c: Formatting fix.
 137
 138 2006-05-14  Thiemo Seufer  <ths@mips.com>
 139
 140         * mips16-opc.c (I1, I32, I64): New shortcut defines.
 141         (mips16_opcodes): Change membership of instructions to their
 142         lowest baseline ISA.
 143
 144 2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         * i386-dis.c (grps): Update sgdt/sidt for 64bit.
 147
 148 2006-05-05  Julian Brown  <julian@codesourcery.com>
 149
 150         * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
 151         vldm/vstm.
 152
 153 2006-05-05  Thiemo Seufer  <ths@mips.com>
 154             David Ung  <davidu@mips.com>
 155
 156         * mips-opc.c: Add macro for cache instruction.
 157
 158 2006-05-04  Thiemo Seufer  <ths@mips.com>
 159             Nigel Stephens  <nigel@mips.com>
 160             David Ung  <davidu@mips.com>
 161
 162         * mips-dis.c (mips_arch_choices): Add smartmips instruction
 163         decoding to MIPS32 and MIPS32R2.  Limit DSP decoding to release
 164         2 ISAs.  Add MIPS3D decoding to MIPS32R2.  Add MT decoding to
 165         MIPS64R2.
 166         * mips-opc.c: fix random typos in comments.
 167         (INSN_SMARTMIPS): New defines.
 168         (mips_builtin_opcodes): Add paired single support for MIPS32R2.
 169         Move bc3f, bc3fl, bc3t, bc3tl downwards.  Move flushi, flushd,
 170         flushid, wb upwards.  Move cfc3, ctc3 downwards.  Rework the
 171         FP_S and FP_D flags to denote single and double register
 172         accesses separately.  Move dmfc3, dmtc3, mfc3, mtc3 downwards.
 173         Allow jr.hb and jalr.hb for release 1 ISAs.  Allow luxc1, suxc1
 174         for MIPS32R2.  Add SmartMIPS instructions.  Add two-argument
 175         variants of bc2f, bc2fl, bc2t, bc2tl.  Add mfhc2, mthc2 to
 176         release 2 ISAs.
 177         * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
 178
 179 2006-05-03  Thiemo Seufer  <ths@mips.com>
 180
 181         * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
 182
 183 2006-05-02  Thiemo Seufer  <ths@mips.com>
 184             Nigel Stephens  <nigel@mips.com>
 185             David Ung  <davidu@mips.com>
 186
 187         * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
 188         (print_mips16_insn_arg): Force mips16 to odd addresses.
 189
 190 2006-04-30  Thiemo Seufer  <ths@mips.com>
 191             David Ung  <davidu@mips.com>
 192
 193         * mips-opc.c (mips_builtin_opcodes): Add udi instructions
 194         "udi0" to "udi15".
 195         * mips-dis.c (print_insn_args): Adds udi argument handling.
 196
 197 2006-04-28  James E Wilson  <wilson@specifix.com>
 198
 199         * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
 200         error message.
 201
 202 2006-04-28  Thiemo Seufer  <ths@mips.com>
 203             David Ung  <davidu@mips.com>
 204             Nigel Stephens  <nigel@mips.com>
 205
 206         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
 207         names.
 208
 209 2006-04-28  Thiemo Seufer  <ths@mips.com>
 210             Nigel Stephens  <nigel@mips.com>
 211             David Ung  <davidu@mips.com>
 212
 213         * mips-dis.c (print_insn_args): Add mips_opcode argument.
 214         (print_insn_mips):  Adjust print_insn_args call.
 215
 216 2006-04-28  Thiemo Seufer  <ths@mips.com>
 217             Nigel Stephens  <nigel@mips.com>
 218
 219         * mips-dis.c (print_insn_args): Print $fcc only for FP
 220         instructions, use $cc elsewise.
 221
 222 2006-04-28  Thiemo Seufer  <ths@mips.com>
 223             Nigel Stephens  <nigel@mips.com>
 224
 225         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
 226         Map MIPS16 registers to O32 names.
 227         (print_mips16_insn_arg): Use mips16_reg_names.
 228
 229 2006-04-26  Julian Brown  <julian@codesourcery.com>
 230
 231         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
 232         VMOV.
 233
 234 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
 235             Julian Brown  <julian@codesourcery.com>
 236
 237         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
 238         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
 239         Add unified load/store instruction names.
 240         (neon_opcode_table): New.
 241         (arm_opcodes): Expand meaning of %<bitfield>['`?].
 242         (arm_decode_bitfield): New.
 243         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
 244         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
 245         (print_insn_neon): New.
 246         (print_insn_arm): Adjust print_insn_coprocessor call. Call
 247         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
 248         (print_insn_thumb32): Likewise.
 249
 250 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 251
 252         * Makefile.am: Run "make dep-am".
 253         * Makefile.in: Regenerate.
 254
 255 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
 256
 257         * avr-dis.c (avr_operand): Warning fix.
 258
 259         * configure: Regenerate.
 260
 261 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
 262
 263         * po/POTFILES.in: Regenerated.
 264
 265 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
 266
 267         PR binutils/2454
 268         * avr-dis.c (avr_operand): Arrange for a comment to appear before
 269         the symolic form of an address, so that the output of objdump -d
 270         can be reassembled.
 271
 272 2006-04-10  DJ Delorie  <dj@redhat.com>
 273
 274         * m32c-asm.c: Regenerate.
 275
 276 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
 277
 278         * Makefile.am: Add install-html target.
 279         * Makefile.in: Regenerate.
 280
 281 2006-04-06  Nick Clifton  <nickc@redhat.com>
 282
 283         * po/vi/po: Updated Vietnamese translation.
 284
 285 2006-03-31  Paul Koning  <ni1d@arrl.net>
 286
 287         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
 288
 289 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 290
 291         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
 292         logic to identify halfword shifts.
 293
 294 2006-03-16  Paul Brook  <paul@codesourcery.com>
 295
 296         * arm-dis.c (arm_opcodes): Rename swi to svc.
 297         (thumb_opcodes): Ditto.
 298
 299 2006-03-13  DJ Delorie  <dj@redhat.com>
 300
 301         * m32c-asm.c: Regenerate.
 302         * m32c-desc.c: Likewise.
 303         * m32c-desc.h: Likewise.
 304         * m32c-dis.c: Likewise.
 305         * m32c-ibld.c: Likewise.
 306         * m32c-opc.c: Likewise.
 307         * m32c-opc.h: Likewise.
 308
 309 2006-03-10  DJ Delorie  <dj@redhat.com>
 310
 311         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 312         * m32c-opc.c: Likewise.
 313         * m32c-opc.h: Likewise.
 314
 315
 316 2006-03-09  Nick Clifton  <nickc@redhat.com>
 317
 318         * po/sv.po: Updated Swedish translation.
 319
 320 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 321
 322         PR binutils/2428
 323         * i386-dis.c (REP_Fixup): New function.
 324         (AL): Remove duplicate.
 325         (Xbr): New.
 326         (Xvr): Likewise.
 327         (Ybr): Likewise.
 328         (Yvr): Likewise.
 329         (indirDXr): Likewise.
 330         (ALr): Likewise.
 331         (eAXr): Likewise.
 332         (dis386): Updated entries of ins, outs, movs, lods and stos.
 333
 334 2006-03-05  Nick Clifton  <nickc@redhat.com>
 335
 336         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 337         signed 32-bit value into an unsigned 32-bit field when the host is
 338         a 64-bit machine.
 339         * fr30-ibld.c: Regenerate.
 340         * frv-ibld.c: Regenerate.
 341         * ip2k-ibld.c: Regenerate.
 342         * iq2000-asm.c: Regenerate.
 343         * iq2000-ibld.c: Regenerate.
 344         * m32c-ibld.c: Regenerate.
 345         * m32r-ibld.c: Regenerate.
 346         * openrisc-ibld.c: Regenerate.
 347         * xc16x-ibld.c: Regenerate.
 348         * xstormy16-ibld.c: Regenerate.
 349
 350 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 351
 352         * xc16x-asm.c: Regenerate.
 353         * xc16x-dis.c: Regenerate.
 354
 355 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 356
 357         * po/Make-in: Add html target.
 358
 359 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 360
 361         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 362         Intel Merom New Instructions.
 363         (THREE_BYTE_0): Likewise.
 364         (THREE_BYTE_1): Likewise.
 365         (three_byte_table): Likewise.
 366         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 367         THREE_BYTE_1 for entry 0x3a.
 368         (twobyte_has_modrm): Updated.
 369         (twobyte_uses_SSE_prefix): Likewise.
 370         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 371         Instructions.
 372
 373 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 374
 375         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 376         (v9_hpriv_reg_names): New table.
 377         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 378         New cases '$' and '%' for read/write hyperprivileged register.
 379         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 380         window handling and rdhpr/wrhpr instructions.
 381
 382 2006-02-24  DJ Delorie  <dj@redhat.com>
 383
 384         * m32c-desc.c: Regenerate with linker relaxation attributes.
 385         * m32c-desc.h: Likewise.
 386         * m32c-dis.c: Likewise.
 387         * m32c-opc.c: Likewise.
 388
 389 2006-02-24  Paul Brook  <paul@codesourcery.com>
 390
 391         * arm-dis.c (arm_opcodes): Add V7 instructions.
 392         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 393         (print_arm_address): New function.
 394         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 395         (psr_name): New function.
 396         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 397
 398 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         * ia64-opc-i.c (bXc): New.
 401         (mXc): Likewise.
 402         (OpX2TaTbYaXcC): Likewise.
 403         (TF). Likewise.
 404         (TFCM). Likewise.
 405         (ia64_opcodes_i): Add instructions for tf.
 406
 407         * ia64-opc.h (IMMU5b): New.
 408
 409         * ia64-asmtab.c: Regenerated.
 410
 411 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 412
 413         * ia64-gen.c: Update copyright years.
 414         * ia64-opc-b.c: Likewise.
 415
 416 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 417
 418         * ia64-gen.c (lookup_regindex): Handle ".vm".
 419         (print_dependency_table): Handle '\"'.
 420
 421         * ia64-ic.tbl: Updated from SDM 2.2.
 422         * ia64-raw.tbl: Likewise.
 423         * ia64-waw.tbl: Likewise.
 424         * ia64-asmtab.c: Regenerated.
 425
 426         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 427
 428 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 429             Anil Paranjape   <anilp1@kpitcummins.com>
 430             Shilin Shakti    <shilins@kpitcummins.com>
 431
 432         * xc16x-desc.h: New file
 433         * xc16x-desc.c: New file
 434         * xc16x-opc.h: New file
 435         * xc16x-opc.c: New file
 436         * xc16x-ibld.c: New file
 437         * xc16x-asm.c: New file
 438         * xc16x-dis.c: New file
 439         * Makefile.am: Entries for xc16x
 440         * Makefile.in: Regenerate
 441         * cofigure.in: Add xc16x target information.
 442         * configure: Regenerate.
 443         * disassemble.c: Add xc16x target information.
 444
 445 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 446
 447         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 448         moves.
 449
 450 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-dis.c ('Z'): Add a new macro.
 453         (dis386_twobyte): Use "movZ" for control register moves.
 454
 455 2006-02-10  Nick Clifton  <nickc@redhat.com>
 456
 457         * iq2000-asm.c: Regenerate.
 458
 459 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 460
 461         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 462
 463 2006-01-26  David Ung  <davidu@mips.com>
 464
 465         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 466         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 467         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 468         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 469         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 470
 471 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 472
 473         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 474         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 475         disassembled.
 476         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 477         buffer overflows when disassembling instructions like
 478         ld (ix+123),0x23
 479         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 480         operand, if the offset is negative.
 481
 482 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 483
 484         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 485         unsigned char to hold data to be disassembled.
 486
 487 2006-01-17  Andreas Schwab  <schwab@suse.de>
 488
 489         PR binutils/1486
 490         * disassemble.c (disassemble_init_for_target): Set
 491         disassembler_needs_relocs for bfd_arch_arm.
 492
 493 2006-01-16  Paul Brook  <paul@codesourcery.com>
 494
 495         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 496         f?add?, and f?sub? instructions.
 497
 498 2006-01-16  Nick Clifton  <nickc@redhat.com>
 499
 500         * po/zh_CN.po: New Chinese (simplified) translation.
 501         * configure.in (ALL_LINGUAS): Add "zh_CH".
 502         * configure: Regenerate.
 503
 504 2006-01-05  Paul Brook  <paul@codesourcery.com>
 505
 506         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 507
 508 2006-01-06  DJ Delorie  <dj@redhat.com>
 509
 510         * m32c-desc.c: Regenerate.
 511         * m32c-opc.c: Regenerate.
 512         * m32c-opc.h: Regenerate.
 513
 514 2006-01-03  DJ Delorie  <dj@redhat.com>
 515
 516         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 517         * m32c-ibld.c: Regenerated.
 518
 519 For older changes see ChangeLog-2005
 520 \f
 521 Local Variables:
 522 mode: change-log
 523 left-margin: 8
 524 fill-column: 74
 525 version-control: never
 526 End: