opcodes/ChangeLog

   1 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
   4         * i386-init.h: Regenerated.
   5
   6 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR binutis/18386
   9         * i386-dis.c: Add comments for '@'.
  10         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
  11         (enum x86_64_isa): New.
  12         (isa64): Likewise.
  13         (print_i386_disassembler_options): Add amd64 and intel64.
  14         (print_insn): Handle amd64 and intel64.
  15         (putop): Handle '@'.
  16         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
  17         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
  18         * i386-opc.h (AMD64): New.
  19         (CpuIntel64): Likewise.
  20         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
  21         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
  22         Mark direct call/jmp without Disp16|Disp32 as Intel64.
  23         * i386-init.h: Regenerated.
  24         * i386-tbl.h: Likewise.
  25
  26 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
  27
  28         * ppc-opc.c (IH) New define.
  29         (powerpc_opcodes) <wait>: Do not enable for POWER7.
  30         <tlbie>: Add RS operand for POWER7.
  31         <slbia>: Add IH operand for POWER6.
  32
  33 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
  36         direct branch.
  37         (jmp): Likewise.
  38         * i386-tbl.h: Regenerated.
  39
  40 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
  41
  42         * configure.ac: Support bfd_iamcu_arch.
  43         * disassemble.c (disassembler): Support bfd_iamcu_arch.
  44         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
  45         CPU_IAMCU_COMPAT_FLAGS.
  46         (cpu_flags): Add CpuIAMCU.
  47         * i386-opc.h (CpuIAMCU): New.
  48         (i386_cpu_flags): Add cpuiamcu.
  49         * configure: Regenerated.
  50         * i386-init.h: Likewise.
  51         * i386-tbl.h: Likewise.
  52
  53 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         PR binutis/18386
  56         * i386-dis.c (X86_64_E8): New.
  57         (X86_64_E9): Likewise.
  58         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
  59         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
  60         (x86_64_table): Add X86_64_E8 and X86_64_E9.
  61         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
  62         (putop): Handle '^'.
  63         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
  64         REX_W.
  65
  66 2015-04-30  DJ Delorie  <dj@redhat.com>
  67
  68         * disassemble.c (disassembler): Choose suitable disassembler based
  69         on E_ABI.
  70         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
  71         it to decode mul/div insns.
  72         * rl78-decode.c: Regenerate.
  73         * rl78-dis.c (print_insn_rl78): Rename to...
  74         (print_insn_rl78_common): ...this, take ISA parameter.
  75         (print_insn_rl78): New.
  76         (print_insn_rl78_g10): New.
  77         (print_insn_rl78_g13): New.
  78         (print_insn_rl78_g14): New.
  79         (rl78_get_disassembler): New.
  80
  81 2015-04-29  Nick Clifton  <nickc@redhat.com>
  82
  83         * po/fr.po: Updated French translation.
  84
  85 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
  86
  87         * ppc-opc.c (DCBT_EO): New define.
  88         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
  89         <lharx>: Likewise.
  90         <stbcx.>: Likewise.
  91         <sthcx.>: Likewise.
  92         <waitrsv>: Do not enable for POWER7 and later.
  93         <waitimpl>: Likewise.
  94         <dcbt>: Default to the two operand form of the instruction for all
  95         "old" cpus.  For "new" cpus, use the operand ordering that matches
  96         whether the cpu is server or embedded.
  97         <dcbtst>: Likewise.
  98
  99 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 100
 101         * s390-opc.c: New instruction type VV0UU2.
 102         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 103         and WFC.
 104
 105 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 108         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 109         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 110         (vfpclasspd, vfpclassps): Add %XZ.
 111
 112 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 113
 114         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 115         (PREFIX_UD_REPZ): Likewise.
 116         (PREFIX_UD_REPNZ): Likewise.
 117         (PREFIX_UD_DATA): Likewise.
 118         (PREFIX_UD_ADDR): Likewise.
 119         (PREFIX_UD_LOCK): Likewise.
 120
 121 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 122
 123         * i386-dis.c (prefix_requirement): Removed.
 124         (print_insn): Don't set prefix_requirement.  Check
 125         dp->prefix_requirement instead of prefix_requirement.
 126
 127 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 128
 129         PR binutils/17898
 130         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 131         (PREFIX_MOD_0_0FC7_REG_6): This.
 132         (PREFIX_MOD_3_0FC7_REG_6): New.
 133         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 134         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 135         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 136         PREFIX_MOD_3_0FC7_REG_7.
 137         (mod_table): Replace PREFIX_0FC7_REG_6 with
 138         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 139         PREFIX_MOD_3_0FC7_REG_7.
 140
 141 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 144         (PREFIX_MANDATORY_REPNZ): Likewise.
 145         (PREFIX_MANDATORY_DATA): Likewise.
 146         (PREFIX_MANDATORY_ADDR): Likewise.
 147         (PREFIX_MANDATORY_LOCK): Likewise.
 148         (PREFIX_MANDATORY): Likewise.
 149         (PREFIX_UD_SHIFT): Set to 8
 150         (PREFIX_UD_REPZ): Updated.
 151         (PREFIX_UD_REPNZ): Likewise.
 152         (PREFIX_UD_DATA): Likewise.
 153         (PREFIX_UD_ADDR): Likewise.
 154         (PREFIX_UD_LOCK): Likewise.
 155         (PREFIX_IGNORED_SHIFT): New.
 156         (PREFIX_IGNORED_REPZ): Likewise.
 157         (PREFIX_IGNORED_REPNZ): Likewise.
 158         (PREFIX_IGNORED_DATA): Likewise.
 159         (PREFIX_IGNORED_ADDR): Likewise.
 160         (PREFIX_IGNORED_LOCK): Likewise.
 161         (PREFIX_OPCODE): Likewise.
 162         (PREFIX_IGNORED): Likewise.
 163         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 164         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 165         (three_byte_table): Likewise.
 166         (mod_table): Likewise.
 167         (mandatory_prefix): Renamed to ...
 168         (prefix_requirement): This.
 169         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 170         Update PREFIX_90 entry.
 171         (get_valid_dis386): Check prefix_requirement to see if a prefix
 172         should be ignored.
 173         (print_insn): Replace mandatory_prefix with prefix_requirement.
 174
 175 2015-04-15  Renlin Li  <renlin.li@arm.com>
 176
 177         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 178         use it for ssat and ssat16.
 179         (print_insn_thumb32): Add handle case for 'D' control code.
 180
 181 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 182             H.J. Lu  <hongjiu.lu@intel.com>
 183
 184         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 185         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 186         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 187         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 188         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 189         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 190         Fill prefix_requirement field.
 191         (struct dis386): Add prefix_requirement field.
 192         (dis386): Fill prefix_requirement field.
 193         (dis386_twobyte): Ditto.
 194         (twobyte_has_mandatory_prefix_: Remove.
 195         (reg_table): Fill prefix_requirement field.
 196         (prefix_table): Ditto.
 197         (x86_64_table): Ditto.
 198         (three_byte_table): Ditto.
 199         (xop_table): Ditto.
 200         (vex_table): Ditto.
 201         (vex_len_table): Ditto.
 202         (vex_w_table): Ditto.
 203         (mod_table): Ditto.
 204         (bad_opcode): Ditto.
 205         (print_insn): Use prefix_requirement.
 206         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 207         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 208         (float_reg): Ditto.
 209
 210 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 211
 212         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 213
 214 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * Makefile.in: Regenerated.
 217
 218 2015-03-25  Anton Blanchard  <anton@samba.org>
 219
 220         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 221         powerpc_opcd_indices and vle_opcd_indices once.
 222
 223 2015-03-25  Anton Blanchard  <anton@samba.org>
 224
 225         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 226
 227 2015-03-24  Terry Guo  <terry.guo@arm.com>
 228
 229         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 230         (opcode16): Likewise.
 231         (coprocessor_opcodes): Replace bit with feature struct.
 232         (neon_opcodes): Likewise.
 233         (arm_opcodes): Likewise.
 234         (thumb_opcodes): Likewise.
 235         (thumb32_opcodes): Likewise.
 236         (print_insn_coprocessor): Likewise.
 237         (print_insn_arm): Likewise.
 238         (select_arm_features): Follow new feature struct.
 239
 240 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 241
 242         * i386-dis.c (rm_table): Add clzero.
 243         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 244         Add CPU_CLZERO_FLAGS.
 245         (cpu_flags): Add CpuCLZERO.
 246         * i386-opc.h: Add CpuCLZERO.
 247         * i386-opc.tbl: Add clzero.
 248         * i386-init.h: Re-generated.
 249         * i386-tbl.h: Re-generated.
 250
 251 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 252
 253         * mips-opc.c (decode_mips_operand): Fix constraint issues
 254         with u and y operands.
 255
 256 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 257
 258         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 259
 260 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 261
 262         * s390-opc.c: Add new IBM z13 instructions.
 263         * s390-opc.txt: Likewise.
 264
 265 2015-03-10  Renlin Li  <renlin.li@arm.com>
 266
 267         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 268         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 269         related alias.
 270         * aarch64-asm-2.c: Regenerate.
 271         * aarch64-dis-2.c: Likewise.
 272         * aarch64-opc-2.c: Likewise.
 273
 274 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 275
 276         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 277
 278 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 279
 280         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 281         arch_sh_up.
 282         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 283         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 284
 285 2015-02-23  Vinay  <Vinay.G@kpit.com>
 286
 287         * rl78-decode.opc (MOV): Added space between two operands for
 288         'mov' instruction in index addressing mode.
 289         * rl78-decode.c: Regenerate.
 290
 291 2015-02-19  Pedro Alves  <palves@redhat.com>
 292
 293         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 294
 295 2015-02-10  Pedro Alves  <palves@redhat.com>
 296             Tom Tromey  <tromey@redhat.com>
 297
 298         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 299         microblaze_and, microblaze_xor.
 300         * microblaze-opc.h (opcodes): Adjust.
 301
 302 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 303
 304         * Makefile.am: Add FT32 files.
 305         * configure.ac: Handle FT32.
 306         * disassemble.c (disassembler): Call print_insn_ft32.
 307         * ft32-dis.c: New file.
 308         * ft32-opc.c: New file.
 309         * Makefile.in: Regenerate.
 310         * configure: Regenerate.
 311         * po/POTFILES.in: Regenerate.
 312
 313 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 314
 315         * nds32-asm.c (keyword_sr): Add new system registers.
 316
 317 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 318
 319         * s390-dis.c (s390_extract_operand): Support vector register
 320         operands.
 321         (s390_print_insn_with_opcode): Support new operands types and add
 322         new handling of optional operands.
 323         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 324         and include opcode/s390.h instead.
 325         (struct op_struct): New field `flags'.
 326         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 327         (dumpTable): Dump flags.
 328         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 329         string.
 330         * s390-opc.c: Add new operands types, instruction formats, and
 331         instruction masks.
 332         (s390_opformats): Add new formats for .insn.
 333         * s390-opc.txt: Add new instructions.
 334
 335 2015-01-01  Alan Modra  <amodra@gmail.com>
 336
 337         Update year range in copyright notice of all files.
 338
 339 For older changes see ChangeLog-2014
 340 \f
 341 Copyright (C) 2015 Free Software Foundation, Inc.
 342
 343 Copying and distribution of this file, with or without modification,
 344 are permitted in any medium without royalty provided the copyright
 345 notice and this notice are preserved.
 346
 347 Local Variables:
 348 mode: change-log
 349 left-margin: 8
 350 fill-column: 74
 351 version-control: never
 352 End: