opcodes/ChangeLog

   1 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutis/18386
   4         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
   5         (indir_v_mode): New.
   6         Add comments for '&'.
   7         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
   8         (putop): Handle '&'.
   9         (intel_operand_size): Handle indir_v_mode.
  10         (OP_E_register): Likewise.
  11         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
  12         64-bit indirect call/jmp for AMD64.
  13         * i386-tbl.h: Regenerated
  14
  15 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
  16
  17         * arc-dis.c (struct arc_operand_iterator): New structure.
  18         (find_format_from_table): All the old content from find_format,
  19         with some minor adjustments, and parameter renaming.
  20         (find_format_long_instructions): New function.
  21         (find_format): Rewritten.
  22         (arc_insn_length): Add LSB parameter.
  23         (extract_operand_value): New function.
  24         (operand_iterator_next): New function.
  25         (print_insn_arc): Use new functions to find opcode, and iterator
  26         over operands.
  27         * arc-opc.c (insert_nps_3bit_dst_short): New function.
  28         (extract_nps_3bit_dst_short): New function.
  29         (insert_nps_3bit_src2_short): New function.
  30         (extract_nps_3bit_src2_short): New function.
  31         (insert_nps_bitop1_size): New function.
  32         (extract_nps_bitop1_size): New function.
  33         (insert_nps_bitop2_size): New function.
  34         (extract_nps_bitop2_size): New function.
  35         (insert_nps_bitop_mod4_msb): New function.
  36         (extract_nps_bitop_mod4_msb): New function.
  37         (insert_nps_bitop_mod4_lsb): New function.
  38         (extract_nps_bitop_mod4_lsb): New function.
  39         (insert_nps_bitop_dst_pos3_pos4): New function.
  40         (extract_nps_bitop_dst_pos3_pos4): New function.
  41         (insert_nps_bitop_ins_ext): New function.
  42         (extract_nps_bitop_ins_ext): New function.
  43         (arc_operands): Add new operands.
  44         (arc_long_opcodes): New global array.
  45         (arc_num_long_opcodes): New global.
  46         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
  47
  48 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  49
  50         * nds32-asm.h: Add extern "C".
  51         * sh-opc.h: Likewise.
  52
  53 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
  54
  55         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
  56         0,b,limm to the rflt instruction.
  57
  58 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  59
  60         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
  61         constant.
  62
  63 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         PR gas/20145
  66         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
  67         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
  68         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
  69         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
  70         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
  71         * i386-init.h: Regenerated.
  72
  73 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
  74
  75         PR gas/20145
  76         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
  77         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
  78         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
  79         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
  80         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
  81         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
  82         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
  83         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
  84         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
  85         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
  86         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
  87         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
  88         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
  89         CpuRegMask for AVX512.
  90         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
  91         and CpuRegMask.
  92         (set_bitfield_from_cpu_flag_init): New function.
  93         (set_bitfield): Remove const on f.  Call
  94         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
  95         * i386-opc.h (CpuRegMMX): New.
  96         (CpuRegXMM): Likewise.
  97         (CpuRegYMM): Likewise.
  98         (CpuRegZMM): Likewise.
  99         (CpuRegMask): Likewise.
 100         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 101         and cpuregmask.
 102         * i386-init.h: Regenerated.
 103         * i386-tbl.h: Likewise.
 104
 105 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 106
 107         PR gas/20154
 108         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 109         (opcode_modifiers): Add AMD64 and Intel64.
 110         (main): Properly verify CpuMax.
 111         * i386-opc.h (CpuAMD64): Removed.
 112         (CpuIntel64): Likewise.
 113         (CpuMax): Set to CpuNo64.
 114         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 115         (AMD64): New.
 116         (Intel64): Likewise.
 117         (i386_opcode_modifier): Add amd64 and intel64.
 118         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 119         on call and jmp.
 120         * i386-init.h: Regenerated.
 121         * i386-tbl.h: Likewise.
 122
 123 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         PR gas/20154
 126         * i386-gen.c (main): Fail if CpuMax is incorrect.
 127         * i386-opc.h (CpuMax): Set to CpuIntel64.
 128         * i386-tbl.h: Regenerated.
 129
 130 2016-05-27  Nick Clifton  <nickc@redhat.com>
 131
 132         PR target/20150
 133         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 134         (msp430dis_opcode_unsigned): New function.
 135         (msp430dis_opcode_signed): New function.
 136         (msp430_singleoperand): Use the new opcode reading functions.
 137         Only disassenmble bytes if they were successfully read.
 138         (msp430_doubleoperand): Likewise.
 139         (msp430_branchinstr): Likewise.
 140         (msp430x_callx_instr): Likewise.
 141         (print_insn_msp430): Check that it is safe to read bytes before
 142         attempting disassembly.  Use the new opcode reading functions.
 143
 144 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 145
 146         * ppc-opc.c (CY): New define.  Document it.
 147         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 148
 149 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 152         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 153         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 154         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 155         CPU_ANY_AVX_FLAGS.
 156         * i386-init.h: Regenerated.
 157
 158 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         PR gas/20141
 161         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 162         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 163         * i386-init.h: Regenerated.
 164
 165 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 166
 167         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 168         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 169         * i386-init.h: Regenerated.
 170
 171 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 172
 173         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 174         information.
 175         (print_insn_arc): Set insn_type information.
 176         * arc-opc.c (C_CC): Add F_CLASS_COND.
 177         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 178         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 179         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 180         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 181         (brne, brne_s, jeq_s, jne_s): Likewise.
 182
 183 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 184
 185         * arc-tbl.h (neg): New instruction variant.
 186
 187 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 188
 189         * arc-dis.c (find_format, find_format, get_auxreg)
 190         (print_insn_arc): Changed.
 191         * arc-ext.h (INSERT_XOP): Likewise.
 192
 193 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 194
 195         * tic54x-dis.c (sprint_mmr): Adjust.
 196         * tic54x-opc.c: Likewise.
 197
 198 2016-05-19  Alan Modra  <amodra@gmail.com>
 199
 200         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 201
 202 2016-05-19  Alan Modra  <amodra@gmail.com>
 203
 204         * ppc-opc.c: Formatting.
 205         (NSISIGNOPT): Define.
 206         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 207
 208 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 209
 210         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 211         replacing references to `micromips_ase' throughout.
 212         (_print_insn_mips): Don't use file-level microMIPS annotation to
 213         determine the disassembly mode with the symbol table.
 214
 215 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 216
 217         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 218
 219 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 220
 221         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 222         mips64r6.
 223         * mips-opc.c (D34): New macro.
 224         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 225
 226 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 227
 228         * i386-dis.c (prefix_table): Add RDPID instruction.
 229         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 230         (cpu_flags): Add RDPID bitfield.
 231         * i386-opc.h (enum): Add RDPID element.
 232         (i386_cpu_flags): Add RDPID field.
 233         * i386-opc.tbl: Add RDPID instruction.
 234         * i386-init.h: Regenerate.
 235         * i386-tbl.h: Regenerate.
 236
 237 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 238
 239         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 240         branch type of a symbol.
 241         (print_insn): Likewise.
 242
 243 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 244
 245         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 246         Mainline Security Extensions instructions.
 247         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 248         Extensions instructions.
 249         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 250         instructions.
 251         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 252         special registers.
 253
 254 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 255
 256         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 257
 258 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 259
 260         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 261         (arcExtMap_genOpcode): Likewise.
 262         * arc-opc.c (arg_32bit_rc): Define new variable.
 263         (arg_32bit_u6): Likewise.
 264         (arg_32bit_limm): Likewise.
 265
 266 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 267
 268         * aarch64-gen.c (VERIFIER): Define.
 269         * aarch64-opc.c (VERIFIER): Define.
 270         (verify_ldpsw): Use static linkage.
 271         * aarch64-opc.h (verify_ldpsw): Remove.
 272         * aarch64-tbl.h: Use VERIFIER for verifiers.
 273
 274 2016-04-28  Nick Clifton  <nickc@redhat.com>
 275
 276         PR target/19722
 277         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 278         * aarch64-opc.c (verify_ldpsw): New function.
 279         * aarch64-opc.h (verify_ldpsw): New prototype.
 280         * aarch64-tbl.h: Add initialiser for verifier field.
 281         (LDPSW): Set verifier to verify_ldpsw.
 282
 283 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 284
 285         PR binutils/19983
 286         PR binutils/19984
 287         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 288         smaller than address size.
 289
 290 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 291
 292         * alpha-dis.c: Regenerate.
 293         * crx-dis.c: Likewise.
 294         * disassemble.c: Likewise.
 295         * epiphany-opc.c: Likewise.
 296         * fr30-opc.c: Likewise.
 297         * frv-opc.c: Likewise.
 298         * ip2k-opc.c: Likewise.
 299         * iq2000-opc.c: Likewise.
 300         * lm32-opc.c: Likewise.
 301         * lm32-opinst.c: Likewise.
 302         * m32c-opc.c: Likewise.
 303         * m32r-opc.c: Likewise.
 304         * m32r-opinst.c: Likewise.
 305         * mep-opc.c: Likewise.
 306         * mt-opc.c: Likewise.
 307         * or1k-opc.c: Likewise.
 308         * or1k-opinst.c: Likewise.
 309         * tic80-opc.c: Likewise.
 310         * xc16x-opc.c: Likewise.
 311         * xstormy16-opc.c: Likewise.
 312
 313 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 314
 315         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 316         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 317         calcsd, and calcxd instructions.
 318         * arc-opc.c (insert_nps_bitop_size): Delete.
 319         (extract_nps_bitop_size): Delete.
 320         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 321         (extract_nps_qcmp_m3): Define.
 322         (extract_nps_qcmp_m2): Define.
 323         (extract_nps_qcmp_m1): Define.
 324         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 325         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 326         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 327         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 328         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 329         NPS_QCMP_M3.
 330
 331 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 332
 333         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 334
 335 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         * Makefile.in: Regenerated with automake 1.11.6.
 338         * aclocal.m4: Likewise.
 339
 340 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 341
 342         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 343         instructions.
 344         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 345         (extract_nps_cmem_uimm16): New function.
 346         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 347
 348 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 349
 350         * arc-dis.c (arc_insn_length): New function.
 351         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 352         (find_format): Change insnLen parameter to unsigned.
 353
 354 2016-04-13  Nick Clifton  <nickc@redhat.com>
 355
 356         PR target/19937
 357         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 358         the LD.B and LD.BU instructions.
 359
 360 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 361
 362         * arc-dis.c (find_format): Check for extension flags.
 363         (print_flags): New function.
 364         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 365         .extAuxRegister.
 366         * arc-ext.c (arcExtMap_coreRegName): Use
 367         LAST_EXTENSION_CORE_REGISTER.
 368         (arcExtMap_coreReadWrite): Likewise.
 369         (dump_ARC_extmap): Update printing.
 370         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 371         (arc_aux_regs): Add cpu field.
 372         * arc-regs.h: Add cpu field, lower case name aux registers.
 373
 374 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 375
 376         * arc-tbl.h: Add rtsc, sleep with no arguments.
 377
 378 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 379
 380         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 381         Initialize.
 382         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 383         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 384         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 385         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 386         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 387         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 388         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 389         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 390         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 391         (arc_opcode arc_opcodes): Null terminate the array.
 392         (arc_num_opcodes): Remove.
 393         * arc-ext.h (INSERT_XOP): Define.
 394         (extInstruction_t): Likewise.
 395         (arcExtMap_instName): Delete.
 396         (arcExtMap_insn): New function.
 397         (arcExtMap_genOpcode): Likewise.
 398         * arc-ext.c (ExtInstruction): Remove.
 399         (create_map): Zero initialize instruction fields.
 400         (arcExtMap_instName): Remove.
 401         (arcExtMap_insn): New function.
 402         (dump_ARC_extmap): More info while debuging.
 403         (arcExtMap_genOpcode): New function.
 404         * arc-dis.c (find_format): New function.
 405         (print_insn_arc): Use find_format.
 406         (arc_get_disassembler): Enable dump_ARC_extmap only when
 407         debugging.
 408
 409 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 410
 411         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 412         instruction bits out.
 413
 414 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 415
 416         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 417         * arc-opc.c (arc_flag_operands): Add new flags.
 418         (arc_flag_classes): Add new classes.
 419
 420 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 421
 422         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 423
 424 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 425
 426         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 427         encode1, rflt, crc16, and crc32 instructions.
 428         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 429         (arc_flag_classes): Add C_NPS_R.
 430         (insert_nps_bitop_size_2b): New function.
 431         (extract_nps_bitop_size_2b): Likewise.
 432         (insert_nps_bitop_uimm8): Likewise.
 433         (extract_nps_bitop_uimm8): Likewise.
 434         (arc_operands): Add new operand entries.
 435
 436 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 437
 438         * arc-regs.h: Add a new subclass field.  Add double assist
 439         accumulator register values.
 440         * arc-tbl.h: Use DPA subclass to mark the double assist
 441         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 442         * arc-opc.c (RSP): Define instead of SP.
 443         (arc_aux_regs): Add the subclass field.
 444
 445 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 446
 447         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 448
 449 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 450
 451         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 452         NPS_R_SRC1.
 453
 454 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 455
 456         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 457         issues.  No functional changes.
 458
 459 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 460
 461         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 462         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 463         (RTT): Remove duplicate.
 464         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 465         (PCT_CONFIG*): Remove.
 466         (D1L, D1H, D2H, D2L): Define.
 467
 468 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 469
 470         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 471
 472 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 473
 474         * arc-tbl.h (invld07): Remove.
 475         * arc-ext-tbl.h: New file.
 476         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 477         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 478
 479 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 480
 481         Fix -Wstack-usage warnings.
 482         * aarch64-dis.c (print_operands): Substitute size.
 483         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 484
 485 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 486
 487         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 488         to get a proper diagnostic when an invalid ASR register is used.
 489
 490 2016-03-22  Nick Clifton  <nickc@redhat.com>
 491
 492         * configure: Regenerate.
 493
 494 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 495
 496         * arc-nps400-tbl.h: New file.
 497         * arc-opc.c: Add top level comment.
 498         (insert_nps_3bit_dst): New function.
 499         (extract_nps_3bit_dst): New function.
 500         (insert_nps_3bit_src2): New function.
 501         (extract_nps_3bit_src2): New function.
 502         (insert_nps_bitop_size): New function.
 503         (extract_nps_bitop_size): New function.
 504         (arc_flag_operands): Add nps400 entries.
 505         (arc_flag_classes): Add nps400 entries.
 506         (arc_operands): Add nps400 entries.
 507         (arc_opcodes): Add nps400 include.
 508
 509 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 510
 511         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 512         the new class enum values.
 513
 514 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 515
 516         * arc-dis.c (print_insn_arc): Handle nps400.
 517
 518 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 519
 520         * arc-opc.c (BASE): Delete.
 521
 522 2016-03-18  Nick Clifton  <nickc@redhat.com>
 523
 524         PR target/19721
 525         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 526         of MOV insn that aliases an ORR insn.
 527
 528 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 529
 530         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 531
 532 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 533
 534         * mcore-opc.h: Add const qualifiers.
 535         * microblaze-opc.h (struct op_code_struct): Likewise.
 536         * sh-opc.h: Likewise.
 537         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 538         (tic4x_print_op): Likewise.
 539
 540 2016-03-02  Alan Modra  <amodra@gmail.com>
 541
 542         * or1k-desc.h: Regenerate.
 543         * fr30-ibld.c: Regenerate.
 544         * rl78-decode.c: Regenerate.
 545
 546 2016-03-01  Nick Clifton  <nickc@redhat.com>
 547
 548         PR target/19747
 549         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 550
 551 2016-02-24  Renlin Li  <renlin.li@arm.com>
 552
 553         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 554         (print_insn_coprocessor): Support fp16 instructions.
 555
 556 2016-02-24  Renlin Li  <renlin.li@arm.com>
 557
 558         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 559         vminnm, vrint(mpna).
 560
 561 2016-02-24  Renlin Li  <renlin.li@arm.com>
 562
 563         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 564         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 565
 566 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 567
 568         * i386-dis.c (print_insn): Parenthesize expression to prevent
 569         truncated addresses.
 570         (OP_J): Likewise.
 571
 572 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 573             Janek van Oirschot  <jvanoirs@synopsys.com>
 574
 575         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 576         variable.
 577
 578 2016-02-04  Nick Clifton  <nickc@redhat.com>
 579
 580         PR target/19561
 581         * msp430-dis.c (print_insn_msp430): Add a special case for
 582         decoding an RRC instruction with the ZC bit set in the extension
 583         word.
 584
 585 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 586
 587         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 588         * epiphany-ibld.c: Regenerate.
 589         * fr30-ibld.c: Regenerate.
 590         * frv-ibld.c: Regenerate.
 591         * ip2k-ibld.c: Regenerate.
 592         * iq2000-ibld.c: Regenerate.
 593         * lm32-ibld.c: Regenerate.
 594         * m32c-ibld.c: Regenerate.
 595         * m32r-ibld.c: Regenerate.
 596         * mep-ibld.c: Regenerate.
 597         * mt-ibld.c: Regenerate.
 598         * or1k-ibld.c: Regenerate.
 599         * xc16x-ibld.c: Regenerate.
 600         * xstormy16-ibld.c: Regenerate.
 601
 602 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 603
 604         * epiphany-dis.c: Regenerated from latest cpu files.
 605
 606 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 607
 608         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 609         test bit.
 610
 611 2016-01-25  Renlin Li  <renlin.li@arm.com>
 612
 613         * arm-dis.c (mapping_symbol_for_insn): New function.
 614         (find_ifthen_state): Call mapping_symbol_for_insn().
 615
 616 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 617
 618         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 619         of MSR UAO immediate operand.
 620
 621 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 622
 623         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 624         instruction support.
 625
 626 2016-01-17  Alan Modra  <amodra@gmail.com>
 627
 628         * configure: Regenerate.
 629
 630 2016-01-14  Nick Clifton  <nickc@redhat.com>
 631
 632         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 633         instructions that can support stack pointer operations.
 634         * rl78-decode.c: Regenerate.
 635         * rl78-dis.c: Fix display of stack pointer in MOVW based
 636         instructions.
 637
 638 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 639
 640         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 641         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 642         erxtatus_el1 and erxaddr_el1.
 643
 644 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 645
 646         * arm-dis.c (arm_opcodes): Add "esb".
 647         (thumb_opcodes): Likewise.
 648
 649 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 650
 651         * ppc-opc.c <xscmpnedp>: Delete.
 652         <xvcmpnedp>: Likewise.
 653         <xvcmpnedp.>: Likewise.
 654         <xvcmpnesp>: Likewise.
 655         <xvcmpnesp.>: Likewise.
 656
 657 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 658
 659         PR gas/13050
 660         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 661         addition to ISA_A.
 662
 663 2016-01-01  Alan Modra  <amodra@gmail.com>
 664
 665         Update year range in copyright notice of all files.
 666
 667 For older changes see ChangeLog-2015
 668 \f
 669 Copyright (C) 2016 Free Software Foundation, Inc.
 670
 671 Copying and distribution of this file, with or without modification,
 672 are permitted in any medium without royalty provided the copyright
 673 notice and this notice are preserved.
 674
 675 Local Variables:
 676 mode: change-log
 677 left-margin: 8
 678 fill-column: 74
 679 version-control: never
 680 End: