opcodes/ChangeLog

   1 2020-11-14  Borislav Petkov  <bp@suse.de>
   2
   3         * i386-dis.c (ckprefix): Do not assign active_seg_prefix in
   4         64-bit addressing mode.
   5         (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of
   6         active_seg_prefix.
   7
   8 2020-11-11  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   9
  10         * aarch64-tbl.h: Enable -march=armv8.6-a+ls64.
  11
  12 2020-11-09  Spencer E. Olson  <olsonse@umich.edu>
  13
  14         * pru-opc.c: Add opcode description for LMBD (left-most bit
  15         detect).
  16
  17 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  18
  19         * aarch64-opc.c: Add ACCDATA_EL1 system register
  20
  21 2020-11-09  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  22
  23         * aarch64-opc.c (aarch64_print_operand): Support operand AARCH64_OPND_Rt_LS64
  24         print.
  25         * aarch64-tbl.h (struct aarch64_opcode): Update _LS64_INSN instructions with
  26         Rt_ls64 operands.
  27         * aarch64-asm-2.c: Regenerated.
  28         * aarch64-dis-2.c: Regenerated.
  29         * aarch64-opc-2.c: Regenerated.
  30
  31 2020-11-06  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  32
  33         * aarch64-tbl.h (PAC): Handle for PAC feature.
  34         (PAC_INSN): New PAC instruction.
  35         (struct aarch64_opcode):  Move PAC instructions from V8_3_INSN to
  36         PAC_INSN.
  37
  38 2020-11-04  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  39
  40         * aarch64-opc.c: Add RAS 1.1 new system registers: ERXPFGCTL_EL1,
  41         ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and ERXPFGF_EL1.
  42
  43 2020-11-03  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  44
  45         * aarch64-tbl.h (QL_X2NIL): New qualifier for 64-byte stores.
  46         (LS64): Handler with +ls64 feature flags.
  47         (_LS64_INSN): New instruction group macro.
  48         (struct aarch64_opcode): Add LS64 instructions.
  49         * aarch64-asm-2.c: Regenerated.
  50         * aarch64-dis-2.c: Regenerated.
  51         * aarch64-opc-2.c: Regenerated.
  52
  53 2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  54
  55         * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
  56         * aarch64-asm-2.c: Regenerated.
  57         * aarch64-dis-2.c: Regenerated.
  58         * aarch64-opc-2.c: Regenerated.
  59
  60 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  61
  62         * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
  63         * aarch64-tbl.h (CSRE): New CSRE feature handler.
  64         (_CSRE_INSN): New CSRE instruction type.
  65         (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
  66         * aarch64-asm-2.c: Regenerated.
  67         * aarch64-dis-2.c: Regenerated.
  68         * aarch64-opc-2.c: Regenerated.
  69
  70 2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  71
  72         * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
  73         and operand description.
  74         * aarch64-asm-2.c: Regenerated.
  75         * aarch64-dis-2.c: Regenerated.
  76         * aarch64-opc-2.c: Regenerated.
  77
  78 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
  79
  80         * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
  81
  82 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
  83
  84         * csky-dis.c (csky_output_operand): Add handler for
  85         OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
  86         * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
  87         (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
  88         some instructions for VDSPV1.
  89
  90 2020-10-26  Lili Cui  <lili.cui@intel.com>
  91
  92         * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
  93
  94 2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  95
  96         * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
  97         * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
  98         ins_barrier_dsb_nx.
  99         * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
 100         * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
 101         ext_barrier_dsb_nx.
 102         * aarch64-opc.c (aarch64_print_operand): New options table
 103         aarch64_barrier_dsb_nxs_options.
 104         * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
 105         * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
 106         Armv8.7-a instruction.
 107         * aarch64-asm-2.c: Regenerated.
 108         * aarch64-dis-2.c: Regenerated.
 109         * aarch64-opc-2.c: Regenerated.
 110
 111 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 112
 113         * po/es.po: Remove the duplicated entry.
 114
 115 2020-10-20  Dr. David Alan Gilbert  <dgilbert@redhat.com>
 116
 117         * po/es.po: Fix printf format.
 118
 119 2020-10-20  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 120
 121         * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
 122         * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
 123         CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
 124         Add CPU_ZNVER3_FLAGS.
 125         (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 126         * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
 127         * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
 128         rmpupdate, rmpadjust.
 129         * i386-init.h: Re-generated.
 130         * i386-tbl.h: Re-generated.
 131
 132 2020-10-16  Lili Cui  <lili.cui@intel.com>
 133
 134         * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
 135         and move it from cpu_flags to opcode_modifiers.
 136         Use VexW0 and VexVVVV in the AVX-VNNI instructions.
 137         * i386-gen.c: Likewise.
 138         * i386-opc.h: Likewise.
 139         * i386-opc.h: Likewise.
 140         * i386-init.h: Regenerated.
 141         * i386-tbl.h: Likewise.
 142
 143 2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 144
 145         * aarch64-tbl.h (ARMV8_7): New macro.
 146
 147 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 148             Lili Cui  <lili.cui@intel.com>
 149
 150         * i386-dis.c (PREFIX_VEX_0F3850): New.
 151         (PREFIX_VEX_0F3851): Likewise.
 152         (PREFIX_VEX_0F3852): Likewise.
 153         (PREFIX_VEX_0F3853): Likewise.
 154         (VEX_W_0F3850_P_2): Likewise.
 155         (VEX_W_0F3851_P_2): Likewise.
 156         (VEX_W_0F3852_P_2): Likewise.
 157         (VEX_W_0F3853_P_2): Likewise.
 158         (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
 159         PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
 160         (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
 161         VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
 162         (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
 163         * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
 164         CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
 165         CPU_ANY_AVX_VNNI_FLAGS.
 166         (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
 167         * i386-opc.h (CpuAVX_VNNI): New.
 168         (CpuVEX_PREFIX): Likewise.
 169         (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
 170         * i386-opc.tbl: Add Intel AVX VNNI instructions.
 171         * i386-init.h: Regenerated.
 172         * i386-tbl.h: Likewise.
 173
 174 2020-10-14  Lili Cui  <lili.cui@intel.com>
 175             H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         * i386-dis.c (PREFIX_0F3A0F): New.
 178         (MOD_0F3A0F_PREFIX_1): Likewise.
 179         (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
 180         (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
 181         (prefix_table): Add PREFIX_0F3A0F.
 182         (mod_table): Add MOD_0F3A0F_PREFIX_1.
 183         (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
 184         (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
 185         * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
 186         CPU_ANY_HRESET_FLAGS.
 187         (cpu_flags): Add CpuHRESET.
 188         (output_i386_opcode): Allow 4 byte base_opcode.
 189         * i386-opc.h (enum): Add CpuHRESET.
 190         (i386_cpu_flags): Add cpuhreset.
 191         * i386-opc.tbl: Add Intel HRESET instruction.
 192         * i386-init.h: Regenerate.
 193         * i386-tbl.h: Likewise.
 194
 195 2020-10-14  Lili Cui  <lili.cui@intel.com>
 196
 197         * i386-dis.c (enum): Add
 198         PREFIX_MOD_3_0F01_REG_5_RM_4,
 199         PREFIX_MOD_3_0F01_REG_5_RM_5,
 200         PREFIX_MOD_3_0F01_REG_5_RM_6,
 201         PREFIX_MOD_3_0F01_REG_5_RM_7,
 202         X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
 203         X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
 204         X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
 205         X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
 206         X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
 207         (prefix_table): New instructions (see prefixes above).
 208         (rm_table): Likewise
 209         * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
 210         CPU_ANY_UINTR_FLAGS.
 211         (cpu_flags): Add CpuUINTR.
 212         * i386-opc.h (enum): Add CpuUINTR.
 213         (i386_cpu_flags): Add cpuuintr.
 214         * i386-opc.tbl: Add UINTR insns.
 215         * i386-init.h: Regenerate.
 216         * i386-tbl.h: Likewise.
 217
 218 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         * i386-gen.c (process_i386_opcode_modifier): Return 1 for
 221         non-VEX/EVEX/prefix encoding.
 222         (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
 223         has a prefix byte.
 224         * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
 225         base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
 226         * i386-tbl.h: Regenerated.
 227
 228 2020-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         * i386-gen.c (opcode_modifiers): Replace VexOpcode with
 231         OpcodePrefix.
 232         * i386-opc.h (VexOpcode): Renamed to ...
 233         (OpcodePrefix): This.
 234         (PREFIX_NONE): New.
 235         (PREFIX_0X66): Likewise.
 236         (PREFIX_0XF2): Likewise.
 237         (PREFIX_0XF3): Likewise.
 238         * i386-opc.tbl (Prefix_0X66): New.
 239         (Prefix_0XF2): Likewise.
 240         (Prefix_0XF3): Likewise.
 241         Replace VexOpcode= with OpcodePrefix=.  Use Prefix_0X66 on xorpd.
 242         Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
 243         * i386-tbl.h: Regenerated.
 244
 245 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 246
 247         * aarch64-opc.c: Add BRBE system registers.
 248
 249 2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 250
 251         * aarch64-opc.c: New CSRE system registers defined.
 252
 253 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 254
 255         * cgen-asm.c: Fix spelling mistakes.
 256         * cgen-dis.c: Fix spelling mistakes.
 257         * tic30-dis.c: Fix spelling mistakes.
 258
 259 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         PR binutils/26704
 262         * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
 263
 264 2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         PR binutils/26705
 267         * i386-dis.c (print_insn): Clear modrm if not needed.
 268         (putop): Check need_modrm for modrm.mod != 3.  Don't check
 269         need_modrm for modrm.mod == 3.
 270
 271 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 272
 273         * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
 274         TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
 275         TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
 276         TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
 277         TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
 278         TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
 279         TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
 280         TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
 281         WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
 282         TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
 283         TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
 284         TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
 285         TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
 286         TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
 287
 288 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 289
 290         * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
 291
 292 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 293
 294         * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
 295         TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
 296
 297 2020-09-26  Alan Modra  <amodra@gmail.com>
 298
 299         * csky-opc.h: Formatting.
 300         (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
 301         (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
 302         and shift 1u.
 303         (get_register_number): Likewise.
 304         * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
 305
 306 2020-09-24  Lili Cui  <lili.cui@intel.com>
 307
 308         PR 26654
 309         * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 310
 311 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 312
 313         * csky-dis.c (csky_output_operand): Enclose body of if in curly
 314         braces.
 315
 316 2020-09-24  Lili Cui  <lili.cui@intel.com>
 317
 318         * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
 319         PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
 320         X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
 321         X86_64_0F01_REG_1_RM_7_P_2.
 322         (prefix_table): Likewise.
 323         (x86_64_table): Likewise.
 324         (rm_table): Likewise.
 325         * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
 326         and CPU_ANY_TDX_FLAGS.
 327         (cpu_flags): Add CpuTDX.
 328         * i386-opc.h (enum): Add CpuTDX.
 329         (i386_cpu_flags): Add cputdx.
 330         * i386-opc.tbl: Add TDX insns.
 331         * i386-init.h: Regenerate.
 332         * i386-tbl.h: Likewise.
 333
 334 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 335
 336         * csky-dis.c (using_abi): New.
 337         (parse_csky_dis_options): New function.
 338         (get_gr_name): New function.
 339         (get_cr_name): New function.
 340         (csky_output_operand): Use get_gr_name and get_cr_name to
 341         disassemble and add handle of OPRND_TYPE_IMM5b_LS.
 342         (print_insn_csky): Parse disassembler options.
 343         * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
 344         (GENARAL_REG_BANK): Define.
 345         (REG_SUPPORT_ALL): Define.
 346         (REG_SUPPORT_ALL): New.
 347         (ASH): Define.
 348         (REG_SUPPORT_A): Define.
 349         (REG_SUPPORT_B): Define.
 350         (REG_SUPPORT_C): Define.
 351         (REG_SUPPORT_D): Define.
 352         (REG_SUPPORT_E): Define.
 353         (csky_abiv1_general_regs): New.
 354         (csky_abiv1_control_regs): New.
 355         (csky_abiv2_general_regs): New.
 356         (csky_abiv2_control_regs): New.
 357         (get_register_name): New function.
 358         (get_register_number): New function.
 359         (csky_get_general_reg_name): New function.
 360         (csky_get_general_regno): New function.
 361         (csky_get_control_reg_name): New function.
 362         (csky_get_control_regno): New function.
 363         (csky_v2_opcodes): Prefer two oprerans format for bclri and
 364         bseti, strengthen the operands legality check of addc, zext
 365         and sext.
 366
 367 2020-09-23  Lili Cui  <lili.cui@intel.com>
 368
 369         * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
 370         MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
 371         MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
 372         MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
 373         PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
 374         (reg_table): New instructions (see prefixes above).
 375         (prefix_table): Likewise.
 376         (three_byte_table): Likewise.
 377         (mod_table): Likewise
 378         * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
 379         CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
 380         (cpu_flags): Likewise.
 381         (operand_type_init): Likewise.
 382         * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
 383         (i386_cpu_flags): Add cpukl and cpuwide_kl.
 384         * i386-opc.tbl: Add KL and WIDE_KL insns.
 385         * i386-init.h: Regenerate.
 386         * i386-tbl.h: Likewise.
 387
 388 2020-09-21  Alan Modra  <amodra@gmail.com>
 389
 390         * rx-dis.c (flag_names): Add missing comma.
 391         (register_names, flag_names, double_register_names),
 392         (double_register_high_names, double_register_low_names),
 393         (double_control_register_names, double_condition_names): Remove
 394         trailing commas.
 395
 396 2020-09-18  David Faust  <david.faust@oracle.com>
 397
 398         * bpf-desc.c: Regenerate.
 399         * bpf-desc.h: Likewise.
 400         * bpf-opc.c: Likewise.
 401         * bpf-opc.h: Likewise.
 402
 403 2020-09-16  Andrew Burgess <andrew.burgess@embecosm.com>
 404
 405         * csky-dis.c (csky_get_disassembler): Don't return NULL when there
 406         is no BFD.
 407
 408 2020-09-16  Alan Modra  <amodra@gmail.com>
 409
 410         * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
 411
 412 2020-09-10  Nick Clifton  <nickc@redhat.com>
 413
 414         * ppc-dis.c (ppc_symbol_is_valid): New function.  Returns false
 415         for hidden, local, no-type symbols.
 416         (disassemble_init_powerpc): Point the symbol_is_valid field in the
 417         info structure at the new function.
 418
 419 2020-09-10  Cooper Qu  <cooper.qu@linux.alibaba.com>
 420
 421         * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
 422         * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
 423         opcode fixing.
 424
 425 2020-09-10  Nick Clifton  <nickc@redhat.com>
 426
 427         * csky-dis.c (csky_output_operand): Coerce the immediate values to
 428         long before printing.
 429
 430 2020-09-10  Alan Modra  <amodra@gmail.com>
 431
 432         * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
 433
 434 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 435
 436         * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
 437         ISA flag.
 438
 439 2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
 440
 441         * csky-dis.c (csky_output_operand): Add handlers for
 442         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 443         OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
 444         to support FPUV3 instructions.
 445         * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
 446         OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
 447         OPRND_TYPE_DFLOAT_FMOVI.
 448         (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
 449          OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
 450          OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
 451          OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
 452          OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
 453          OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
 454          OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
 455          OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
 456          OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
 457          OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
 458          OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
 459          OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
 460          OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
 461         (csky_v2_opcodes): Add FPUV3 instructions.
 462
 463 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 464
 465         * aarch64-dis.c (print_operands): Pass CPU features to
 466         aarch64_print_operand().
 467         * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
 468         preferred disassembly of system registers.
 469         (SR_RNG): Refactor to use new SR_FEAT2 macro.
 470         (SR_FEAT2): New.
 471         (SR_V8_1_A): New.
 472         (SR_V8_4_A): New.
 473         (SR_V8_A): New.
 474         (SR_V8_R): New.
 475         (SR_EXPAND_ELx): New.
 476         (SR_EXPAND_EL12): New.
 477         (aarch64_sys_regs): Specify which registers are only on
 478         A-profile, add R-profile system registers.
 479         (ENC_BARLAR): New.
 480         (PRBARn_ELx): New.
 481         (PRLARn_ELx): New.
 482         (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
 483         Armv8-R AArch64.
 484
 485 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 486
 487         * aarch64-tbl.h (aarch64_feature_v8_r): New.
 488         (ARMV8_R): New.
 489         (V8_R_INSN): New.
 490         (aarch64_opcode_table): Add dfb.
 491         * aarch64-opc-2.c: Regenerate.
 492         * aarch64-asm-2.c: Regenerate.
 493         * aarch64-dis-2.c: Regenerate.
 494
 495 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 496
 497         * aarch64-dis.c (arch_variant): New.
 498         (determine_disassembling_preference): Disassemble according to
 499         arch variant.
 500         (select_aarch64_variant): New.
 501         (print_insn_aarch64): Set feature set.
 502
 503 2020-09-02  Alan Modra  <amodra@gmail.com>
 504
 505         * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
 506         (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
 507         (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
 508         (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
 509         (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
 510         (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
 511         (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
 512         for value parameter and update code to suit.
 513         (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
 514         (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
 515
 516 2020-09-02  Alan Modra  <amodra@gmail.com>
 517
 518         * i386-dis.c (OP_E_memory): Don't cast to signed type when
 519         negating.
 520         (get32, get32s): Use unsigned types in shift expressions.
 521
 522 2020-09-02  Alan Modra  <amodra@gmail.com>
 523
 524         * csky-dis.c (print_insn_csky): Use unsigned type for "given".
 525
 526 2020-09-02  Alan Modra  <amodra@gmail.com>
 527
 528         * crx-dis.c: Whitespace.
 529         (print_arg): Use unsigned type for longdisp and mask variables,
 530         and for left shift constant.
 531
 532 2020-09-02  Alan Modra  <amodra@gmail.com>
 533
 534         * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
 535         * bpf-ibld.c: Regenerate.
 536         * epiphany-ibld.c: Regenerate.
 537         * fr30-ibld.c: Regenerate.
 538         * frv-ibld.c: Regenerate.
 539         * ip2k-ibld.c: Regenerate.
 540         * iq2000-ibld.c: Regenerate.
 541         * lm32-ibld.c: Regenerate.
 542         * m32c-ibld.c: Regenerate.
 543         * m32r-ibld.c: Regenerate.
 544         * mep-ibld.c: Regenerate.
 545         * mt-ibld.c: Regenerate.
 546         * or1k-ibld.c: Regenerate.
 547         * xc16x-ibld.c: Regenerate.
 548         * xstormy16-ibld.c: Regenerate.
 549
 550 2020-09-02  Alan Modra  <amodra@gmail.com>
 551
 552         * bfin-dis.c (MASKBITS): Use SIGNBIT.
 553
 554 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 555
 556         * csky-opc.h (csky_v2_opcodes): Move divul and divsl
 557         to CSKYV2_ISA_3E3R3 instruction set.
 558
 559 2020-09-02  Cooper Qu  <cooper.qu@linux.alibaba.com>
 560
 561         * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
 562
 563 2020-09-01  Alan Modra  <amodra@gmail.com>
 564
 565         * mep-ibld.c: Regenerate.
 566
 567 2020-08-31  Cooper Qu  <cooper.qu@linux.alibaba.com>
 568
 569         * csky-dis.c (csky_output_operand): Assign dis_info.value for
 570         OPRND_TYPE_VREG.
 571
 572 2020-08-30  Alan Modra  <amodra@gmail.com>
 573
 574         * cr16-dis.c: Formatting.
 575         (parameter): Delete struct typedef.  Use dwordU instead
 576         throughout file.
 577         (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
 578         and tbitb.
 579         (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
 580
 581 2020-08-29  Alan Modra  <amodra@gmail.com>
 582
 583         PR 26446
 584         * csky-opc.h (MAX_OPRND_NUM): Define to 5.
 585         (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
 586
 587 2020-08-28  Alan Modra  <amodra@gmail.com>
 588
 589         PR 26449
 590         PR 26450
 591         * cgen-ibld.in (insert_1): Use 1UL in forming mask.
 592         (extract_normal): Likewise.
 593         (insert_normal): Likewise, and move past zero length test.
 594         (put_insn_int_value): Handle mask for zero length, use 1UL.
 595         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 596         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 597         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 598         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 599
 600 2020-08-28  Cooper Qu  <cooper.qu@linux.alibaba.com>
 601
 602         * csky-dis.c (CSKY_DEFAULT_ISA): Define.
 603         (csky_dis_info): Add member isa.
 604         (csky_find_inst_info): Skip instructions that do not belong to
 605         current CPU.
 606         (csky_get_disassembler): Get infomation from attribute section.
 607         (print_insn_csky): Set defualt ISA flag.
 608         * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
 609         * csky-opc.h (struct csky_opcode): Change isa_flag16 and
 610         isa_flag32'type to unsigned 64 bits.
 611
 612 2020-08-26  Jose E. Marchesi  <jemarch@gnu.org>
 613
 614         * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
 615
 616 2020-08-26  David Faust  <david.faust@oracle.com>
 617
 618         * bpf-desc.c: Regenerate.
 619         * bpf-desc.h: Likewise.
 620         * bpf-opc.c: Likewise.
 621         * bpf-opc.h: Likewise.
 622         * disassemble.c (disassemble_init_for_target): Set bits for xBPF
 623         ISA when appropriate.
 624
 625 2020-08-25  Alan Modra  <amodra@gmail.com>
 626
 627         PR 26504
 628         * vax-dis.c (parse_disassembler_options): Always add at least one
 629         to entry_addr_total_slots.
 630
 631 2020-08-24  Cooper Qu  <cooper.qu@linux.alibaba.com>
 632
 633         * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
 634         in other CPUs to speed up disassembling.
 635         * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
 636         Change plsli.u16 to plsli.16, change sync's operand format.
 637
 638 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 639
 640         * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
 641
 642 2020-08-21  Nick Clifton  <nickc@redhat.com>
 643
 644         * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
 645         symbols.
 646
 647 2020-08-21  Cooper Qu  <cooper.qu@linux.alibaba.com>
 648
 649         * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
 650
 651 2020-08-19  Alan Modra  <amodra@gmail.com>
 652
 653         * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
 654         vcmpuq and xvtlsbb.
 655
 656 2020-08-18  Peter Bergner  <bergner@linux.ibm.com>
 657
 658         * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
 659         <xvcvbf16spn>: ...to this.
 660
 661 2020-08-12  Alex Coplan  <alex.coplan@arm.com>
 662
 663         * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
 664
 665 2020-08-12  Nick Clifton  <nickc@redhat.com>
 666
 667         * po/sr.po: Updated Serbian translation.
 668
 669 2020-08-11  Alan Modra  <amodra@gmail.com>
 670
 671         * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
 672
 673 2020-08-10  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 674
 675         * aarch64-opc.c (aarch64_print_operand):
 676         (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
 677         (aarch64_sys_reg_supported_p): Function removed.
 678         (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
 679         (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
 680         into this function.
 681
 682 2020-08-10  Alan Modra  <amodra@gmail.com>
 683
 684         * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
 685         instructions.
 686
 687 2020-08-10  Alan Modra  <amodra@gmail.com>
 688
 689         * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
 690         Enable icbt for power5, miso for power8.
 691
 692 2020-08-10  Alan Modra  <amodra@gmail.com>
 693
 694         * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
 695         mtvsrd, and similarly for mfvsrd.
 696
 697 2020-08-04  Christian Groessler  <chris@groessler.org>
 698             Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
 699
 700         * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
 701         opcodes (special "out" to absolute address).
 702         * z8k-opc.h: Regenerate.
 703
 704 2020-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 705
 706         PR gas/26305
 707         * i386-opc.h (Prefix_Disp8): New.
 708         (Prefix_Disp16): Likewise.
 709         (Prefix_Disp32): Likewise.
 710         (Prefix_Load): Likewise.
 711         (Prefix_Store): Likewise.
 712         (Prefix_VEX): Likewise.
 713         (Prefix_VEX3): Likewise.
 714         (Prefix_EVEX): Likewise.
 715         (Prefix_REX): Likewise.
 716         (Prefix_NoOptimize): Likewise.
 717         * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes.  Add {disp16}.
 718         * i386-tbl.h: Regenerated.
 719
 720 2020-07-29  Andreas Arnez  <arnez@linux.ibm.com>
 721
 722         * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
 723         default case with abort() instead of printing an error message and
 724         continuing, to avoid a maybe-uninitialized warning.
 725
 726 2020-07-24  Nick Clifton  <nickc@redhat.com>
 727
 728         * po/de.po: Updated German translation.
 729
 730 2020-07-21  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-dis.c (OP_E_memory): Revert previous change.
 733
 734 2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         PR gas/26237
 737         * i386-dis.c (OP_E_memory): Don't display eiz with no scale
 738         without base nor index registers.
 739
 740 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-dis.c (putop): Move 'V' and 'W' handling.
 743
 744 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-dis.c (dis386): Adjust 'V' description. Use P-based
 747         construct for push/pop of register.
 748         (putop): Honor cond when handling 'P'. Drop handling of plain
 749         'V'.
 750
 751 2020-07-15  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
 754         description. Drop '&' description. Use P for push of immediate,
 755         pushf/popf, enter, and leave. Use %LP for lret/retf.
 756         (dis386_twobyte): Use P for push/pop of fs/gs.
 757         (reg_table): Use P for push/pop. Use @ for near call/jmp.
 758         (x86_64_table): Use P for far call/jmp.
 759         (putop): Drop handling of 'U' and '&'. Move and adjust handling
 760         of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
 761         labels.
 762         (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
 763         and dqw_mode (unconditional).
 764
 765 2020-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         PR gas/26237
 768         * i386-dis.c (OP_E_memory): Without base nor index registers,
 769         32-bit displacement to 64 bits.
 770
 771 2020-07-14  Claudiu Zissulescu  <claziss@gmail.com>
 772
 773         * arc-dis.c (print_insn_arc): Detect and emit a warning when a
 774         faulty double register pair is detected.
 775
 776 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
 779
 780 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-dis.c (OP_R, Rm): Delete.
 783         (MOD_0F24, MOD_0F26): Rename to ...
 784         (X86_64_0F24, X86_64_0F26): ... respectively.
 785         (dis386): Update 'L' and 'Z' comments.
 786         (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
 787         table references.
 788         (mod_table): Move opcode 0F24 and 0F26 entries ...
 789         (x86_64_table): ... here.
 790         (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
 791         'Z' case block.
 792
 793 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-dis.c (Rd, Rdq, MaskR): Delete.
 796         (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
 797         MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
 798         MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
 799         MOD_EVEX_0F387C): New enumerators.
 800         (reg_table): Use Edq for rdssp.
 801         (prefix_table): Use Edq for incssp.
 802         (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
 803         kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
 804         ktest*, and kshift*. Use Edq / MaskE for kmov*.
 805         * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
 806         * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
 807         0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
 808         * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
 809         0F3828_P_1 and 0F3838_P_1.
 810         * i386-dis-evex-w.h: Reference mod_table[] for opcodes
 811         0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
 812
 813 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
 816         PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
 817         PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
 818         PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
 819         PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
 820         PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
 821         (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
 822         VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
 823         VEX_LEN_0F38F3_R_3_P_0): Rename to ...
 824         (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
 825         VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
 826         (reg_table, prefix_table, three_byte_table, vex_table,
 827         vex_len_table, mod_table, rm_table): Replace / remove respective
 828         entries.
 829         (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
 830         of PREFIX_DATA in used_prefixes.
 831
 832 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
 835         MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
 836         MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
 837         MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
 838         (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
 839         MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
 840         (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
 841         VEX_W_0F3A33_L_0): Delete.
 842         (dis386): Adjust "BW" description.
 843         (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
 844         0F3A31, 0F3A32, and 0F3A33.
 845         (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 846         entries.
 847         (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
 848         entries.
 849
 850 2020-07-14  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
 853         PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
 854         PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
 855         PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
 856         PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
 857         PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
 858         PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
 859         PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
 860         PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
 861         PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
 862         PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
 863         PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
 864         PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
 865         PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
 866         PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
 867         PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
 868         PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
 869         PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
 870         PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
 871         PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
 872         PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
 873         PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
 874         PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
 875         PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
 876         PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
 877         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 878         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 879         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
 880         PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
 881         PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 882         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 883         PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
 884         PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
 885         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 886         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 887         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 888         PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
 889         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 890         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 891         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
 892         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 893         PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
 894         PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
 895         PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
 896         PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
 897         PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
 898         PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
 899         PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
 900         PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
 901         PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
 902         PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
 903         PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
 904         PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
 905         PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
 906         PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
 907         PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
 908         PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
 909         PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 910         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 911         PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
 912         PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
 913         PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
 914         PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
 915         PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
 916         PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
 917         PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
 918         PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
 919         PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
 920         PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
 921         PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
 922         PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
 923         PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
 924         PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
 925         PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
 926         PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
 927         PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
 928         PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
 929         PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
 930         PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
 931         PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
 932         PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
 933         PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
 934         PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
 935         PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
 936         PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
 937         PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
 938         PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
 939         PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
 940         PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
 941         PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
 942         PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
 943         PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
 944         PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
 945         PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
 946         PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
 947         PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
 948         PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
 949         PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
 950         PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
 951         PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
 952         PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
 953         PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
 954         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
 955         PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
 956         PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
 957         PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
 958         PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
 959         PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
 960         PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
 961         PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
 962         PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 963         PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
 964         PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
 965         PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
 966         PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
 967         PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
 968         PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
 969         PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
 970         PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
 971         PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
 972         PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
 973         PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
 974         PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
 975         PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
 976         PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
 977         PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
 978         PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
 979         PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
 980         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
 981         PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
 982         PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
 983         PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
 984         PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
 985         PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
 986         PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
 987         PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
 988         PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
 989         PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
 990         PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
 991         PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
 992         PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
 993         PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
 994         PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
 995         PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
 996         PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
 997         PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
 998         PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
 999         PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
1000         PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
1001         PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
1002         PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
1003         PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
1004         PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
1005         PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
1006         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
1007         PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
1008         PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
1009         (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
1010         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
1011         MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
1012         MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
1013         MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
1014         MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
1015         MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
1016         MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
1017         MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
1018         MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
1019         MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
1020         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1021         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1022         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
1023         MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
1024         VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
1025         VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
1026         VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
1027         VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
1028         VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
1029         VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
1030         VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
1031         VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
1032         VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
1033         VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
1034         VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
1035         VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
1036         VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
1037         EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
1038         EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
1039         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
1040         EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
1041         EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
1042         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1043         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
1044         EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1045         EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1046         EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
1047         EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
1048         EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
1049         EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
1050         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
1051         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1052         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
1053         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1054         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1055         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1056         EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
1057         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
1058         EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
1059         EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
1060         EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
1061         EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
1062         EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
1063         EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
1064         VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
1065         VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
1066         VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
1067         VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
1068         VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
1069         VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
1070         VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
1071         VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
1072         VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
1073         VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
1074         VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
1075         VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
1076         VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
1077         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
1078         VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
1079         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
1080         VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
1081         VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
1082         EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
1083         EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
1084         EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
1085         EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
1086         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
1087         EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
1088         EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
1089         EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
1090         EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
1091         EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
1092         EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
1093         EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
1094         EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
1095         EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
1096         EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
1097         EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
1098         EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
1099         EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
1100         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
1101         EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
1102         EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
1103         EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1104         EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
1105         EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
1106         EVEX_W_0F3A72_P_2): Rename to ...
1107         (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
1108         MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
1109         MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1110         MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1111         MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1112         MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1113         MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1114         MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1115         MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1116         MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1117         MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1118         VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1119         VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1120         VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1121         VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1122         VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1123         VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1124         VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1125         VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1126         VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1127         EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1128         EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1129         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1130         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1131         EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1132         EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1133         EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1134         EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1135         EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1136         EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1137         EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1138         EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1139         EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1140         EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1141         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1142         EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1143         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1144         EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1145         EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1146         EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1147         EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1148         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1149         EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1150         EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1151         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1152         VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1153         VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1154         VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1155         VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1156         VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1157         VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1158         VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1159         VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1160         VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1161         VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1162         VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1163         VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1164         VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1165         EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1166         EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1167         EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1168         EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1169         EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1170         EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1171         EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1172         EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1173         EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1174         EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1175         EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1176         EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1177         EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1178         EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1179         respectively.
1180         (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1181         vex_w_table, mod_table): Replace / remove respective entries.
1182         (print_insn): Move up dp->prefix_requirement handling. Handle
1183         PREFIX_DATA.
1184         * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1185         i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1186         Replace / remove respective entries.
1187
1188 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1189
1190         * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1191         PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1192         (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1193         vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1194         Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1195         the latter two.
1196         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1197         0F2C, 0F2D, 0F2E, and 0F2F.
1198         * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1199         0F2F table entries.
1200
1201 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1202
1203         * i386-dis.c (OP_VexR, VexScalarR): New.
1204         (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1205         XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1206         need_vex_reg): Delete.
1207         (prefix_table): Replace VexScalar by VexScalarR and
1208         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1209         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1210         (vex_len_table): Replace EXqVexScalarS by EXqS.
1211         (get_valid_dis386): Don't set need_vex_reg.
1212         (print_insn): Don't initialize need_vex_reg.
1213         (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1214         q_scalar_swap_mode cases.
1215         (OP_EX): Don't check for d_scalar_swap_mode and
1216         q_scalar_swap_mode.
1217         (OP_VEX): Done check need_vex_reg.
1218         * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1219         XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1220         EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1221
1222 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1223
1224         * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1225         (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1226         VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1227         VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1228         (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1229         VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1230         VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1231         VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1232         (vex_table): Replace Vex128 by Vex.
1233         (vex_len_table): Likewise. Adjust referenced enum names.
1234         (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1235         referenced enum names.
1236         (OP_VEX): Drop vex128_mode and vex256_mode cases.
1237         * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1238
1239 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1240
1241         * i386-dis.c (dis386): "LW" description now applies to "DQ".
1242         (putop): Handle "DQ". Don't handle "LW" anymore.
1243         (prefix_table, mod_table): Replace %LW by %DQ.
1244         * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1245
1246 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1247
1248         * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1249         dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1250         d_scalar_swap_mode case handling. Move shift adjsutment into
1251         the case its applicable to.
1252
1253 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1254
1255         * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1256         (EXbScalar, EXwScalar): Fold to ...
1257         (EXbwUnit): ... this.
1258         (b_scalar_mode, w_scalar_mode): Fold to ...
1259         (bw_unit_mode): ... this.
1260         (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1261         w_scalar_mode handling by bw_unit_mode one.
1262         * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1263         ...
1264         * i386-dis-evex-prefix.h: ... here.
1265
1266 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-dis.c (PCMPESTR_Fixup): Delete.
1269         (dis386): Adjust "LQ" description.
1270         (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1271         cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1272         PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1273         vpcmpestrm, and vpcmpestri.
1274         (putop): Honor "cond" when handling LQ.
1275         * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1276         vcvtsi2ss and vcvtusi2ss.
1277         * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1278         vcvtsi2sd and vcvtusi2sd.
1279
1280 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1281
1282         * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1283         (simd_cmp_op): Add const.
1284         (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1285         (CMP_Fixup): Handle VEX case.
1286         (prefix_table): Replace VCMP by CMP.
1287         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1288
1289 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1290
1291         * i386-dis.c (MOVBE_Fixup): Delete.
1292         (Mv): Define.
1293         (prefix_table): Use Mv for movbe entries.
1294
1295 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1296
1297         * i386-dis.c (CRC32_Fixup): Delete.
1298         (prefix_table): Use Eb/Ev for crc32 entries.
1299
1300 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1301
1302         * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1303         Conditionalize invocations of "USED_REX (0)".
1304
1305 2020-07-14  Jan Beulich  <jbeulich@suse.com>
1306
1307         * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1308         CH, DH, BH, AX, DX): Delete.
1309         (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1310         eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1311         dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1312
1313 2020-07-10  Lili Cui  <lili.cui@intel.com>
1314
1315         * i386-dis.c (TMM): New.
1316         (EXtmm): Likewise.
1317         (VexTmm): Likewise.
1318         (MVexSIBMEM): Likewise.
1319         (tmm_mode): Likewise.
1320         (vex_sibmem_mode): Likewise.
1321         (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1322         (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1323         (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1324         (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1325         (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1326         (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1327         (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1328         (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1329         (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1330         (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1331         (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1332         (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1333         (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1334         (PREFIX_VEX_0F3849_X86_64): Likewise.
1335         (PREFIX_VEX_0F384B_X86_64): Likewise.
1336         (PREFIX_VEX_0F385C_X86_64): Likewise.
1337         (PREFIX_VEX_0F385E_X86_64): Likewise.
1338         (X86_64_VEX_0F3849): Likewise.
1339         (X86_64_VEX_0F384B): Likewise.
1340         (X86_64_VEX_0F385C): Likewise.
1341         (X86_64_VEX_0F385E): Likewise.
1342         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1343         (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1344         (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1345         (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1346         (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1347         (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1348         (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1349         (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1350         (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1351         (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1352         (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1353         (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1354         (VEX_W_0F3849_X86_64_P_0): Likewise.
1355         (VEX_W_0F3849_X86_64_P_2): Likewise.
1356         (VEX_W_0F3849_X86_64_P_3): Likewise.
1357         (VEX_W_0F384B_X86_64_P_1): Likewise.
1358         (VEX_W_0F384B_X86_64_P_2): Likewise.
1359         (VEX_W_0F384B_X86_64_P_3): Likewise.
1360         (VEX_W_0F385C_X86_64_P_1): Likewise.
1361         (VEX_W_0F385E_X86_64_P_0): Likewise.
1362         (VEX_W_0F385E_X86_64_P_1): Likewise.
1363         (VEX_W_0F385E_X86_64_P_2): Likewise.
1364         (VEX_W_0F385E_X86_64_P_3): Likewise.
1365         (names_tmm): Likewise.
1366         (att_names_tmm): Likewise.
1367         (intel_operand_size): Handle void_mode.
1368         (OP_XMM): Handle tmm_mode.
1369         (OP_EX): Likewise.
1370         (OP_VEX): Likewise.
1371         * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1372         CpuAMX_BF16 and CpuAMX_TILE.
1373         (operand_type_shorthands): Add RegTMM.
1374         (operand_type_init): Likewise.
1375         (operand_types): Add Tmmword.
1376         (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1377         (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1378         * i386-opc.h (CpuAMX_INT8): New.
1379         (CpuAMX_BF16): Likewise.
1380         (CpuAMX_TILE): Likewise.
1381         (SIBMEM): Likewise.
1382         (Tmmword): Likewise.
1383         (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1384         (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1385         (i386_operand_type): Add tmmword.
1386         * i386-opc.tbl: Add AMX instructions.
1387         * i386-reg.tbl: Add AMX registers.
1388         * i386-init.h: Regenerated.
1389         * i386-tbl.h: Likewise.
1390
1391 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1392
1393         * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1394         (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1395         Rename to ...
1396         (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1397         REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1398         respectively.
1399         (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1400         VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1401         VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1402         VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1403         VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1404         VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1405         VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1406         VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1407         VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1408         VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1409         VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1410         VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1411         VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1412         VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1413         VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1414         VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1415         VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1416         VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1417         VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1418         VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1419         VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1420         VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1421         VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1422         VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1423         VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1424         VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1425         VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1426         VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1427         VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1428         VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1429         VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1430         VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1431         VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1432         VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1433         VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1434         VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1435         (reg_table): Re-order XOP entries. Adjust their operands.
1436         (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1437         08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1438         08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1439         09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1440         09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1441         09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1442         entries by references ...
1443         (vex_len_table): ... to resepctive new entries here. For several
1444         new and existing entries reference ...
1445         (vex_w_table): ... new entries here.
1446         (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1447
1448 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1449
1450         * i386-dis.c (XMVexScalarI4): Define.
1451         (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1452         VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1453         VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1454         (vex_len_table): Move scalar FMA4 entries ...
1455         (prefix_table): ... here.
1456         (OP_REG_VexI4): Handle scalar_mode.
1457         * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1458         * i386-tbl.h: Re-generate.
1459
1460 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1461
1462         * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1463         Vex_2src_2): Delete.
1464         (OP_VexW, VexW): New.
1465         (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1466         for shifts and rotates by register.
1467
1468 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1469
1470         * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1471         VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1472         OP_EX_VexReg): Delete.
1473         (OP_VexI4, VexI4): New.
1474         (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1475         (prefix_table): ... here.
1476         (print_insn): Drop setting of vex_w_done.
1477
1478 2020-07-08  Jan Beulich  <jbeulich@suse.com>
1479
1480         * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1481         (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1482         (xop_table): Replace operands of 4-operand insns.
1483         (OP_REG_VexI4): Move VEX.W based operand swaping here.
1484
1485 2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
1486
1487         * arc-opc.c (insert_rbd): New function.
1488         (RBD): Define.
1489         (RBDdup): Likewise.
1490         * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1491         instructions.
1492
1493 2020-07-07  Jan Beulich  <jbeulich@suse.com>
1494
1495         * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1496         EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1497         EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1498         EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1499         Delete.
1500         (putop): Handle "BW".
1501         * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1502         0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1503         and 0F3A3F ...
1504         * i386-dis-evex-prefix.h: ... here.
1505
1506 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1507
1508         * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1509         (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1510         VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1511         VEX_W_0FXOP_09_83): New enumerators.
1512         (xop_table): Reference the above.
1513         (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1514         (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1515         VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1516         (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1517
1518 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1519
1520         * i386-dis.c (EVEX_W_0F3838_P_1,
1521         EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1522         EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1523         EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1524         EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1525         EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1526         (putop): Centralize management of last[]. Delete SAVE_LAST.
1527         * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1528         0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1529         0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1530         * i386-dis-evex-prefix.h: here.
1531
1532 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1533
1534         * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1535         MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1536         MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1537         MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1538         enumerators.
1539         (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1540         EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1541         EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1542         EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1543         (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1544         EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1545         EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1546         EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1547         these, respectively.
1548         * i386-dis-evex-len.h: Adjust comments.
1549         * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1550         MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1551         MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1552         MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1553         MOD_EVEX_0F385B_P_2_W_1 table entries.
1554         * i386-dis-evex-w.h: Reference mod_table[] for
1555         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1556         EVEX_W_0F385B_P_2.
1557
1558 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1559
1560         * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1561         vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1562         EXymm.
1563         (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1564         Likewise. Mark 256-bit entries invalid.
1565
1566 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1567
1568         * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1569         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1570         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1571         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1572         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1573         PREFIX_EVEX_0F382B): Delete.
1574         (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1575         EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1576         EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1577         EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1578         EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1579         to ...
1580         (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1581         EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1582         EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1583         EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1584         respectively.
1585         * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1586         for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1587         0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1588         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1589         PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1590         PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1591         PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1592         PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1593         PREFIX_EVEX_0F382B): Remove table entries.
1594         * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1595         0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1596         0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1597
1598 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1599
1600         * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1601         EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1602         enumerators.
1603         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1604         EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1605         EVEX_LEN_0F3A01_P_2_W_1 table entries.
1606         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1607         entries.
1608
1609 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1610
1611         * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1612         EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1613         EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1614         EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1615         * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1616         EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1617         EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1618         EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1619         * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1620         entries.
1621
1622 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1623
1624         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1625         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1626         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1627         respectively.
1628         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1629         entries.
1630         * i386-dis-evex.h (evex_table): Reference VEX table entry for
1631         opcode 0F3A1D.
1632         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1633         entry.
1634         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1635
1636 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1637
1638         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1639         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1640         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1641         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1642         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1643         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1644         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1645         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1646         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1647         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1648         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1649         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1650         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1651         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1652         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1653         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1654         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1655         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1656         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1657         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1658         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1659         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1660         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1661         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1662         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1663         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1664         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1665         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1666         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1667         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1668         (prefix_table): Add EXxEVexR to FMA table entries.
1669         (OP_Rounding): Move abort() invocation.
1670         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1671         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1672         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1673         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1674         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1675         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1676         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1677         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1678         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1679         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1680         0F3ACE, 0F3ACF.
1681         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1682         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1683         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1684         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1685         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1686         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1687         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1688         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1689         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1690         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1691         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1692         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1693         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1694         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1695         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1696         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1697         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1698         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1699         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1700         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1701         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1702         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1703         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1704         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1705         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1706         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1707         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1708         Delete table entries.
1709         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1710         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1711         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1712         Likewise.
1713
1714 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1715
1716         * i386-dis.c (EXqScalarS): Delete.
1717         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1718         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1719
1720 2020-07-06  Jan Beulich  <jbeulich@suse.com>
1721
1722         * i386-dis.c (safe-ctype.h): Include.
1723         (EXdScalar, EXqScalar): Delete.
1724         (d_scalar_mode, q_scalar_mode): Delete.
1725         (prefix_table, vex_len_table): Use EXxmm_md in place of
1726         EXdScalar and EXxmm_mq in place of EXqScalar.
1727         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1728         d_scalar_mode and q_scalar_mode.
1729         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1730         (vmovsd): Use EXxmm_mq.
1731
1732 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
1733
1734         PR 26204
1735         * arc-dis.c: Fix spelling mistake.
1736         * po/opcodes.pot: Regenerate.
1737
1738 2020-07-06  Nick Clifton  <nickc@redhat.com>
1739
1740         * po/pt_BR.po: Updated Brazilian Portugugese translation.
1741         * po/uk.po: Updated Ukranian translation.
1742
1743 2020-07-04  Nick Clifton  <nickc@redhat.com>
1744
1745         * configure: Regenerate.
1746         * po/opcodes.pot: Regenerate.
1747
1748 2020-07-04  Nick Clifton  <nickc@redhat.com>
1749
1750         Binutils 2.35 branch created.
1751
1752 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
1753
1754         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1755         * i386-opc.h (VexSwapSources): New.
1756         (i386_opcode_modifier): Add vexswapsources.
1757         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1758         with two source operands swapped.
1759         * i386-tbl.h: Regenerated.
1760
1761 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
1762
1763         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
1764         unprivileged CSR can also be initialized.
1765
1766 2020-06-29  Alan Modra  <amodra@gmail.com>
1767
1768         * arm-dis.c: Use C style comments.
1769         * cr16-opc.c: Likewise.
1770         * ft32-dis.c: Likewise.
1771         * moxie-opc.c: Likewise.
1772         * tic54x-dis.c: Likewise.
1773         * s12z-opc.c: Remove useless comment.
1774         * xgate-dis.c: Likewise.
1775
1776 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1777
1778         * i386-opc.tbl: Add a blank line.
1779
1780 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
1781
1782         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1783         (VecSIB128): Renamed to ...
1784         (VECSIB128): This.
1785         (VecSIB256): Renamed to ...
1786         (VECSIB256): This.
1787         (VecSIB512): Renamed to ...
1788         (VECSIB512): This.
1789         (VecSIB): Renamed to ...
1790         (SIB): This.
1791         (i386_opcode_modifier): Replace vecsib with sib.
1792         * i386-opc.tbl (VecSIB128): New.
1793         (VecSIB256): Likewise.
1794         (VecSIB512): Likewise.
1795         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1796         and VecSIB512, respectively.
1797
1798 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1799
1800         * i386-dis.c: Adjust description of I macro.
1801         (x86_64_table): Drop use of I.
1802         (float_mem): Replace use of I.
1803         (putop): Remove handling of I. Adjust setting/clearing of "alt".
1804
1805 2020-06-26  Jan Beulich  <jbeulich@suse.com>
1806
1807         * i386-dis.c: (print_insn): Avoid straight assignment to
1808         priv.orig_sizeflag when processing -M sub-options.
1809
1810 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1811
1812         * i386-dis.c: Adjust description of J macro.
1813         (dis386, x86_64_table, mod_table): Replace J.
1814         (putop): Remove handling of J.
1815
1816 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1817
1818         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1819
1820 2020-06-25  Jan Beulich  <jbeulich@suse.com>
1821
1822         * i386-dis.c: Adjust description of "LQ" macro.
1823         (dis386_twobyte): Use LQ for sysret.
1824         (putop): Adjust handling of LQ.
1825
1826 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
1827
1828         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1829         * riscv-dis.c: Include elfxx-riscv.h.
1830
1831 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
1832
1833         * i386-dis.c (prefix_table): Revert the last vmgexit change.
1834
1835 2020-06-17  Lili Cui  <lili.cui@intel.com>
1836
1837         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1838
1839 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
1840
1841         PR gas/26115
1842         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1843         * i386-opc.tbl: Likewise.
1844         * i386-tbl.h: Regenerated.
1845
1846 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
1847
1848         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1849
1850 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
1851
1852         * aarch64-opc.c (SYSREG): New macro for describing system registers.
1853         (SR_CORE): Likewise.
1854         (SR_FEAT): Likewise.
1855         (SR_RNG): Likewise.
1856         (SR_V8_1): Likewise.
1857         (SR_V8_2): Likewise.
1858         (SR_V8_3): Likewise.
1859         (SR_V8_4): Likewise.
1860         (SR_PAN): Likewise.
1861         (SR_RAS): Likewise.
1862         (SR_SSBS): Likewise.
1863         (SR_SVE): Likewise.
1864         (SR_ID_PFR2): Likewise.
1865         (SR_PROFILE): Likewise.
1866         (SR_MEMTAG): Likewise.
1867         (SR_SCXTNUM): Likewise.
1868         (aarch64_sys_regs): Refactor to store feature information in the table.
1869         (aarch64_sys_reg_supported_p): Collapse logic for system registers
1870         that now describe their own features.
1871         (aarch64_pstatefield_supported_p): Likewise.
1872
1873 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
1874
1875         * i386-dis.c (prefix_table): Fix a typo in comments.
1876
1877 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1878
1879         * i386-dis.c (rex_ignored): Delete.
1880         (ckprefix): Drop rex_ignored initialization.
1881         (get_valid_dis386): Drop setting of rex_ignored.
1882         (print_insn): Drop checking of rex_ignored. Don't record data
1883         size prefix as used with VEX-and-alike encodings.
1884
1885 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1886
1887         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1888         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1889         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1890         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1891         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1892         VEX_0F12, and VEX_0F16.
1893         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1894         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1895         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1896         from movlps and movhlps. New MOD_0F12_PREFIX_2,
1897         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1898         MOD_VEX_0F16_PREFIX_2 entries.
1899
1900 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1901
1902         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1903         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1904         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1905         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1906         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1907         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1908         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1909         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1910         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1911         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1912         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1913         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1914         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1915         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1916         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1917         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1918         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1919         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1920         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1921         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1922         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1923         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1924         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1925         EVEX_W_0FC6_P_2): Delete.
1926         (print_insn): Add EVEX.W vs embedded prefix consistency check
1927         to prefix validation.
1928         * i386-dis-evex.h (evex_table): Don't further descend for
1929         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1930         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1931         and 0F2B.
1932         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1933         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1934         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1935         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1936         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1937         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1938         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1939         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1940         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1941         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1942         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1943         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1944         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1945         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1946         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1947         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1948         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1949         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1950         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1951         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1952         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1953         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1954         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1955         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1956         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1957         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1958         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1959
1960 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1961
1962         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1963         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1964         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1965         vmovmskpX.
1966         (print_insn): Drop pointless check against bad_opcode. Split
1967         prefix validation into legacy and VEX-and-alike parts.
1968         (putop): Re-work 'X' macro handling.
1969
1970 2020-06-09  Jan Beulich  <jbeulich@suse.com>
1971
1972         * i386-dis.c (MOD_0F51): Rename to ...
1973         (MOD_0F50): ... this.
1974
1975 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
1976
1977         * arm-dis.c (arm_opcodes): Add dfb.
1978         (thumb32_opcodes): Add dfb.
1979
1980 2020-06-08  Jan Beulich  <jbeulich@suse.com>
1981
1982         * i386-opc.h (reg_entry): Const-qualify reg_name field.
1983
1984 2020-06-06  Alan Modra  <amodra@gmail.com>
1985
1986         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1987
1988 2020-06-05  Alan Modra  <amodra@gmail.com>
1989
1990         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
1991         size is large enough.
1992
1993 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
1994
1995         * disassemble.c (disassemble_init_for_target): Set endian_code for
1996         bpf targets.
1997         * bpf-desc.c: Regenerate.
1998         * bpf-opc.c: Likewise.
1999         * bpf-dis.c: Likewise.
2000
2001 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
2002
2003         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
2004         (cgen_put_insn_value): Likewise.
2005         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
2006         * cgen-dis.in (print_insn): Likewise.
2007         * cgen-ibld.in (insert_1): Likewise.
2008         (insert_1): Likewise.
2009         (insert_insn_normal): Likewise.
2010         (extract_1): Likewise.
2011         * bpf-dis.c: Regenerate.
2012         * bpf-ibld.c: Likewise.
2013         * bpf-ibld.c: Likewise.
2014         * cgen-dis.in: Likewise.
2015         * cgen-ibld.in: Likewise.
2016         * cgen-opc.c: Likewise.
2017         * epiphany-dis.c: Likewise.
2018         * epiphany-ibld.c: Likewise.
2019         * fr30-dis.c: Likewise.
2020         * fr30-ibld.c: Likewise.
2021         * frv-dis.c: Likewise.
2022         * frv-ibld.c: Likewise.
2023         * ip2k-dis.c: Likewise.
2024         * ip2k-ibld.c: Likewise.
2025         * iq2000-dis.c: Likewise.
2026         * iq2000-ibld.c: Likewise.
2027         * lm32-dis.c: Likewise.
2028         * lm32-ibld.c: Likewise.
2029         * m32c-dis.c: Likewise.
2030         * m32c-ibld.c: Likewise.
2031         * m32r-dis.c: Likewise.
2032         * m32r-ibld.c: Likewise.
2033         * mep-dis.c: Likewise.
2034         * mep-ibld.c: Likewise.
2035         * mt-dis.c: Likewise.
2036         * mt-ibld.c: Likewise.
2037         * or1k-dis.c: Likewise.
2038         * or1k-ibld.c: Likewise.
2039         * xc16x-dis.c: Likewise.
2040         * xc16x-ibld.c: Likewise.
2041         * xstormy16-dis.c: Likewise.
2042         * xstormy16-ibld.c: Likewise.
2043
2044 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
2045
2046         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
2047         (print_insn_): Handle instruction endian.
2048         * bpf-dis.c: Regenerate.
2049         * bpf-desc.c: Regenerate.
2050         * epiphany-dis.c: Likewise.
2051         * epiphany-desc.c: Likewise.
2052         * fr30-dis.c: Likewise.
2053         * fr30-desc.c: Likewise.
2054         * frv-dis.c: Likewise.
2055         * frv-desc.c: Likewise.
2056         * ip2k-dis.c: Likewise.
2057         * ip2k-desc.c: Likewise.
2058         * iq2000-dis.c: Likewise.
2059         * iq2000-desc.c: Likewise.
2060         * lm32-dis.c: Likewise.
2061         * lm32-desc.c: Likewise.
2062         * m32c-dis.c: Likewise.
2063         * m32c-desc.c: Likewise.
2064         * m32r-dis.c: Likewise.
2065         * m32r-desc.c: Likewise.
2066         * mep-dis.c: Likewise.
2067         * mep-desc.c: Likewise.
2068         * mt-dis.c: Likewise.
2069         * mt-desc.c: Likewise.
2070         * or1k-dis.c: Likewise.
2071         * or1k-desc.c: Likewise.
2072         * xc16x-dis.c: Likewise.
2073         * xc16x-desc.c: Likewise.
2074         * xstormy16-dis.c: Likewise.
2075         * xstormy16-desc.c: Likewise.
2076
2077 2020-06-03  Nick Clifton  <nickc@redhat.com>
2078
2079         * po/sr.po: Updated Serbian translation.
2080
2081 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
2082
2083         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
2084         (riscv_get_priv_spec_class): Likewise.
2085
2086 2020-06-01  Alan Modra  <amodra@gmail.com>
2087
2088         * bpf-desc.c: Regenerate.
2089
2090 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
2091             David Faust <david.faust@oracle.com>
2092
2093         * bpf-desc.c: Regenerate.
2094         * bpf-opc.h: Likewise.
2095         * bpf-opc.c: Likewise.
2096         * bpf-dis.c: Likewise.
2097
2098 2020-05-28  Alan Modra  <amodra@gmail.com>
2099
2100         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
2101         values.
2102
2103 2020-05-28  Alan Modra  <amodra@gmail.com>
2104
2105         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
2106         immediates.
2107         (print_insn_ns32k): Revert last change.
2108
2109 2020-05-28  Nick Clifton  <nickc@redhat.com>
2110
2111         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2112         static.
2113
2114 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
2115
2116         Fix extraction of signed constants in nios2 disassembler (again).
2117
2118         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2119         extractions of signed fields.
2120
2121 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
2122
2123         * s390-opc.txt: Relocate vector load/store instructions with
2124         additional alignment parameter and change architecture level
2125         constraint from z14 to z13.
2126
2127 2020-05-21  Alan Modra  <amodra@gmail.com>
2128
2129         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2130         * sparc-dis.c: Likewise.
2131         * tic4x-dis.c: Likewise.
2132         * xtensa-dis.c: Likewise.
2133         * bpf-desc.c: Regenerate.
2134         * epiphany-desc.c: Regenerate.
2135         * fr30-desc.c: Regenerate.
2136         * frv-desc.c: Regenerate.
2137         * ip2k-desc.c: Regenerate.
2138         * iq2000-desc.c: Regenerate.
2139         * lm32-desc.c: Regenerate.
2140         * m32c-desc.c: Regenerate.
2141         * m32r-desc.c: Regenerate.
2142         * mep-asm.c: Regenerate.
2143         * mep-desc.c: Regenerate.
2144         * mt-desc.c: Regenerate.
2145         * or1k-desc.c: Regenerate.
2146         * xc16x-desc.c: Regenerate.
2147         * xstormy16-desc.c: Regenerate.
2148
2149 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
2150
2151         * riscv-opc.c (riscv_ext_version_table): The table used to store
2152         all information about the supported spec and the corresponding ISA
2153         versions.  Currently, only Zicsr is supported to verify the
2154         correctness of Z sub extension settings.  Others will be supported
2155         in the future patches.
2156         (struct isa_spec_t, isa_specs): List for all supported ISA spec
2157         classes and the corresponding strings.
2158         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
2159         spec class by giving a ISA spec string.
2160         * riscv-opc.c (struct priv_spec_t): New structure.
2161         (struct priv_spec_t priv_specs): List for all supported privilege spec
2162         classes and the corresponding strings.
2163         (riscv_get_priv_spec_class): New function.  Get the corresponding
2164         privilege spec class by giving a spec string.
2165         (riscv_get_priv_spec_name): New function.  Get the corresponding
2166         privilege spec string by giving a CSR version class.
2167         * riscv-dis.c: Updated since DECLARE_CSR is changed.
2168         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2169         according to the chosen version.  Build a hash table riscv_csr_hash to
2170         store the valid CSR for the chosen pirv verison.  Dump the direct
2171         CSR address rather than it's name if it is invalid.
2172         (parse_riscv_dis_option_without_args): New function.  Parse the options
2173         without arguments.
2174         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2175         parse the options without arguments first, and then handle the options
2176         with arguments.  Add the new option -Mpriv-spec, which has argument.
2177         * riscv-dis.c (print_riscv_disassembler_options): Add description
2178         about the new OBJDUMP option.
2179
2180 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
2181
2182         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2183         WC values on POWER10 sync, dcbf  and wait instructions.
2184         (insert_pl, extract_pl): New functions.
2185         (L2OPT, LS, WC): Use insert_ls and extract_ls.
2186         (LS3): New , 3-bit L for sync.
2187         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2188         (SC2, PL): New, 2-bit SC and PL for sync and wait.
2189         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2190         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2191         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2192         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2193         <wait>: Enable PL operand on POWER10.
2194         <dcbf>: Enable L3OPT operand on POWER10.
2195         <sync>: Enable SC2 operand on POWER10.
2196
2197 2020-05-19  Stafford Horne  <shorne@gmail.com>
2198
2199         PR 25184
2200         * or1k-asm.c: Regenerate.
2201         * or1k-desc.c: Regenerate.
2202         * or1k-desc.h: Regenerate.
2203         * or1k-dis.c: Regenerate.
2204         * or1k-ibld.c: Regenerate.
2205         * or1k-opc.c: Regenerate.
2206         * or1k-opc.h: Regenerate.
2207         * or1k-opinst.c: Regenerate.
2208
2209 2020-05-11  Alan Modra  <amodra@gmail.com>
2210
2211         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2212         xsmaxcqp, xsmincqp.
2213
2214 2020-05-11  Alan Modra  <amodra@gmail.com>
2215
2216         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2217         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2218
2219 2020-05-11  Alan Modra  <amodra@gmail.com>
2220
2221         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2222
2223 2020-05-11  Alan Modra  <amodra@gmail.com>
2224
2225         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2226         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2227
2228 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2229
2230         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2231         mnemonics.
2232
2233 2020-05-11  Alan Modra  <amodra@gmail.com>
2234
2235         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2236         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2237         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2238         (prefix_opcodes): Add xxeval.
2239
2240 2020-05-11  Alan Modra  <amodra@gmail.com>
2241
2242         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2243         xxgenpcvwm, xxgenpcvdm.
2244
2245 2020-05-11  Alan Modra  <amodra@gmail.com>
2246
2247         * ppc-opc.c (MP, VXVAM_MASK): Define.
2248         (VXVAPS_MASK): Use VXVA_MASK.
2249         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2250         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2251         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2252         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2253
2254 2020-05-11  Alan Modra  <amodra@gmail.com>
2255             Peter Bergner  <bergner@linux.ibm.com>
2256
2257         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2258         New functions.
2259         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2260         YMSK2, XA6a, XA6ap, XB6a entries.
2261         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2262         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2263         (PPCVSX4): Define.
2264         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2265         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2266         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2267         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2268         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2269         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2270         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2271         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2272         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2273         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2274         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2275         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2276         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2277         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2278
2279 2020-05-11  Alan Modra  <amodra@gmail.com>
2280
2281         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2282         (insert_xts, extract_xts): New functions.
2283         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2284         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2285         (VXRC_MASK, VXSH_MASK): Define.
2286         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2287         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2288         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2289         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2290         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2291         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2292         xxblendvh, xxblendvw, xxblendvd, xxpermx.
2293
2294 2020-05-11  Alan Modra  <amodra@gmail.com>
2295
2296         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2297         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2298         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2299         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2300         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2301
2302 2020-05-11  Alan Modra  <amodra@gmail.com>
2303
2304         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2305         (XTP, DQXP, DQXP_MASK): Define.
2306         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2307         (prefix_opcodes): Add plxvp and pstxvp.
2308
2309 2020-05-11  Alan Modra  <amodra@gmail.com>
2310
2311         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2312         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2313         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2314
2315 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2316
2317         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2318
2319 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2320
2321         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2322         (L1OPT): Define.
2323         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2324
2325 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
2326
2327         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2328
2329 2020-05-11  Alan Modra  <amodra@gmail.com>
2330
2331         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2332
2333 2020-05-11  Alan Modra  <amodra@gmail.com>
2334
2335         * ppc-dis.c (ppc_opts): Add "power10" entry.
2336         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2337         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2338
2339 2020-05-11  Nick Clifton  <nickc@redhat.com>
2340
2341         * po/fr.po: Updated French translation.
2342
2343 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
2344
2345         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2346         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2347         (operand_general_constraint_met_p): validate
2348         AARCH64_OPND_UNDEFINED.
2349         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2350         for FLD_imm16_2.
2351         * aarch64-asm-2.c: Regenerated.
2352         * aarch64-dis-2.c: Regenerated.
2353         * aarch64-opc-2.c: Regenerated.
2354
2355 2020-04-29  Nick Clifton  <nickc@redhat.com>
2356
2357         PR 22699
2358         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2359         and SETRC insns.
2360
2361 2020-04-29  Nick Clifton  <nickc@redhat.com>
2362
2363         * po/sv.po: Updated Swedish translation.
2364
2365 2020-04-29  Nick Clifton  <nickc@redhat.com>
2366
2367         PR 22699
2368         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
2369         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2370         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2371         IMM0_8U case.
2372
2373 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
2374
2375         PR 25848
2376         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2377         cmpi only on m68020up and cpu32.
2378
2379 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2380
2381         * aarch64-asm.c (aarch64_ins_none): New.
2382         * aarch64-asm.h (ins_none): New declaration.
2383         * aarch64-dis.c (aarch64_ext_none): New.
2384         * aarch64-dis.h (ext_none): New declaration.
2385         * aarch64-opc.c (aarch64_print_operand): Update case for
2386         AARCH64_OPND_BARRIER_PSB.
2387         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2388         (AARCH64_OPERANDS): Update inserter/extracter for
2389         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2390         * aarch64-asm-2.c: Regenerated.
2391         * aarch64-dis-2.c: Regenerated.
2392         * aarch64-opc-2.c: Regenerated.
2393
2394 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
2395
2396         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2397         (aarch64_feature_ras, RAS): Likewise.
2398         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2399         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2400         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2401         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2402         * aarch64-asm-2.c: Regenerated.
2403         * aarch64-dis-2.c: Regenerated.
2404         * aarch64-opc-2.c: Regenerated.
2405
2406 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
2407
2408         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2409         (print_insn_neon): Support disassembly of conditional
2410         instructions.
2411
2412 2020-02-16  David Faust  <david.faust@oracle.com>
2413
2414         * bpf-desc.c: Regenerate.
2415         * bpf-desc.h: Likewise.
2416         * bpf-opc.c: Regenerate.
2417         * bpf-opc.h: Likewise.
2418
2419 2020-04-07  Lili Cui  <lili.cui@intel.com>
2420
2421         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2422         (prefix_table): New instructions (see prefixes above).
2423         (rm_table): Likewise
2424         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2425         CPU_ANY_TSXLDTRK_FLAGS.
2426         (cpu_flags): Add CpuTSXLDTRK.
2427         * i386-opc.h (enum): Add CpuTSXLDTRK.
2428         (i386_cpu_flags): Add cputsxldtrk.
2429         * i386-opc.tbl: Add XSUSPLDTRK insns.
2430         * i386-init.h: Regenerate.
2431         * i386-tbl.h: Likewise.
2432
2433 2020-04-02  Lili Cui  <lili.cui@intel.com>
2434
2435         * i386-dis.c (prefix_table): New instructions serialize.
2436         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2437         CPU_ANY_SERIALIZE_FLAGS.
2438         (cpu_flags): Add CpuSERIALIZE.
2439         * i386-opc.h (enum): Add CpuSERIALIZE.
2440         (i386_cpu_flags): Add cpuserialize.
2441         * i386-opc.tbl: Add SERIALIZE insns.
2442         * i386-init.h: Regenerate.
2443         * i386-tbl.h: Likewise.
2444
2445 2020-03-26  Alan Modra  <amodra@gmail.com>
2446
2447         * disassemble.h (opcodes_assert): Declare.
2448         (OPCODES_ASSERT): Define.
2449         * disassemble.c: Don't include assert.h.  Include opintl.h.
2450         (opcodes_assert): New function.
2451         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2452         (bfd_h8_disassemble): Reduce size of data array.  Correctly
2453         calculate maxlen.  Omit insn decoding when insn length exceeds
2454         maxlen.  Exit from nibble loop when looking for E, before
2455         accessing next data byte.  Move processing of E outside loop.
2456         Replace tests of maxlen in loop with assertions.
2457
2458 2020-03-26  Alan Modra  <amodra@gmail.com>
2459
2460         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2461
2462 2020-03-25  Alan Modra  <amodra@gmail.com>
2463
2464         * z80-dis.c (suffix): Init mybuf.
2465
2466 2020-03-22  Alan Modra  <amodra@gmail.com>
2467
2468         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2469         successflly read from section.
2470
2471 2020-03-22  Alan Modra  <amodra@gmail.com>
2472
2473         * arc-dis.c (find_format): Use ISO C string concatenation rather
2474         than line continuation within a string.  Don't access needs_limm
2475         before testing opcode != NULL.
2476
2477 2020-03-22  Alan Modra  <amodra@gmail.com>
2478
2479         * ns32k-dis.c (print_insn_arg): Update comment.
2480         (print_insn_ns32k): Reduce size of index_offset array, and
2481         initialize, passing -1 to print_insn_arg for args that are not
2482         an index.  Don't exit arg loop early.  Abort on bad arg number.
2483
2484 2020-03-22  Alan Modra  <amodra@gmail.com>
2485
2486         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2487         * s12z-opc.c: Formatting.
2488         (operands_f): Return an int.
2489         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2490         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2491         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2492         (exg_sex_discrim): Likewise.
2493         (create_immediate_operand, create_bitfield_operand),
2494         (create_register_operand_with_size, create_register_all_operand),
2495         (create_register_all16_operand, create_simple_memory_operand),
2496         (create_memory_operand, create_memory_auto_operand): Don't
2497         segfault on malloc failure.
2498         (z_ext24_decode): Return an int status, negative on fail, zero
2499         on success.
2500         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2501         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2502         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2503         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2504         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2505         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2506         (loop_primitive_decode, shift_decode, psh_pul_decode),
2507         (bit_field_decode): Similarly.
2508         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
2509         to return value, update callers.
2510         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2511         Don't segfault on NULL operand.
2512         (decode_operation): Return OP_INVALID on first fail.
2513         (decode_s12z): Check all reads, returning -1 on fail.
2514
2515 2020-03-20  Alan Modra  <amodra@gmail.com>
2516
2517         * metag-dis.c (print_insn_metag): Don't ignore status from
2518         read_memory_func.
2519
2520 2020-03-20  Alan Modra  <amodra@gmail.com>
2521
2522         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2523         Initialize parts of buffer not written when handling a possible
2524         2-byte insn at end of section.  Don't attempt decoding of such
2525         an insn by the 4-byte machinery.
2526
2527 2020-03-20  Alan Modra  <amodra@gmail.com>
2528
2529         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2530         partially filled buffer.  Prevent lookup of 4-byte insns when
2531         only VLE 2-byte insns are possible due to section size.  Print
2532         ".word" rather than ".long" for 2-byte leftovers.
2533
2534 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
2535
2536         PR 25641
2537         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2538
2539 2020-03-13  Jan Beulich  <jbeulich@suse.com>
2540
2541         * i386-dis.c (X86_64_0D): Rename to ...
2542         (X86_64_0E): ... this.
2543
2544 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
2545
2546         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2547         * Makefile.in: Regenerated.
2548
2549 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2550
2551         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2552         3-operand pseudos.
2553         * i386-tbl.h: Re-generate.
2554
2555 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2556
2557         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2558         vprot*, vpsha*, and vpshl*.
2559         * i386-tbl.h: Re-generate.
2560
2561 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2562
2563         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2564         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2565         * i386-tbl.h: Re-generate.
2566
2567 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2568
2569         * i386-gen.c (set_bitfield): Ignore zero-length field names.
2570         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2571         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2572         * i386-tbl.h: Re-generate.
2573
2574 2020-03-09  Jan Beulich  <jbeulich@suse.com>
2575
2576         * i386-gen.c (struct template_arg, struct template_instance,
2577         struct template_param, struct template, templates,
2578         parse_template, expand_templates): New.
2579         (process_i386_opcodes): Various local variables moved to
2580         expand_templates. Call parse_template and expand_templates.
2581         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2582         * i386-tbl.h: Re-generate.
2583
2584 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2585
2586         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2587         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2588         register and memory source templates. Replace VexW= by VexW*
2589         where applicable.
2590         * i386-tbl.h: Re-generate.
2591
2592 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2593
2594         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2595         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2596         * i386-tbl.h: Re-generate.
2597
2598 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2599
2600         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2601         * i386-tbl.h: Re-generate.
2602
2603 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2604
2605         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2606         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2607         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2608         VexW0 on SSE2AVX variants.
2609         (vmovq): Drop NoRex64 from XMM/XMM variants.
2610         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2611         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2612         applicable use VexW0.
2613         * i386-tbl.h: Re-generate.
2614
2615 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2616
2617         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2618         * i386-opc.h (Rex64): Delete.
2619         (struct i386_opcode_modifier): Remove rex64 field.
2620         * i386-opc.tbl (crc32): Drop Rex64.
2621         Replace Rex64 with Size64 everywhere else.
2622         * i386-tbl.h: Re-generate.
2623
2624 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2625
2626         * i386-dis.c (OP_E_memory): Exclude recording of used address
2627         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2628         addressed memory operands for MPX insns.
2629
2630 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2631
2632         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2633         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2634         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2635         (ptwrite): Split into non-64-bit and 64-bit forms.
2636         * i386-tbl.h: Re-generate.
2637
2638 2020-03-06  Jan Beulich  <jbeulich@suse.com>
2639
2640         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2641         template.
2642         * i386-tbl.h: Re-generate.
2643
2644 2020-03-04  Jan Beulich  <jbeulich@suse.com>
2645
2646         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2647         (prefix_table): Move vmmcall here. Add vmgexit.
2648         (rm_table): Replace vmmcall entry by prefix_table[] escape.
2649         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2650         (cpu_flags): Add CpuSEV_ES entry.
2651         * i386-opc.h (CpuSEV_ES): New.
2652         (union i386_cpu_flags): Add cpusev_es field.
2653         * i386-opc.tbl (vmgexit): New.
2654         * i386-init.h, i386-tbl.h: Re-generate.
2655
2656 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2657
2658         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2659         with MnemonicSize.
2660         * i386-opc.h (IGNORESIZE): New.
2661         (DEFAULTSIZE): Likewise.
2662         (IgnoreSize): Removed.
2663         (DefaultSize): Likewise.
2664         (MnemonicSize): New.
2665         (i386_opcode_modifier): Replace ignoresize/defaultsize with
2666         mnemonicsize.
2667         * i386-opc.tbl (IgnoreSize): New.
2668         (DefaultSize): Likewise.
2669         * i386-tbl.h: Regenerated.
2670
2671 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
2672
2673         PR 25627
2674         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2675         instructions.
2676
2677 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
2678
2679         PR gas/25622
2680         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2681         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2682         * i386-tbl.h: Regenerated.
2683
2684 2020-02-26  Alan Modra  <amodra@gmail.com>
2685
2686         * aarch64-asm.c: Indent labels correctly.
2687         * aarch64-dis.c: Likewise.
2688         * aarch64-gen.c: Likewise.
2689         * aarch64-opc.c: Likewise.
2690         * alpha-dis.c: Likewise.
2691         * i386-dis.c: Likewise.
2692         * nds32-asm.c: Likewise.
2693         * nfp-dis.c: Likewise.
2694         * visium-dis.c: Likewise.
2695
2696 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
2697
2698         * arc-regs.h (int_vector_base): Make it available for all ARC
2699         CPUs.
2700
2701 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
2702
2703         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2704         changed.
2705
2706 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
2707
2708         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2709         c.mv/c.li if rs1 is zero.
2710
2711 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
2712
2713         * i386-gen.c (cpu_flag_init): Replace CpuABM with
2714         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
2715         CPU_POPCNT_FLAGS.
2716         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
2717         * i386-opc.h (CpuABM): Removed.
2718         (CpuPOPCNT): New.
2719         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
2720         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2721         popcnt.  Remove CpuABM from lzcnt.
2722         * i386-init.h: Regenerated.
2723         * i386-tbl.h: Likewise.
2724
2725 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2726
2727         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2728         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2729         VexW1 instead of open-coding them.
2730         * i386-tbl.h: Re-generate.
2731
2732 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2733
2734         * i386-opc.tbl (AddrPrefixOpReg): Define.
2735         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2736         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2737         templates. Drop NoRex64.
2738         * i386-tbl.h: Re-generate.
2739
2740 2020-02-17  Jan Beulich  <jbeulich@suse.com>
2741
2742         PR gas/6518
2743         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2744         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2745         into Intel syntax instance (with Unpsecified) and AT&T one
2746         (without).
2747         (vcvtneps2bf16): Likewise, along with folding the two so far
2748         separate ones.
2749         * i386-tbl.h: Re-generate.
2750
2751 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2752
2753         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2754         CPU_ANY_SSE4A_FLAGS.
2755
2756 2020-02-17  Alan Modra  <amodra@gmail.com>
2757
2758         * i386-gen.c (cpu_flag_init): Correct last change.
2759
2760 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
2761
2762         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
2763         CPU_ANY_SSE4_FLAGS.
2764
2765 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
2766
2767         * i386-opc.tbl (movsx): Remove Intel syntax comments.
2768         (movzx): Likewise.
2769
2770 2020-02-14  Jan Beulich  <jbeulich@suse.com>
2771
2772         PR gas/25438
2773         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2774         destination for Cpu64-only variant.
2775         (movzx): Fold patterns.
2776         * i386-tbl.h: Re-generate.
2777
2778 2020-02-13  Jan Beulich  <jbeulich@suse.com>
2779
2780         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2781         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2782         CPU_ANY_SSE4_FLAGS entry.
2783         * i386-init.h: Re-generate.
2784
2785 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2786
2787         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2788         with Unspecified, making the present one AT&T syntax only.
2789         * i386-tbl.h: Re-generate.
2790
2791 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2792
2793         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2794         * i386-tbl.h: Re-generate.
2795
2796 2020-02-12  Jan Beulich  <jbeulich@suse.com>
2797
2798         PR gas/24546
2799         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2800         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2801         Amd64 and Intel64 templates.
2802         (call, jmp): Likewise for far indirect variants. Dro
2803         Unspecified.
2804         * i386-tbl.h: Re-generate.
2805
2806 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2807
2808         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2809         * i386-opc.h (ShortForm): Delete.
2810         (struct i386_opcode_modifier): Remove shortform field.
2811         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2812         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2813         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2814         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2815         Drop ShortForm.
2816         * i386-tbl.h: Re-generate.
2817
2818 2020-02-11  Jan Beulich  <jbeulich@suse.com>
2819
2820         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2821         fucompi): Drop ShortForm from operand-less templates.
2822         * i386-tbl.h: Re-generate.
2823
2824 2020-02-11  Alan Modra  <amodra@gmail.com>
2825
2826         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2827         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2828         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2829         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2830         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2831
2832 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
2833
2834         * arm-dis.c (print_insn_cde): Define 'V' parse character.
2835         (cde_opcodes): Add VCX* instructions.
2836
2837 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
2838             Matthew Malcomson  <matthew.malcomson@arm.com>
2839
2840         * arm-dis.c (struct cdeopcode32): New.
2841         (CDE_OPCODE): New macro.
2842         (cde_opcodes): New disassembly table.
2843         (regnames): New option to table.
2844         (cde_coprocs): New global variable.
2845         (print_insn_cde): New
2846         (print_insn_thumb32): Use print_insn_cde.
2847         (parse_arm_disassembler_options): Parse coprocN args.
2848
2849 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
2850
2851         PR gas/25516
2852         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2853         with ISA64.
2854         * i386-opc.h (AMD64): Removed.
2855         (Intel64): Likewose.
2856         (AMD64): New.
2857         (INTEL64): Likewise.
2858         (INTEL64ONLY): Likewise.
2859         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2860         * i386-opc.tbl (Amd64): New.
2861         (Intel64): Likewise.
2862         (Intel64Only): Likewise.
2863         Replace AMD64 with Amd64.  Update sysenter/sysenter with
2864         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
2865         * i386-tbl.h: Regenerated.
2866
2867 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
2868
2869         PR 25469
2870         * z80-dis.c: Add support for GBZ80 opcodes.
2871
2872 2020-02-04  Alan Modra  <amodra@gmail.com>
2873
2874         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2875
2876 2020-02-03  Alan Modra  <amodra@gmail.com>
2877
2878         * m32c-ibld.c: Regenerate.
2879
2880 2020-02-01  Alan Modra  <amodra@gmail.com>
2881
2882         * frv-ibld.c: Regenerate.
2883
2884 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2885
2886         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2887         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2888         (OP_E_memory): Replace xmm_mdq_mode case label by
2889         vex_scalar_w_dq_mode one.
2890         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2891
2892 2020-01-31  Jan Beulich  <jbeulich@suse.com>
2893
2894         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2895         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2896         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2897         (intel_operand_size): Drop vex_w_dq_mode case label.
2898
2899 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
2900
2901         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2902         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2903
2904 2020-01-30  Alan Modra  <amodra@gmail.com>
2905
2906         * m32c-ibld.c: Regenerate.
2907
2908 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
2909
2910         * bpf-opc.c: Regenerate.
2911
2912 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2913
2914         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2915         (dis386): Use them to replace C2/C3 table entries.
2916         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2917         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2918         ones. Use Size64 instead of DefaultSize on Intel64 ones.
2919         * i386-tbl.h: Re-generate.
2920
2921 2020-01-30  Jan Beulich  <jbeulich@suse.com>
2922
2923         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2924         forms.
2925         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2926         DefaultSize.
2927         * i386-tbl.h: Re-generate.
2928
2929 2020-01-30  Alan Modra  <amodra@gmail.com>
2930
2931         * tic4x-dis.c (tic4x_dp): Make unsigned.
2932
2933 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
2934             Jan Beulich  <jbeulich@suse.com>
2935
2936         PR binutils/25445
2937         * i386-dis.c (MOVSXD_Fixup): New function.
2938         (movsxd_mode): New enum.
2939         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2940         (intel_operand_size): Handle movsxd_mode.
2941         (OP_E_register): Likewise.
2942         (OP_G): Likewise.
2943         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2944         register on movsxd.  Add movsxd with 16-bit destination register
2945         for AMD64 and Intel64 ISAs.
2946         * i386-tbl.h: Regenerated.
2947
2948 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
2949
2950         PR 25403
2951         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2952         * aarch64-asm-2.c: Regenerate
2953         * aarch64-dis-2.c: Likewise.
2954         * aarch64-opc-2.c: Likewise.
2955
2956 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2957
2958         * i386-opc.tbl (sysret): Drop DefaultSize.
2959         * i386-tbl.h: Re-generate.
2960
2961 2020-01-21  Jan Beulich  <jbeulich@suse.com>
2962
2963         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2964         Dword.
2965         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2966         * i386-tbl.h: Re-generate.
2967
2968 2020-01-20  Nick Clifton  <nickc@redhat.com>
2969
2970         * po/de.po: Updated German translation.
2971         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2972         * po/uk.po: Updated Ukranian translation.
2973
2974 2020-01-20  Alan Modra  <amodra@gmail.com>
2975
2976         * hppa-dis.c (fput_const): Remove useless cast.
2977
2978 2020-01-20  Alan Modra  <amodra@gmail.com>
2979
2980         * arm-dis.c (print_insn_arm): Wrap 'T' value.
2981
2982 2020-01-18  Nick Clifton  <nickc@redhat.com>
2983
2984         * configure: Regenerate.
2985         * po/opcodes.pot: Regenerate.
2986
2987 2020-01-18  Nick Clifton  <nickc@redhat.com>
2988
2989         Binutils 2.34 branch created.
2990
2991 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
2992
2993         * opintl.h: Fix spelling error (seperate).
2994
2995 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
2996
2997         * i386-opc.tbl: Add {vex} pseudo prefix.
2998         * i386-tbl.h: Regenerated.
2999
3000 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
3001
3002         PR 25376
3003         * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
3004         (neon_opcodes): Likewise.
3005         (select_arm_features): Make sure we enable MVE bits when selecting
3006         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
3007         any architecture.
3008
3009 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3010
3011         * i386-opc.tbl: Drop stale comment from XOP section.
3012
3013 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3014
3015         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
3016         (extractps): Add VexWIG to SSE2AVX forms.
3017         * i386-tbl.h: Re-generate.
3018
3019 2020-01-16  Jan Beulich  <jbeulich@suse.com>
3020
3021         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
3022         Size64 from and use VexW1 on SSE2AVX forms.
3023         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
3024         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
3025         * i386-tbl.h: Re-generate.
3026
3027 2020-01-15  Alan Modra  <amodra@gmail.com>
3028
3029         * tic4x-dis.c (tic4x_version): Make unsigned long.
3030         (optab, optab_special, registernames): New file scope vars.
3031         (tic4x_print_register): Set up registernames rather than
3032         malloc'd registertable.
3033         (tic4x_disassemble): Delete optable and optable_special.  Use
3034         optab and optab_special instead.  Throw away old optab,
3035         optab_special and registernames when info->mach changes.
3036
3037 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
3038
3039         PR 25377
3040         * z80-dis.c (suffix): Use .db instruction to generate double
3041         prefix.
3042
3043 2020-01-14  Alan Modra  <amodra@gmail.com>
3044
3045         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
3046         values to unsigned before shifting.
3047
3048 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
3049
3050         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
3051         flow instructions.
3052         (print_insn_thumb16, print_insn_thumb32): Likewise.
3053         (print_insn): Initialize the insn info.
3054         * i386-dis.c (print_insn): Initialize the insn info fields, and
3055         detect jumps.
3056
3057 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3058
3059         * arc-opc.c (C_NE): Make it required.
3060
3061 2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
3062
3063         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
3064         reserved register name.
3065
3066 2020-01-13  Alan Modra  <amodra@gmail.com>
3067
3068         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
3069         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
3070
3071 2020-01-13  Alan Modra  <amodra@gmail.com>
3072
3073         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
3074         result of wasm_read_leb128 in a uint64_t and check that bits
3075         are not lost when copying to other locals.  Use uint32_t for
3076         most locals.  Use PRId64 when printing int64_t.
3077
3078 2020-01-13  Alan Modra  <amodra@gmail.com>
3079
3080         * score-dis.c: Formatting.
3081         * score7-dis.c: Formatting.
3082
3083 2020-01-13  Alan Modra  <amodra@gmail.com>
3084
3085         * score-dis.c (print_insn_score48): Use unsigned variables for
3086         unsigned values.  Don't left shift negative values.
3087         (print_insn_score32): Likewise.
3088         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
3089
3090 2020-01-13  Alan Modra  <amodra@gmail.com>
3091
3092         * tic4x-dis.c (tic4x_print_register): Remove dead code.
3093
3094 2020-01-13  Alan Modra  <amodra@gmail.com>
3095
3096         * fr30-ibld.c: Regenerate.
3097
3098 2020-01-13  Alan Modra  <amodra@gmail.com>
3099
3100         * xgate-dis.c (print_insn): Don't left shift signed value.
3101         (ripBits): Formatting, use 1u.
3102
3103 2020-01-10  Alan Modra  <amodra@gmail.com>
3104
3105         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
3106         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
3107
3108 2020-01-10  Alan Modra  <amodra@gmail.com>
3109
3110         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3111         and XRREG value earlier to avoid a shift with negative exponent.
3112         * m10200-dis.c (disassemble): Similarly.
3113
3114 2020-01-09  Nick Clifton  <nickc@redhat.com>
3115
3116         PR 25224
3117         * z80-dis.c (ld_ii_ii): Use correct cast.
3118
3119 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
3120
3121         PR 25224
3122         * z80-dis.c (ld_ii_ii): Use character constant when checking
3123         opcode byte value.
3124
3125 2020-01-09  Jan Beulich  <jbeulich@suse.com>
3126
3127         * i386-dis.c (SEP_Fixup): New.
3128         (SEP): Define.
3129         (dis386_twobyte): Use it for sysenter/sysexit.
3130         (enum x86_64_isa): Change amd64 enumerator to value 1.
3131         (OP_J): Compare isa64 against intel64 instead of amd64.
3132         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3133         forms.
3134         * i386-tbl.h: Re-generate.
3135
3136 2020-01-08  Alan Modra  <amodra@gmail.com>
3137
3138         * z8k-dis.c: Include libiberty.h
3139         (instr_data_s): Make max_fetched unsigned.
3140         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3141         Don't exceed byte_info bounds.
3142         (output_instr): Make num_bytes unsigned.
3143         (unpack_instr): Likewise for nibl_count and loop.
3144         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3145         idx unsigned.
3146         * z8k-opc.h: Regenerate.
3147
3148 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
3149
3150         * arc-tbl.h (llock): Use 'LLOCK' as class.
3151         (llockd): Likewise.
3152         (scond): Use 'SCOND' as class.
3153         (scondd): Likewise.
3154         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3155         (scondd): Likewise.
3156
3157 2020-01-06  Alan Modra  <amodra@gmail.com>
3158
3159         * m32c-ibld.c: Regenerate.
3160
3161 2020-01-06  Alan Modra  <amodra@gmail.com>
3162
3163         PR 25344
3164         * z80-dis.c (suffix): Don't use a local struct buffer copy.
3165         Peek at next byte to prevent recursion on repeated prefix bytes.
3166         Ensure uninitialised "mybuf" is not accessed.
3167         (print_insn_z80): Don't zero n_fetch and n_used here,..
3168         (print_insn_z80_buf): ..do it here instead.
3169
3170 2020-01-04  Alan Modra  <amodra@gmail.com>
3171
3172         * m32r-ibld.c: Regenerate.
3173
3174 2020-01-04  Alan Modra  <amodra@gmail.com>
3175
3176         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3177
3178 2020-01-04  Alan Modra  <amodra@gmail.com>
3179
3180         * crx-dis.c (match_opcode): Avoid shift left of signed value.
3181
3182 2020-01-04  Alan Modra  <amodra@gmail.com>
3183
3184         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3185
3186 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3187
3188         * aarch64-tbl.h (aarch64_opcode_table): Use
3189         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3190
3191 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3192
3193         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3194         forms of SUDOT and USDOT.
3195
3196 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3197
3198         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3199         uzip{1,2}.
3200         * aarch64-dis-2.c: Re-generate.
3201
3202 2020-01-03  Jan Beulich  <jbeulich@suse.com>
3203
3204         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3205         FMMLA encoding.
3206         * aarch64-dis-2.c: Re-generate.
3207
3208 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
3209
3210         * z80-dis.c: Add support for eZ80 and Z80 instructions.
3211
3212 2020-01-01  Alan Modra  <amodra@gmail.com>
3213
3214         Update year range in copyright notice of all files.
3215
3216 For older changes see ChangeLog-2019
3217 \f
3218 Copyright (C) 2020 Free Software Foundation, Inc.
3219
3220 Copying and distribution of this file, with or without modification,
3221 are permitted in any medium without royalty provided the copyright
3222 notice and this notice are preserved.
3223
3224 Local Variables:
3225 mode: change-log
3226 left-margin: 8
3227 fill-column: 74
3228 version-control: never
3229 End: