1 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-opc.h (Byte): Update comments.
13 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
15 * i386-tbl.h: Regenerated.
17 2018-07-12 Sudakshina Das <sudi.das@arm.com>
19 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
20 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
21 * aarch64-asm-2.c: Regenerate.
22 * aarch64-dis-2.c: Regenerate.
23 * aarch64-opc-2.c: Regenerate.
25 2018-07-12 Tamar Christina <tamar.christina@arm.com>
28 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
29 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
30 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
31 sqdmulh, sqrdmulh): Use Em16.
33 2018-07-11 Sudakshina Das <sudi.das@arm.com>
35 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
36 csdb together with them.
37 (thumb32_opcodes): Likewise.
39 2018-07-11 Jan Beulich <jbeulich@suse.com>
41 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
42 requiring 32-bit registers as operands 2 and 3. Improve
44 (mwait, mwaitx): Fold templates. Improve comments.
45 OPERAND_TYPE_INOUTPORTREG.
46 * i386-tbl.h: Re-generate.
48 2018-07-11 Jan Beulich <jbeulich@suse.com>
50 * i386-gen.c (operand_type_init): Remove
51 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
52 OPERAND_TYPE_INOUTPORTREG.
53 * i386-init.h: Re-generate.
55 2018-07-11 Jan Beulich <jbeulich@suse.com>
57 * i386-opc.tbl (wrssd, wrussd): Add Dword.
58 (wrssq, wrussq): Add Qword.
59 * i386-tbl.h: Re-generate.
61 2018-07-11 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.h: Rename OTMax to OTNum.
64 (OTNumOfUints): Adjust calculation.
65 (OTUnused): Directly alias to OTNum.
67 2018-07-09 Maciej W. Rozycki <macro@mips.com>
69 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
71 (lea_reg_xys): Likewise.
72 (print_insn_loop_primitive): Rename `reg' local variable to
75 2018-07-06 Tamar Christina <tamar.christina@arm.com>
78 * aarch64-tbl.h (ldarh): Fix disassembly mask.
80 2018-07-06 Tamar Christina <tamar.christina@arm.com>
83 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
84 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
86 2018-07-02 Maciej W. Rozycki <macro@mips.com>
89 * mips-dis.c (mips_option_arg_t): New enumeration.
90 (mips_options): New variable.
91 (disassembler_options_mips): New function.
92 (print_mips_disassembler_options): Reimplement in terms of
93 `disassembler_options_mips'.
94 * arm-dis.c (disassembler_options_arm): Adapt to using the
95 `disasm_options_and_args_t' structure.
96 * ppc-dis.c (disassembler_options_powerpc): Likewise.
97 * s390-dis.c (disassembler_options_s390): Likewise.
99 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
101 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
103 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
104 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
105 * testsuite/ld-arm/tls-longplt.d: Likewise.
107 2018-06-29 Tamar Christina <tamar.christina@arm.com>
110 * aarch64-asm-2.c: Regenerate.
111 * aarch64-dis-2.c: Likewise.
112 * aarch64-opc-2.c: Likewise.
113 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
114 * aarch64-opc.c (operand_general_constraint_met_p,
115 aarch64_print_operand): Likewise.
116 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
117 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
119 (AARCH64_OPERANDS): Add Em2.
121 2018-06-26 Nick Clifton <nickc@redhat.com>
123 * po/uk.po: Updated Ukranian translation.
124 * po/de.po: Updated German translation.
125 * po/pt_BR.po: Updated Brazilian Portuguese translation.
127 2018-06-26 Nick Clifton <nickc@redhat.com>
129 * nfp-dis.c: Fix spelling mistake.
131 2018-06-24 Nick Clifton <nickc@redhat.com>
133 * configure: Regenerate.
134 * po/opcodes.pot: Regenerate.
136 2018-06-24 Nick Clifton <nickc@redhat.com>
140 2018-06-19 Tamar Christina <tamar.christina@arm.com>
142 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
143 * aarch64-asm-2.c: Regenerate.
144 * aarch64-dis-2.c: Likewise.
146 2018-06-21 Maciej W. Rozycki <macro@mips.com>
148 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
149 `-M ginv' option description.
151 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
154 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
157 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
159 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
160 * configure.ac: Remove AC_PREREQ.
161 * Makefile.in: Re-generate.
162 * aclocal.m4: Re-generate.
163 * configure: Re-generate.
165 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
167 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
168 mips64r6 descriptors.
169 (parse_mips_ase_option): Handle -Mginv option.
170 (print_mips_disassembler_options): Document -Mginv.
171 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
173 (mips_opcodes): Define ginvi and ginvt.
175 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
176 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
178 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
179 * mips-opc.c (CRC, CRC64): New macros.
180 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
181 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
184 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
187 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
188 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
190 2018-06-06 Alan Modra <amodra@gmail.com>
192 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
193 setjmp. Move init for some other vars later too.
195 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
197 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
198 (dis_private): Add new fields for property section tracking.
199 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
200 (xtensa_instruction_fits): New functions.
201 (fetch_data): Bump minimal fetch size to 4.
202 (print_insn_xtensa): Make struct dis_private static.
203 Load and prepare property table on section change.
204 Don't disassemble literals. Don't disassemble instructions that
205 cross property table boundaries.
207 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
209 * configure: Regenerated.
211 2018-06-01 Jan Beulich <jbeulich@suse.com>
213 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
214 * i386-tbl.h: Re-generate.
216 2018-06-01 Jan Beulich <jbeulich@suse.com>
218 * i386-opc.tbl (sldt, str): Add NoRex64.
219 * i386-tbl.h: Re-generate.
221 2018-06-01 Jan Beulich <jbeulich@suse.com>
223 * i386-opc.tbl (invpcid): Add Oword.
224 * i386-tbl.h: Re-generate.
226 2018-06-01 Alan Modra <amodra@gmail.com>
228 * sysdep.h (_bfd_error_handler): Don't declare.
229 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
230 * rl78-decode.opc: Likewise.
231 * msp430-decode.c: Regenerate.
232 * rl78-decode.c: Regenerate.
234 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
236 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
237 * i386-init.h : Regenerated.
239 2018-05-25 Alan Modra <amodra@gmail.com>
241 * Makefile.in: Regenerate.
242 * po/POTFILES.in: Regenerate.
244 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
246 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
247 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
248 (insert_bab, extract_bab, insert_btab, extract_btab,
249 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
250 (BAT, BBA VBA RBS XB6S): Delete macros.
251 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
252 (BB, BD, RBX, XC6): Update for new macros.
253 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
254 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
255 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
256 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
258 2018-05-18 John Darrington <john@darrington.wattle.id.au>
260 * Makefile.am: Add support for s12z architecture.
261 * configure.ac: Likewise.
262 * disassemble.c: Likewise.
263 * disassemble.h: Likewise.
264 * Makefile.in: Regenerate.
265 * configure: Regenerate.
266 * s12z-dis.c: New file.
269 2018-05-18 Alan Modra <amodra@gmail.com>
271 * nfp-dis.c: Don't #include libbfd.h.
272 (init_nfp3200_priv): Use bfd_get_section_contents.
273 (nit_nfp6000_mecsr_sec): Likewise.
275 2018-05-17 Nick Clifton <nickc@redhat.com>
277 * po/zh_CN.po: Updated simplified Chinese translation.
279 2018-05-16 Tamar Christina <tamar.christina@arm.com>
282 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
283 * aarch64-dis-2.c: Regenerate.
285 2018-05-15 Tamar Christina <tamar.christina@arm.com>
288 * aarch64-asm.c (opintl.h): Include.
289 (aarch64_ins_sysreg): Enforce read/write constraints.
290 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
291 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
292 (F_REG_READ, F_REG_WRITE): New.
293 * aarch64-opc.c (aarch64_print_operand): Generate notes for
295 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
296 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
297 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
298 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
299 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
300 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
301 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
302 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
303 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
304 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
305 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
306 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
307 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
308 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
309 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
310 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
311 msr (F_SYS_WRITE), mrs (F_SYS_READ).
313 2018-05-15 Tamar Christina <tamar.christina@arm.com>
316 * aarch64-dis.c (no_notes: New.
317 (parse_aarch64_dis_option): Support notes.
318 (aarch64_decode_insn, print_operands): Likewise.
319 (print_aarch64_disassembler_options): Document notes.
320 * aarch64-opc.c (aarch64_print_operand): Support notes.
322 2018-05-15 Tamar Christina <tamar.christina@arm.com>
325 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
326 and take error struct.
327 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
328 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
329 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
330 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
331 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
332 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
333 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
334 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
335 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
336 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
337 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
338 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
339 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
340 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
341 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
342 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
343 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
344 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
345 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
346 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
347 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
348 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
349 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
350 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
351 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
352 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
353 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
354 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
355 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
356 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
357 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
358 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
359 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
360 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
361 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
362 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
363 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
364 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
365 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
366 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
367 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
368 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
369 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
370 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
371 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
372 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
373 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
374 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
375 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
376 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
377 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
378 (determine_disassembling_preference, aarch64_decode_insn,
379 print_insn_aarch64_word, print_insn_data): Take errors struct.
380 (print_insn_aarch64): Use errors.
381 * aarch64-asm-2.c: Regenerate.
382 * aarch64-dis-2.c: Regenerate.
383 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
384 boolean in aarch64_insert_operan.
385 (print_operand_extractor): Likewise.
386 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
388 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
390 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
392 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
394 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
396 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
398 * cr16-opc.c (cr16_instruction): Comment typo fix.
399 * hppa-dis.c (print_insn_hppa): Likewise.
401 2018-05-08 Jim Wilson <jimw@sifive.com>
403 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
404 (match_c_slli64, match_srxi_as_c_srxi): New.
405 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
406 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
407 <c.slli, c.srli, c.srai>: Use match_s_slli.
408 <c.slli64, c.srli64, c.srai64>: New.
410 2018-05-08 Alan Modra <amodra@gmail.com>
412 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
413 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
414 partition opcode space for index lookup.
416 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
418 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
419 <insn_length>: ...with this. Update usage.
420 Remove duplicate call to *info->memory_error_func.
422 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
423 H.J. Lu <hongjiu.lu@intel.com>
425 * i386-dis.c (Gva): New.
426 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
427 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
428 (prefix_table): New instructions (see prefix above).
429 (mod_table): New instructions (see prefix above).
430 (OP_G): Handle va_mode.
431 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
433 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
434 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
435 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
436 * i386-opc.tbl: Add movidir{i,64b}.
437 * i386-init.h: Regenerated.
438 * i386-tbl.h: Likewise.
440 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
442 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
444 * i386-opc.h (AddrPrefixOp0): Renamed to ...
445 (AddrPrefixOpReg): This.
446 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
447 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
449 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
451 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
452 (vle_num_opcodes): Likewise.
453 (spe2_num_opcodes): Likewise.
454 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
456 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
457 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
460 2018-05-01 Tamar Christina <tamar.christina@arm.com>
462 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
464 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
466 Makefile.am: Added nfp-dis.c.
467 configure.ac: Added bfd_nfp_arch.
468 disassemble.h: Added print_insn_nfp prototype.
469 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
470 nfp-dis.c: New, for NFP support.
471 po/POTFILES.in: Added nfp-dis.c to the list.
472 Makefile.in: Regenerate.
473 configure: Regenerate.
475 2018-04-26 Jan Beulich <jbeulich@suse.com>
477 * i386-opc.tbl: Fold various non-memory operand AVX512VL
478 templates into their base ones.
479 * i386-tlb.h: Re-generate.
481 2018-04-26 Jan Beulich <jbeulich@suse.com>
483 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
484 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
485 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
486 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
487 * i386-init.h: Re-generate.
489 2018-04-26 Jan Beulich <jbeulich@suse.com>
491 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
492 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
493 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
494 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
496 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
498 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
500 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
501 cpuregzmm, and cpuregmask.
502 * i386-init.h: Re-generate.
503 * i386-tbl.h: Re-generate.
505 2018-04-26 Jan Beulich <jbeulich@suse.com>
507 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
508 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
509 * i386-init.h: Re-generate.
511 2018-04-26 Jan Beulich <jbeulich@suse.com>
513 * i386-gen.c (VexImmExt): Delete.
514 * i386-opc.h (VexImmExt, veximmext): Delete.
515 * i386-opc.tbl: Drop all VexImmExt uses.
516 * i386-tlb.h: Re-generate.
518 2018-04-25 Jan Beulich <jbeulich@suse.com>
520 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
522 * i386-tlb.h: Re-generate.
524 2018-04-25 Tamar Christina <tamar.christina@arm.com>
526 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
528 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
530 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
532 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
533 (cpu_flags): Add CpuCLDEMOTE.
534 * i386-init.h: Regenerate.
535 * i386-opc.h (enum): Add CpuCLDEMOTE,
536 (i386_cpu_flags): Add cpucldemote.
537 * i386-opc.tbl: Add cldemote.
538 * i386-tbl.h: Regenerate.
540 2018-04-16 Alan Modra <amodra@gmail.com>
542 * Makefile.am: Remove sh5 and sh64 support.
543 * configure.ac: Likewise.
544 * disassemble.c: Likewise.
545 * disassemble.h: Likewise.
546 * sh-dis.c: Likewise.
547 * sh64-dis.c: Delete.
548 * sh64-opc.c: Delete.
549 * sh64-opc.h: Delete.
550 * Makefile.in: Regenerate.
551 * configure: Regenerate.
552 * po/POTFILES.in: Regenerate.
554 2018-04-16 Alan Modra <amodra@gmail.com>
556 * Makefile.am: Remove w65 support.
557 * configure.ac: Likewise.
558 * disassemble.c: Likewise.
559 * disassemble.h: Likewise.
562 * Makefile.in: Regenerate.
563 * configure: Regenerate.
564 * po/POTFILES.in: Regenerate.
566 2018-04-16 Alan Modra <amodra@gmail.com>
568 * configure.ac: Remove we32k support.
569 * configure: Regenerate.
571 2018-04-16 Alan Modra <amodra@gmail.com>
573 * Makefile.am: Remove m88k support.
574 * configure.ac: Likewise.
575 * disassemble.c: Likewise.
576 * disassemble.h: Likewise.
577 * m88k-dis.c: Delete.
578 * Makefile.in: Regenerate.
579 * configure: Regenerate.
580 * po/POTFILES.in: Regenerate.
582 2018-04-16 Alan Modra <amodra@gmail.com>
584 * Makefile.am: Remove i370 support.
585 * configure.ac: Likewise.
586 * disassemble.c: Likewise.
587 * disassemble.h: Likewise.
588 * i370-dis.c: Delete.
589 * i370-opc.c: Delete.
590 * Makefile.in: Regenerate.
591 * configure: Regenerate.
592 * po/POTFILES.in: Regenerate.
594 2018-04-16 Alan Modra <amodra@gmail.com>
596 * Makefile.am: Remove h8500 support.
597 * configure.ac: Likewise.
598 * disassemble.c: Likewise.
599 * disassemble.h: Likewise.
600 * h8500-dis.c: Delete.
601 * h8500-opc.h: Delete.
602 * Makefile.in: Regenerate.
603 * configure: Regenerate.
604 * po/POTFILES.in: Regenerate.
606 2018-04-16 Alan Modra <amodra@gmail.com>
608 * configure.ac: Remove tahoe support.
609 * configure: Regenerate.
611 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
613 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
615 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
617 * i386-tbl.h: Regenerated.
619 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
621 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
622 PREFIX_MOD_1_0FAE_REG_6.
624 (OP_E_register): Use va_mode.
625 * i386-dis-evex.h (prefix_table):
626 New instructions (see prefixes above).
627 * i386-gen.c (cpu_flag_init): Add WAITPKG.
628 (cpu_flags): Likewise.
629 * i386-opc.h (enum): Likewise.
630 (i386_cpu_flags): Likewise.
631 * i386-opc.tbl: Add umonitor, umwait, tpause.
632 * i386-init.h: Regenerate.
633 * i386-tbl.h: Likewise.
635 2018-04-11 Alan Modra <amodra@gmail.com>
637 * opcodes/i860-dis.c: Delete.
638 * opcodes/i960-dis.c: Delete.
639 * Makefile.am: Remove i860 and i960 support.
640 * configure.ac: Likewise.
641 * disassemble.c: Likewise.
642 * disassemble.h: Likewise.
643 * Makefile.in: Regenerate.
644 * configure: Regenerate.
645 * po/POTFILES.in: Regenerate.
647 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
650 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
652 (print_insn): Clear vex instead of vex.evex.
654 2018-04-04 Nick Clifton <nickc@redhat.com>
656 * po/es.po: Updated Spanish translation.
658 2018-03-28 Jan Beulich <jbeulich@suse.com>
660 * i386-gen.c (opcode_modifiers): Delete VecESize.
661 * i386-opc.h (VecESize): Delete.
662 (struct i386_opcode_modifier): Delete vecesize.
663 * i386-opc.tbl: Drop VecESize.
664 * i386-tlb.h: Re-generate.
666 2018-03-28 Jan Beulich <jbeulich@suse.com>
668 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
669 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
670 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
671 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
672 * i386-tlb.h: Re-generate.
674 2018-03-28 Jan Beulich <jbeulich@suse.com>
676 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
678 * i386-tlb.h: Re-generate.
680 2018-03-28 Jan Beulich <jbeulich@suse.com>
682 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
683 (vex_len_table): Drop Y for vcvt*2si.
684 (putop): Replace plain 'Y' handling by abort().
686 2018-03-28 Nick Clifton <nickc@redhat.com>
689 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
690 instructions with only a base address register.
691 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
692 handle AARHC64_OPND_SVE_ADDR_R.
693 (aarch64_print_operand): Likewise.
694 * aarch64-asm-2.c: Regenerate.
695 * aarch64_dis-2.c: Regenerate.
696 * aarch64-opc-2.c: Regenerate.
698 2018-03-22 Jan Beulich <jbeulich@suse.com>
700 * i386-opc.tbl: Drop VecESize from register only insn forms and
701 memory forms not allowing broadcast.
702 * i386-tlb.h: Re-generate.
704 2018-03-22 Jan Beulich <jbeulich@suse.com>
706 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
707 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
708 sha256*): Drop Disp<N>.
710 2018-03-22 Jan Beulich <jbeulich@suse.com>
712 * i386-dis.c (EbndS, bnd_swap_mode): New.
713 (prefix_table): Use EbndS.
714 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
715 * i386-opc.tbl (bndmov): Move misplaced Load.
716 * i386-tlb.h: Re-generate.
718 2018-03-22 Jan Beulich <jbeulich@suse.com>
720 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
721 templates allowing memory operands and folded ones for register
723 * i386-tlb.h: Re-generate.
725 2018-03-22 Jan Beulich <jbeulich@suse.com>
727 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
728 256-bit templates. Drop redundant leftover Disp<N>.
729 * i386-tlb.h: Re-generate.
731 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
733 * riscv-opc.c (riscv_insn_types): New.
735 2018-03-13 Nick Clifton <nickc@redhat.com>
737 * po/pt_BR.po: Updated Brazilian Portuguese translation.
739 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
741 * i386-opc.tbl: Add Optimize to clr.
742 * i386-tbl.h: Regenerated.
744 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
746 * i386-gen.c (opcode_modifiers): Remove OldGcc.
747 * i386-opc.h (OldGcc): Removed.
748 (i386_opcode_modifier): Remove oldgcc.
749 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
750 instructions for old (<= 2.8.1) versions of gcc.
751 * i386-tbl.h: Regenerated.
753 2018-03-08 Jan Beulich <jbeulich@suse.com>
755 * i386-opc.h (EVEXDYN): New.
756 * i386-opc.tbl: Fold various AVX512VL templates.
757 * i386-tlb.h: Re-generate.
759 2018-03-08 Jan Beulich <jbeulich@suse.com>
761 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
762 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
763 vpexpandd, vpexpandq): Fold AFX512VF templates.
764 * i386-tlb.h: Re-generate.
766 2018-03-08 Jan Beulich <jbeulich@suse.com>
768 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
769 Fold 128- and 256-bit VEX-encoded templates.
770 * i386-tlb.h: Re-generate.
772 2018-03-08 Jan Beulich <jbeulich@suse.com>
774 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
775 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
776 vpexpandd, vpexpandq): Fold AVX512F templates.
777 * i386-tlb.h: Re-generate.
779 2018-03-08 Jan Beulich <jbeulich@suse.com>
781 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
782 64-bit templates. Drop Disp<N>.
783 * i386-tlb.h: Re-generate.
785 2018-03-08 Jan Beulich <jbeulich@suse.com>
787 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
788 and 256-bit templates.
789 * i386-tlb.h: Re-generate.
791 2018-03-08 Jan Beulich <jbeulich@suse.com>
793 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
794 * i386-tlb.h: Re-generate.
796 2018-03-08 Jan Beulich <jbeulich@suse.com>
798 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
800 * i386-tlb.h: Re-generate.
802 2018-03-08 Jan Beulich <jbeulich@suse.com>
804 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
805 * i386-tlb.h: Re-generate.
807 2018-03-08 Jan Beulich <jbeulich@suse.com>
809 * i386-gen.c (opcode_modifiers): Delete FloatD.
810 * i386-opc.h (FloatD): Delete.
811 (struct i386_opcode_modifier): Delete floatd.
812 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
814 * i386-tlb.h: Re-generate.
816 2018-03-08 Jan Beulich <jbeulich@suse.com>
818 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
820 2018-03-08 Jan Beulich <jbeulich@suse.com>
822 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
823 * i386-tlb.h: Re-generate.
825 2018-03-08 Jan Beulich <jbeulich@suse.com>
827 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
829 * i386-tlb.h: Re-generate.
831 2018-03-07 Alan Modra <amodra@gmail.com>
833 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
835 * disassemble.h (print_insn_rs6000): Delete.
836 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
837 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
838 (print_insn_rs6000): Delete.
840 2018-03-03 Alan Modra <amodra@gmail.com>
842 * sysdep.h (opcodes_error_handler): Define.
843 (_bfd_error_handler): Declare.
844 * Makefile.am: Remove stray #.
845 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
847 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
848 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
849 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
850 opcodes_error_handler to print errors. Standardize error messages.
851 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
852 and include opintl.h.
853 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
854 * i386-gen.c: Standardize error messages.
855 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
856 * Makefile.in: Regenerate.
857 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
858 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
859 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
860 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
861 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
862 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
863 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
864 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
865 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
866 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
867 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
868 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
869 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
871 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
873 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
874 vpsub[bwdq] instructions.
875 * i386-tbl.h: Regenerated.
877 2018-03-01 Alan Modra <amodra@gmail.com>
879 * configure.ac (ALL_LINGUAS): Sort.
880 * configure: Regenerate.
882 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
884 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
885 macro by assignements.
887 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
890 * i386-gen.c (opcode_modifiers): Add Optimize.
891 * i386-opc.h (Optimize): New enum.
892 (i386_opcode_modifier): Add optimize.
893 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
894 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
895 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
896 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
897 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
899 * i386-tbl.h: Regenerated.
901 2018-02-26 Alan Modra <amodra@gmail.com>
903 * crx-dis.c (getregliststring): Allocate a large enough buffer
904 to silence false positive gcc8 warning.
906 2018-02-22 Shea Levy <shea@shealevy.com>
908 * disassemble.c (ARCH_riscv): Define if ARCH_all.
910 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
912 * i386-opc.tbl: Add {rex},
913 * i386-tbl.h: Regenerated.
915 2018-02-20 Maciej W. Rozycki <macro@mips.com>
917 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
918 (mips16_opcodes): Replace `M' with `m' for "restore".
920 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
922 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
924 2018-02-13 Maciej W. Rozycki <macro@mips.com>
926 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
927 variable to `function_index'.
929 2018-02-13 Nick Clifton <nickc@redhat.com>
932 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
933 about truncation of printing.
935 2018-02-12 Henry Wong <henry@stuffedcow.net>
937 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
939 2018-02-05 Nick Clifton <nickc@redhat.com>
941 * po/pt_BR.po: Updated Brazilian Portuguese translation.
943 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
945 * i386-dis.c (enum): Add pconfig.
946 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
947 (cpu_flags): Add CpuPCONFIG.
948 * i386-opc.h (enum): Add CpuPCONFIG.
949 (i386_cpu_flags): Add cpupconfig.
950 * i386-opc.tbl: Add PCONFIG instruction.
951 * i386-init.h: Regenerate.
952 * i386-tbl.h: Likewise.
954 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
956 * i386-dis.c (enum): Add PREFIX_0F09.
957 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
958 (cpu_flags): Add CpuWBNOINVD.
959 * i386-opc.h (enum): Add CpuWBNOINVD.
960 (i386_cpu_flags): Add cpuwbnoinvd.
961 * i386-opc.tbl: Add WBNOINVD instruction.
962 * i386-init.h: Regenerate.
963 * i386-tbl.h: Likewise.
965 2018-01-17 Jim Wilson <jimw@sifive.com>
967 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
969 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
971 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
972 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
973 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
974 (cpu_flags): Add CpuIBT, CpuSHSTK.
975 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
976 (i386_cpu_flags): Add cpuibt, cpushstk.
977 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
978 * i386-init.h: Regenerate.
979 * i386-tbl.h: Likewise.
981 2018-01-16 Nick Clifton <nickc@redhat.com>
983 * po/pt_BR.po: Updated Brazilian Portugese translation.
984 * po/de.po: Updated German translation.
986 2018-01-15 Jim Wilson <jimw@sifive.com>
988 * riscv-opc.c (match_c_nop): New.
989 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
991 2018-01-15 Nick Clifton <nickc@redhat.com>
993 * po/uk.po: Updated Ukranian translation.
995 2018-01-13 Nick Clifton <nickc@redhat.com>
997 * po/opcodes.pot: Regenerated.
999 2018-01-13 Nick Clifton <nickc@redhat.com>
1001 * configure: Regenerate.
1003 2018-01-13 Nick Clifton <nickc@redhat.com>
1005 2.30 branch created.
1007 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1009 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1010 * i386-tbl.h: Regenerate.
1012 2018-01-10 Jan Beulich <jbeulich@suse.com>
1014 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1015 * i386-tbl.h: Re-generate.
1017 2018-01-10 Jan Beulich <jbeulich@suse.com>
1019 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1020 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1021 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1022 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1023 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1024 Disp8MemShift of AVX512VL forms.
1025 * i386-tbl.h: Re-generate.
1027 2018-01-09 Jim Wilson <jimw@sifive.com>
1029 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1030 then the hi_addr value is zero.
1032 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1034 * arm-dis.c (arm_opcodes): Add csdb.
1035 (thumb32_opcodes): Add csdb.
1037 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1039 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1040 * aarch64-asm-2.c: Regenerate.
1041 * aarch64-dis-2.c: Regenerate.
1042 * aarch64-opc-2.c: Regenerate.
1044 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1047 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1048 Remove AVX512 vmovd with 64-bit operands.
1049 * i386-tbl.h: Regenerated.
1051 2018-01-05 Jim Wilson <jimw@sifive.com>
1053 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1056 2018-01-03 Alan Modra <amodra@gmail.com>
1058 Update year range in copyright notice of all files.
1060 2018-01-02 Jan Beulich <jbeulich@suse.com>
1062 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1063 and OPERAND_TYPE_REGZMM entries.
1065 For older changes see ChangeLog-2017
1067 Copyright (C) 2018 Free Software Foundation, Inc.
1069 Copying and distribution of this file, with or without modification,
1070 are permitted in any medium without royalty provided the copyright
1071 notice and this notice are preserved.
1077 version-control: never