opcodes/ChangeLog

   1 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
   2
   3         * aarch64-opc.c (SYSREG): New macro for describing system registers.
   4         (SR_CORE): Likewise.
   5         (SR_FEAT): Likewise.
   6         (SR_RNG): Likewise.
   7         (SR_V8_1): Likewise.
   8         (SR_V8_2): Likewise.
   9         (SR_V8_3): Likewise.
  10         (SR_V8_4): Likewise.
  11         (SR_PAN): Likewise.
  12         (SR_RAS): Likewise.
  13         (SR_SSBS): Likewise.
  14         (SR_SVE): Likewise.
  15         (SR_ID_PFR2): Likewise.
  16         (SR_PROFILE): Likewise.
  17         (SR_MEMTAG): Likewise.
  18         (SR_SCXTNUM): Likewise.
  19         (aarch64_sys_regs): Refactor to store feature information in the table.
  20         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  21         that now describe their own features.
  22         (aarch64_pstatefield_supported_p): Likewise.
  23
  24 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  25
  26         * i386-dis.c (prefix_table): Fix a typo in comments.
  27
  28 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-dis.c (rex_ignored): Delete.
  31         (ckprefix): Drop rex_ignored initialization.
  32         (get_valid_dis386): Drop setting of rex_ignored.
  33         (print_insn): Drop checking of rex_ignored. Don't record data
  34         size prefix as used with VEX-and-alike encodings.
  35
  36 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  39         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  40         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  41         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  42         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  43         VEX_0F12, and VEX_0F16.
  44         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  45         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  46         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  47         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  48         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  49         MOD_VEX_0F16_PREFIX_2 entries.
  50
  51 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  54         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
  55         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  56         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
  57         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
  58         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
  59         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
  60         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
  61         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
  62         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
  63         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
  64         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
  65         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
  66         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
  67         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
  68         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
  69         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
  70         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
  71         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
  72         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
  73         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
  74         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
  75         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
  76         EVEX_W_0FC6_P_2): Delete.
  77         (print_insn): Add EVEX.W vs embedded prefix consistency check
  78         to prefix validation.
  79         * i386-dis-evex.h (evex_table): Don't further descend for
  80         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
  81         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
  82         and 0F2B.
  83         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
  84         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
  85         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
  86         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
  87         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
  88         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
  89         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
  90         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
  91         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
  92         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
  93         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
  94         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
  95         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
  96         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
  97         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
  98         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
  99         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 100         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 101         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 102         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 103         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 104         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 105         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 106         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 107         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 108         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 109         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 110
 111 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 114         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 115         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 116         vmovmskpX.
 117         (print_insn): Drop pointless check against bad_opcode. Split
 118         prefix validation into legacy and VEX-and-alike parts.
 119         (putop): Re-work 'X' macro handling.
 120
 121 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 122
 123         * i386-dis.c (MOD_0F51): Rename to ...
 124         (MOD_0F50): ... this.
 125
 126 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 127
 128         * arm-dis.c (arm_opcodes): Add dfb.
 129         (thumb32_opcodes): Add dfb.
 130
 131 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 134
 135 2020-06-06  Alan Modra  <amodra@gmail.com>
 136
 137         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 138
 139 2020-06-05  Alan Modra  <amodra@gmail.com>
 140
 141         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 142         size is large enough.
 143
 144 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 145
 146         * disassemble.c (disassemble_init_for_target): Set endian_code for
 147         bpf targets.
 148         * bpf-desc.c: Regenerate.
 149         * bpf-opc.c: Likewise.
 150         * bpf-dis.c: Likewise.
 151
 152 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 153
 154         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 155         (cgen_put_insn_value): Likewise.
 156         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 157         * cgen-dis.in (print_insn): Likewise.
 158         * cgen-ibld.in (insert_1): Likewise.
 159         (insert_1): Likewise.
 160         (insert_insn_normal): Likewise.
 161         (extract_1): Likewise.
 162         * bpf-dis.c: Regenerate.
 163         * bpf-ibld.c: Likewise.
 164         * bpf-ibld.c: Likewise.
 165         * cgen-dis.in: Likewise.
 166         * cgen-ibld.in: Likewise.
 167         * cgen-opc.c: Likewise.
 168         * epiphany-dis.c: Likewise.
 169         * epiphany-ibld.c: Likewise.
 170         * fr30-dis.c: Likewise.
 171         * fr30-ibld.c: Likewise.
 172         * frv-dis.c: Likewise.
 173         * frv-ibld.c: Likewise.
 174         * ip2k-dis.c: Likewise.
 175         * ip2k-ibld.c: Likewise.
 176         * iq2000-dis.c: Likewise.
 177         * iq2000-ibld.c: Likewise.
 178         * lm32-dis.c: Likewise.
 179         * lm32-ibld.c: Likewise.
 180         * m32c-dis.c: Likewise.
 181         * m32c-ibld.c: Likewise.
 182         * m32r-dis.c: Likewise.
 183         * m32r-ibld.c: Likewise.
 184         * mep-dis.c: Likewise.
 185         * mep-ibld.c: Likewise.
 186         * mt-dis.c: Likewise.
 187         * mt-ibld.c: Likewise.
 188         * or1k-dis.c: Likewise.
 189         * or1k-ibld.c: Likewise.
 190         * xc16x-dis.c: Likewise.
 191         * xc16x-ibld.c: Likewise.
 192         * xstormy16-dis.c: Likewise.
 193         * xstormy16-ibld.c: Likewise.
 194
 195 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 196
 197         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 198         (print_insn_): Handle instruction endian.
 199         * bpf-dis.c: Regenerate.
 200         * bpf-desc.c: Regenerate.
 201         * epiphany-dis.c: Likewise.
 202         * epiphany-desc.c: Likewise.
 203         * fr30-dis.c: Likewise.
 204         * fr30-desc.c: Likewise.
 205         * frv-dis.c: Likewise.
 206         * frv-desc.c: Likewise.
 207         * ip2k-dis.c: Likewise.
 208         * ip2k-desc.c: Likewise.
 209         * iq2000-dis.c: Likewise.
 210         * iq2000-desc.c: Likewise.
 211         * lm32-dis.c: Likewise.
 212         * lm32-desc.c: Likewise.
 213         * m32c-dis.c: Likewise.
 214         * m32c-desc.c: Likewise.
 215         * m32r-dis.c: Likewise.
 216         * m32r-desc.c: Likewise.
 217         * mep-dis.c: Likewise.
 218         * mep-desc.c: Likewise.
 219         * mt-dis.c: Likewise.
 220         * mt-desc.c: Likewise.
 221         * or1k-dis.c: Likewise.
 222         * or1k-desc.c: Likewise.
 223         * xc16x-dis.c: Likewise.
 224         * xc16x-desc.c: Likewise.
 225         * xstormy16-dis.c: Likewise.
 226         * xstormy16-desc.c: Likewise.
 227
 228 2020-06-03  Nick Clifton  <nickc@redhat.com>
 229
 230         * po/sr.po: Updated Serbian translation.
 231
 232 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 233
 234         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 235         (riscv_get_priv_spec_class): Likewise.
 236
 237 2020-06-01  Alan Modra  <amodra@gmail.com>
 238
 239         * bpf-desc.c: Regenerate.
 240
 241 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 242             David Faust <david.faust@oracle.com>
 243
 244         * bpf-desc.c: Regenerate.
 245         * bpf-opc.h: Likewise.
 246         * bpf-opc.c: Likewise.
 247         * bpf-dis.c: Likewise.
 248
 249 2020-05-28  Alan Modra  <amodra@gmail.com>
 250
 251         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 252         values.
 253
 254 2020-05-28  Alan Modra  <amodra@gmail.com>
 255
 256         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 257         immediates.
 258         (print_insn_ns32k): Revert last change.
 259
 260 2020-05-28  Nick Clifton  <nickc@redhat.com>
 261
 262         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 263         static.
 264
 265 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 266
 267         Fix extraction of signed constants in nios2 disassembler (again).
 268
 269         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 270         extractions of signed fields.
 271
 272 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 273
 274         * s390-opc.txt: Relocate vector load/store instructions with
 275         additional alignment parameter and change architecture level
 276         constraint from z14 to z13.
 277
 278 2020-05-21  Alan Modra  <amodra@gmail.com>
 279
 280         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 281         * sparc-dis.c: Likewise.
 282         * tic4x-dis.c: Likewise.
 283         * xtensa-dis.c: Likewise.
 284         * bpf-desc.c: Regenerate.
 285         * epiphany-desc.c: Regenerate.
 286         * fr30-desc.c: Regenerate.
 287         * frv-desc.c: Regenerate.
 288         * ip2k-desc.c: Regenerate.
 289         * iq2000-desc.c: Regenerate.
 290         * lm32-desc.c: Regenerate.
 291         * m32c-desc.c: Regenerate.
 292         * m32r-desc.c: Regenerate.
 293         * mep-asm.c: Regenerate.
 294         * mep-desc.c: Regenerate.
 295         * mt-desc.c: Regenerate.
 296         * or1k-desc.c: Regenerate.
 297         * xc16x-desc.c: Regenerate.
 298         * xstormy16-desc.c: Regenerate.
 299
 300 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 301
 302         * riscv-opc.c (riscv_ext_version_table): The table used to store
 303         all information about the supported spec and the corresponding ISA
 304         versions.  Currently, only Zicsr is supported to verify the
 305         correctness of Z sub extension settings.  Others will be supported
 306         in the future patches.
 307         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 308         classes and the corresponding strings.
 309         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 310         spec class by giving a ISA spec string.
 311         * riscv-opc.c (struct priv_spec_t): New structure.
 312         (struct priv_spec_t priv_specs): List for all supported privilege spec
 313         classes and the corresponding strings.
 314         (riscv_get_priv_spec_class): New function.  Get the corresponding
 315         privilege spec class by giving a spec string.
 316         (riscv_get_priv_spec_name): New function.  Get the corresponding
 317         privilege spec string by giving a CSR version class.
 318         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 319         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 320         according to the chosen version.  Build a hash table riscv_csr_hash to
 321         store the valid CSR for the chosen pirv verison.  Dump the direct
 322         CSR address rather than it's name if it is invalid.
 323         (parse_riscv_dis_option_without_args): New function.  Parse the options
 324         without arguments.
 325         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 326         parse the options without arguments first, and then handle the options
 327         with arguments.  Add the new option -Mpriv-spec, which has argument.
 328         * riscv-dis.c (print_riscv_disassembler_options): Add description
 329         about the new OBJDUMP option.
 330
 331 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 332
 333         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 334         WC values on POWER10 sync, dcbf  and wait instructions.
 335         (insert_pl, extract_pl): New functions.
 336         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 337         (LS3): New , 3-bit L for sync.
 338         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 339         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 340         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 341         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 342         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 343         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 344         <wait>: Enable PL operand on POWER10.
 345         <dcbf>: Enable L3OPT operand on POWER10.
 346         <sync>: Enable SC2 operand on POWER10.
 347
 348 2020-05-19  Stafford Horne  <shorne@gmail.com>
 349
 350         PR 25184
 351         * or1k-asm.c: Regenerate.
 352         * or1k-desc.c: Regenerate.
 353         * or1k-desc.h: Regenerate.
 354         * or1k-dis.c: Regenerate.
 355         * or1k-ibld.c: Regenerate.
 356         * or1k-opc.c: Regenerate.
 357         * or1k-opc.h: Regenerate.
 358         * or1k-opinst.c: Regenerate.
 359
 360 2020-05-11  Alan Modra  <amodra@gmail.com>
 361
 362         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 363         xsmaxcqp, xsmincqp.
 364
 365 2020-05-11  Alan Modra  <amodra@gmail.com>
 366
 367         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 368         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 369
 370 2020-05-11  Alan Modra  <amodra@gmail.com>
 371
 372         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 373
 374 2020-05-11  Alan Modra  <amodra@gmail.com>
 375
 376         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 377         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 378
 379 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 380
 381         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 382         mnemonics.
 383
 384 2020-05-11  Alan Modra  <amodra@gmail.com>
 385
 386         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 387         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 388         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 389         (prefix_opcodes): Add xxeval.
 390
 391 2020-05-11  Alan Modra  <amodra@gmail.com>
 392
 393         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 394         xxgenpcvwm, xxgenpcvdm.
 395
 396 2020-05-11  Alan Modra  <amodra@gmail.com>
 397
 398         * ppc-opc.c (MP, VXVAM_MASK): Define.
 399         (VXVAPS_MASK): Use VXVA_MASK.
 400         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 401         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 402         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 403         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 404
 405 2020-05-11  Alan Modra  <amodra@gmail.com>
 406             Peter Bergner  <bergner@linux.ibm.com>
 407
 408         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 409         New functions.
 410         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 411         YMSK2, XA6a, XA6ap, XB6a entries.
 412         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 413         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 414         (PPCVSX4): Define.
 415         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 416         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 417         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 418         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 419         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 420         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 421         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 422         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 423         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 424         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 425         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 426         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 427         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 428         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 429
 430 2020-05-11  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 433         (insert_xts, extract_xts): New functions.
 434         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 435         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 436         (VXRC_MASK, VXSH_MASK): Define.
 437         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 438         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 439         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 440         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 441         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 442         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 443         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 444
 445 2020-05-11  Alan Modra  <amodra@gmail.com>
 446
 447         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 448         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 449         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 450         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 451         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 452
 453 2020-05-11  Alan Modra  <amodra@gmail.com>
 454
 455         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 456         (XTP, DQXP, DQXP_MASK): Define.
 457         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 458         (prefix_opcodes): Add plxvp and pstxvp.
 459
 460 2020-05-11  Alan Modra  <amodra@gmail.com>
 461
 462         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 463         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 464         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 465
 466 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 467
 468         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 469
 470 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 471
 472         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 473         (L1OPT): Define.
 474         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 475
 476 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 477
 478         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 479
 480 2020-05-11  Alan Modra  <amodra@gmail.com>
 481
 482         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 483
 484 2020-05-11  Alan Modra  <amodra@gmail.com>
 485
 486         * ppc-dis.c (ppc_opts): Add "power10" entry.
 487         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 488         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 489
 490 2020-05-11  Nick Clifton  <nickc@redhat.com>
 491
 492         * po/fr.po: Updated French translation.
 493
 494 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 495
 496         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 497         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 498         (operand_general_constraint_met_p): validate
 499         AARCH64_OPND_UNDEFINED.
 500         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 501         for FLD_imm16_2.
 502         * aarch64-asm-2.c: Regenerated.
 503         * aarch64-dis-2.c: Regenerated.
 504         * aarch64-opc-2.c: Regenerated.
 505
 506 2020-04-29  Nick Clifton  <nickc@redhat.com>
 507
 508         PR 22699
 509         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 510         and SETRC insns.
 511
 512 2020-04-29  Nick Clifton  <nickc@redhat.com>
 513
 514         * po/sv.po: Updated Swedish translation.
 515
 516 2020-04-29  Nick Clifton  <nickc@redhat.com>
 517
 518         PR 22699
 519         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 520         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 521         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 522         IMM0_8U case.
 523
 524 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 525
 526         PR 25848
 527         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 528         cmpi only on m68020up and cpu32.
 529
 530 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 531
 532         * aarch64-asm.c (aarch64_ins_none): New.
 533         * aarch64-asm.h (ins_none): New declaration.
 534         * aarch64-dis.c (aarch64_ext_none): New.
 535         * aarch64-dis.h (ext_none): New declaration.
 536         * aarch64-opc.c (aarch64_print_operand): Update case for
 537         AARCH64_OPND_BARRIER_PSB.
 538         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 539         (AARCH64_OPERANDS): Update inserter/extracter for
 540         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 541         * aarch64-asm-2.c: Regenerated.
 542         * aarch64-dis-2.c: Regenerated.
 543         * aarch64-opc-2.c: Regenerated.
 544
 545 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 546
 547         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 548         (aarch64_feature_ras, RAS): Likewise.
 549         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 550         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 551         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 552         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 553         * aarch64-asm-2.c: Regenerated.
 554         * aarch64-dis-2.c: Regenerated.
 555         * aarch64-opc-2.c: Regenerated.
 556
 557 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 558
 559         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 560         (print_insn_neon): Support disassembly of conditional
 561         instructions.
 562
 563 2020-02-16  David Faust  <david.faust@oracle.com>
 564
 565         * bpf-desc.c: Regenerate.
 566         * bpf-desc.h: Likewise.
 567         * bpf-opc.c: Regenerate.
 568         * bpf-opc.h: Likewise.
 569
 570 2020-04-07  Lili Cui  <lili.cui@intel.com>
 571
 572         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 573         (prefix_table): New instructions (see prefixes above).
 574         (rm_table): Likewise
 575         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 576         CPU_ANY_TSXLDTRK_FLAGS.
 577         (cpu_flags): Add CpuTSXLDTRK.
 578         * i386-opc.h (enum): Add CpuTSXLDTRK.
 579         (i386_cpu_flags): Add cputsxldtrk.
 580         * i386-opc.tbl: Add XSUSPLDTRK insns.
 581         * i386-init.h: Regenerate.
 582         * i386-tbl.h: Likewise.
 583
 584 2020-04-02  Lili Cui  <lili.cui@intel.com>
 585
 586         * i386-dis.c (prefix_table): New instructions serialize.
 587         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 588         CPU_ANY_SERIALIZE_FLAGS.
 589         (cpu_flags): Add CpuSERIALIZE.
 590         * i386-opc.h (enum): Add CpuSERIALIZE.
 591         (i386_cpu_flags): Add cpuserialize.
 592         * i386-opc.tbl: Add SERIALIZE insns.
 593         * i386-init.h: Regenerate.
 594         * i386-tbl.h: Likewise.
 595
 596 2020-03-26  Alan Modra  <amodra@gmail.com>
 597
 598         * disassemble.h (opcodes_assert): Declare.
 599         (OPCODES_ASSERT): Define.
 600         * disassemble.c: Don't include assert.h.  Include opintl.h.
 601         (opcodes_assert): New function.
 602         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 603         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 604         calculate maxlen.  Omit insn decoding when insn length exceeds
 605         maxlen.  Exit from nibble loop when looking for E, before
 606         accessing next data byte.  Move processing of E outside loop.
 607         Replace tests of maxlen in loop with assertions.
 608
 609 2020-03-26  Alan Modra  <amodra@gmail.com>
 610
 611         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 612
 613 2020-03-25  Alan Modra  <amodra@gmail.com>
 614
 615         * z80-dis.c (suffix): Init mybuf.
 616
 617 2020-03-22  Alan Modra  <amodra@gmail.com>
 618
 619         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 620         successflly read from section.
 621
 622 2020-03-22  Alan Modra  <amodra@gmail.com>
 623
 624         * arc-dis.c (find_format): Use ISO C string concatenation rather
 625         than line continuation within a string.  Don't access needs_limm
 626         before testing opcode != NULL.
 627
 628 2020-03-22  Alan Modra  <amodra@gmail.com>
 629
 630         * ns32k-dis.c (print_insn_arg): Update comment.
 631         (print_insn_ns32k): Reduce size of index_offset array, and
 632         initialize, passing -1 to print_insn_arg for args that are not
 633         an index.  Don't exit arg loop early.  Abort on bad arg number.
 634
 635 2020-03-22  Alan Modra  <amodra@gmail.com>
 636
 637         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 638         * s12z-opc.c: Formatting.
 639         (operands_f): Return an int.
 640         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 641         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 642         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 643         (exg_sex_discrim): Likewise.
 644         (create_immediate_operand, create_bitfield_operand),
 645         (create_register_operand_with_size, create_register_all_operand),
 646         (create_register_all16_operand, create_simple_memory_operand),
 647         (create_memory_operand, create_memory_auto_operand): Don't
 648         segfault on malloc failure.
 649         (z_ext24_decode): Return an int status, negative on fail, zero
 650         on success.
 651         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 652         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 653         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 654         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 655         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 656         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 657         (loop_primitive_decode, shift_decode, psh_pul_decode),
 658         (bit_field_decode): Similarly.
 659         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 660         to return value, update callers.
 661         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 662         Don't segfault on NULL operand.
 663         (decode_operation): Return OP_INVALID on first fail.
 664         (decode_s12z): Check all reads, returning -1 on fail.
 665
 666 2020-03-20  Alan Modra  <amodra@gmail.com>
 667
 668         * metag-dis.c (print_insn_metag): Don't ignore status from
 669         read_memory_func.
 670
 671 2020-03-20  Alan Modra  <amodra@gmail.com>
 672
 673         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 674         Initialize parts of buffer not written when handling a possible
 675         2-byte insn at end of section.  Don't attempt decoding of such
 676         an insn by the 4-byte machinery.
 677
 678 2020-03-20  Alan Modra  <amodra@gmail.com>
 679
 680         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 681         partially filled buffer.  Prevent lookup of 4-byte insns when
 682         only VLE 2-byte insns are possible due to section size.  Print
 683         ".word" rather than ".long" for 2-byte leftovers.
 684
 685 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 686
 687         PR 25641
 688         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 689
 690 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-dis.c (X86_64_0D): Rename to ...
 693         (X86_64_0E): ... this.
 694
 695 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 698         * Makefile.in: Regenerated.
 699
 700 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 703         3-operand pseudos.
 704         * i386-tbl.h: Re-generate.
 705
 706 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 709         vprot*, vpsha*, and vpshl*.
 710         * i386-tbl.h: Re-generate.
 711
 712 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 715         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 716         * i386-tbl.h: Re-generate.
 717
 718 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 721         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 722         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 723         * i386-tbl.h: Re-generate.
 724
 725 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-gen.c (struct template_arg, struct template_instance,
 728         struct template_param, struct template, templates,
 729         parse_template, expand_templates): New.
 730         (process_i386_opcodes): Various local variables moved to
 731         expand_templates. Call parse_template and expand_templates.
 732         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 733         * i386-tbl.h: Re-generate.
 734
 735 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 738         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 739         register and memory source templates. Replace VexW= by VexW*
 740         where applicable.
 741         * i386-tbl.h: Re-generate.
 742
 743 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 744
 745         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 746         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 747         * i386-tbl.h: Re-generate.
 748
 749 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 752         * i386-tbl.h: Re-generate.
 753
 754 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 757         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 758         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 759         VexW0 on SSE2AVX variants.
 760         (vmovq): Drop NoRex64 from XMM/XMM variants.
 761         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 762         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 763         applicable use VexW0.
 764         * i386-tbl.h: Re-generate.
 765
 766 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 769         * i386-opc.h (Rex64): Delete.
 770         (struct i386_opcode_modifier): Remove rex64 field.
 771         * i386-opc.tbl (crc32): Drop Rex64.
 772         Replace Rex64 with Size64 everywhere else.
 773         * i386-tbl.h: Re-generate.
 774
 775 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-dis.c (OP_E_memory): Exclude recording of used address
 778         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 779         addressed memory operands for MPX insns.
 780
 781 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 782
 783         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 784         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 785         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 786         (ptwrite): Split into non-64-bit and 64-bit forms.
 787         * i386-tbl.h: Re-generate.
 788
 789 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 792         template.
 793         * i386-tbl.h: Re-generate.
 794
 795 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 798         (prefix_table): Move vmmcall here. Add vmgexit.
 799         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 800         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 801         (cpu_flags): Add CpuSEV_ES entry.
 802         * i386-opc.h (CpuSEV_ES): New.
 803         (union i386_cpu_flags): Add cpusev_es field.
 804         * i386-opc.tbl (vmgexit): New.
 805         * i386-init.h, i386-tbl.h: Re-generate.
 806
 807 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 810         with MnemonicSize.
 811         * i386-opc.h (IGNORESIZE): New.
 812         (DEFAULTSIZE): Likewise.
 813         (IgnoreSize): Removed.
 814         (DefaultSize): Likewise.
 815         (MnemonicSize): New.
 816         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 817         mnemonicsize.
 818         * i386-opc.tbl (IgnoreSize): New.
 819         (DefaultSize): Likewise.
 820         * i386-tbl.h: Regenerated.
 821
 822 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 823
 824         PR 25627
 825         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 826         instructions.
 827
 828 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 829
 830         PR gas/25622
 831         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 832         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 833         * i386-tbl.h: Regenerated.
 834
 835 2020-02-26  Alan Modra  <amodra@gmail.com>
 836
 837         * aarch64-asm.c: Indent labels correctly.
 838         * aarch64-dis.c: Likewise.
 839         * aarch64-gen.c: Likewise.
 840         * aarch64-opc.c: Likewise.
 841         * alpha-dis.c: Likewise.
 842         * i386-dis.c: Likewise.
 843         * nds32-asm.c: Likewise.
 844         * nfp-dis.c: Likewise.
 845         * visium-dis.c: Likewise.
 846
 847 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 848
 849         * arc-regs.h (int_vector_base): Make it available for all ARC
 850         CPUs.
 851
 852 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 853
 854         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 855         changed.
 856
 857 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 858
 859         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 860         c.mv/c.li if rs1 is zero.
 861
 862 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 863
 864         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 865         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 866         CPU_POPCNT_FLAGS.
 867         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 868         * i386-opc.h (CpuABM): Removed.
 869         (CpuPOPCNT): New.
 870         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 871         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 872         popcnt.  Remove CpuABM from lzcnt.
 873         * i386-init.h: Regenerated.
 874         * i386-tbl.h: Likewise.
 875
 876 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 877
 878         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 879         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 880         VexW1 instead of open-coding them.
 881         * i386-tbl.h: Re-generate.
 882
 883 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl (AddrPrefixOpReg): Define.
 886         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 887         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 888         templates. Drop NoRex64.
 889         * i386-tbl.h: Re-generate.
 890
 891 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 892
 893         PR gas/6518
 894         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 895         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 896         into Intel syntax instance (with Unpsecified) and AT&T one
 897         (without).
 898         (vcvtneps2bf16): Likewise, along with folding the two so far
 899         separate ones.
 900         * i386-tbl.h: Re-generate.
 901
 902 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 905         CPU_ANY_SSE4A_FLAGS.
 906
 907 2020-02-17  Alan Modra  <amodra@gmail.com>
 908
 909         * i386-gen.c (cpu_flag_init): Correct last change.
 910
 911 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 912
 913         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 914         CPU_ANY_SSE4_FLAGS.
 915
 916 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 917
 918         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 919         (movzx): Likewise.
 920
 921 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 922
 923         PR gas/25438
 924         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 925         destination for Cpu64-only variant.
 926         (movzx): Fold patterns.
 927         * i386-tbl.h: Re-generate.
 928
 929 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 930
 931         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 932         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 933         CPU_ANY_SSE4_FLAGS entry.
 934         * i386-init.h: Re-generate.
 935
 936 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 937
 938         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 939         with Unspecified, making the present one AT&T syntax only.
 940         * i386-tbl.h: Re-generate.
 941
 942 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 943
 944         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 945         * i386-tbl.h: Re-generate.
 946
 947 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 948
 949         PR gas/24546
 950         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 951         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 952         Amd64 and Intel64 templates.
 953         (call, jmp): Likewise for far indirect variants. Dro
 954         Unspecified.
 955         * i386-tbl.h: Re-generate.
 956
 957 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 960         * i386-opc.h (ShortForm): Delete.
 961         (struct i386_opcode_modifier): Remove shortform field.
 962         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 963         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 964         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 965         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 966         Drop ShortForm.
 967         * i386-tbl.h: Re-generate.
 968
 969 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 970
 971         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 972         fucompi): Drop ShortForm from operand-less templates.
 973         * i386-tbl.h: Re-generate.
 974
 975 2020-02-11  Alan Modra  <amodra@gmail.com>
 976
 977         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 978         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 979         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 980         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 981         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 982
 983 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 984
 985         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 986         (cde_opcodes): Add VCX* instructions.
 987
 988 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 989             Matthew Malcomson  <matthew.malcomson@arm.com>
 990
 991         * arm-dis.c (struct cdeopcode32): New.
 992         (CDE_OPCODE): New macro.
 993         (cde_opcodes): New disassembly table.
 994         (regnames): New option to table.
 995         (cde_coprocs): New global variable.
 996         (print_insn_cde): New
 997         (print_insn_thumb32): Use print_insn_cde.
 998         (parse_arm_disassembler_options): Parse coprocN args.
 999
1000 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1001
1002         PR gas/25516
1003         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1004         with ISA64.
1005         * i386-opc.h (AMD64): Removed.
1006         (Intel64): Likewose.
1007         (AMD64): New.
1008         (INTEL64): Likewise.
1009         (INTEL64ONLY): Likewise.
1010         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1011         * i386-opc.tbl (Amd64): New.
1012         (Intel64): Likewise.
1013         (Intel64Only): Likewise.
1014         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1015         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1016         * i386-tbl.h: Regenerated.
1017
1018 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1019
1020         PR 25469
1021         * z80-dis.c: Add support for GBZ80 opcodes.
1022
1023 2020-02-04  Alan Modra  <amodra@gmail.com>
1024
1025         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1026
1027 2020-02-03  Alan Modra  <amodra@gmail.com>
1028
1029         * m32c-ibld.c: Regenerate.
1030
1031 2020-02-01  Alan Modra  <amodra@gmail.com>
1032
1033         * frv-ibld.c: Regenerate.
1034
1035 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1038         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1039         (OP_E_memory): Replace xmm_mdq_mode case label by
1040         vex_scalar_w_dq_mode one.
1041         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1042
1043 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1046         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1047         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1048         (intel_operand_size): Drop vex_w_dq_mode case label.
1049
1050 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1051
1052         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1053         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1054
1055 2020-01-30  Alan Modra  <amodra@gmail.com>
1056
1057         * m32c-ibld.c: Regenerate.
1058
1059 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1060
1061         * bpf-opc.c: Regenerate.
1062
1063 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1066         (dis386): Use them to replace C2/C3 table entries.
1067         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1068         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1069         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1070         * i386-tbl.h: Re-generate.
1071
1072 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1075         forms.
1076         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1077         DefaultSize.
1078         * i386-tbl.h: Re-generate.
1079
1080 2020-01-30  Alan Modra  <amodra@gmail.com>
1081
1082         * tic4x-dis.c (tic4x_dp): Make unsigned.
1083
1084 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1085             Jan Beulich  <jbeulich@suse.com>
1086
1087         PR binutils/25445
1088         * i386-dis.c (MOVSXD_Fixup): New function.
1089         (movsxd_mode): New enum.
1090         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1091         (intel_operand_size): Handle movsxd_mode.
1092         (OP_E_register): Likewise.
1093         (OP_G): Likewise.
1094         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1095         register on movsxd.  Add movsxd with 16-bit destination register
1096         for AMD64 and Intel64 ISAs.
1097         * i386-tbl.h: Regenerated.
1098
1099 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1100
1101         PR 25403
1102         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1103         * aarch64-asm-2.c: Regenerate
1104         * aarch64-dis-2.c: Likewise.
1105         * aarch64-opc-2.c: Likewise.
1106
1107 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-opc.tbl (sysret): Drop DefaultSize.
1110         * i386-tbl.h: Re-generate.
1111
1112 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1115         Dword.
1116         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1117         * i386-tbl.h: Re-generate.
1118
1119 2020-01-20  Nick Clifton  <nickc@redhat.com>
1120
1121         * po/de.po: Updated German translation.
1122         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1123         * po/uk.po: Updated Ukranian translation.
1124
1125 2020-01-20  Alan Modra  <amodra@gmail.com>
1126
1127         * hppa-dis.c (fput_const): Remove useless cast.
1128
1129 2020-01-20  Alan Modra  <amodra@gmail.com>
1130
1131         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1132
1133 2020-01-18  Nick Clifton  <nickc@redhat.com>
1134
1135         * configure: Regenerate.
1136         * po/opcodes.pot: Regenerate.
1137
1138 2020-01-18  Nick Clifton  <nickc@redhat.com>
1139
1140         Binutils 2.34 branch created.
1141
1142 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1143
1144         * opintl.h: Fix spelling error (seperate).
1145
1146 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1147
1148         * i386-opc.tbl: Add {vex} pseudo prefix.
1149         * i386-tbl.h: Regenerated.
1150
1151 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1152
1153         PR 25376
1154         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1155         (neon_opcodes): Likewise.
1156         (select_arm_features): Make sure we enable MVE bits when selecting
1157         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1158         any architecture.
1159
1160 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1161
1162         * i386-opc.tbl: Drop stale comment from XOP section.
1163
1164 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1167         (extractps): Add VexWIG to SSE2AVX forms.
1168         * i386-tbl.h: Re-generate.
1169
1170 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1173         Size64 from and use VexW1 on SSE2AVX forms.
1174         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1175         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1176         * i386-tbl.h: Re-generate.
1177
1178 2020-01-15  Alan Modra  <amodra@gmail.com>
1179
1180         * tic4x-dis.c (tic4x_version): Make unsigned long.
1181         (optab, optab_special, registernames): New file scope vars.
1182         (tic4x_print_register): Set up registernames rather than
1183         malloc'd registertable.
1184         (tic4x_disassemble): Delete optable and optable_special.  Use
1185         optab and optab_special instead.  Throw away old optab,
1186         optab_special and registernames when info->mach changes.
1187
1188 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1189
1190         PR 25377
1191         * z80-dis.c (suffix): Use .db instruction to generate double
1192         prefix.
1193
1194 2020-01-14  Alan Modra  <amodra@gmail.com>
1195
1196         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1197         values to unsigned before shifting.
1198
1199 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1200
1201         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1202         flow instructions.
1203         (print_insn_thumb16, print_insn_thumb32): Likewise.
1204         (print_insn): Initialize the insn info.
1205         * i386-dis.c (print_insn): Initialize the insn info fields, and
1206         detect jumps.
1207
1208 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1209
1210         * arc-opc.c (C_NE): Make it required.
1211
1212 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1213
1214         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1215         reserved register name.
1216
1217 2020-01-13  Alan Modra  <amodra@gmail.com>
1218
1219         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1220         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1221
1222 2020-01-13  Alan Modra  <amodra@gmail.com>
1223
1224         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1225         result of wasm_read_leb128 in a uint64_t and check that bits
1226         are not lost when copying to other locals.  Use uint32_t for
1227         most locals.  Use PRId64 when printing int64_t.
1228
1229 2020-01-13  Alan Modra  <amodra@gmail.com>
1230
1231         * score-dis.c: Formatting.
1232         * score7-dis.c: Formatting.
1233
1234 2020-01-13  Alan Modra  <amodra@gmail.com>
1235
1236         * score-dis.c (print_insn_score48): Use unsigned variables for
1237         unsigned values.  Don't left shift negative values.
1238         (print_insn_score32): Likewise.
1239         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1240
1241 2020-01-13  Alan Modra  <amodra@gmail.com>
1242
1243         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1244
1245 2020-01-13  Alan Modra  <amodra@gmail.com>
1246
1247         * fr30-ibld.c: Regenerate.
1248
1249 2020-01-13  Alan Modra  <amodra@gmail.com>
1250
1251         * xgate-dis.c (print_insn): Don't left shift signed value.
1252         (ripBits): Formatting, use 1u.
1253
1254 2020-01-10  Alan Modra  <amodra@gmail.com>
1255
1256         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1257         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1258
1259 2020-01-10  Alan Modra  <amodra@gmail.com>
1260
1261         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1262         and XRREG value earlier to avoid a shift with negative exponent.
1263         * m10200-dis.c (disassemble): Similarly.
1264
1265 2020-01-09  Nick Clifton  <nickc@redhat.com>
1266
1267         PR 25224
1268         * z80-dis.c (ld_ii_ii): Use correct cast.
1269
1270 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1271
1272         PR 25224
1273         * z80-dis.c (ld_ii_ii): Use character constant when checking
1274         opcode byte value.
1275
1276 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1277
1278         * i386-dis.c (SEP_Fixup): New.
1279         (SEP): Define.
1280         (dis386_twobyte): Use it for sysenter/sysexit.
1281         (enum x86_64_isa): Change amd64 enumerator to value 1.
1282         (OP_J): Compare isa64 against intel64 instead of amd64.
1283         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1284         forms.
1285         * i386-tbl.h: Re-generate.
1286
1287 2020-01-08  Alan Modra  <amodra@gmail.com>
1288
1289         * z8k-dis.c: Include libiberty.h
1290         (instr_data_s): Make max_fetched unsigned.
1291         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1292         Don't exceed byte_info bounds.
1293         (output_instr): Make num_bytes unsigned.
1294         (unpack_instr): Likewise for nibl_count and loop.
1295         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1296         idx unsigned.
1297         * z8k-opc.h: Regenerate.
1298
1299 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1300
1301         * arc-tbl.h (llock): Use 'LLOCK' as class.
1302         (llockd): Likewise.
1303         (scond): Use 'SCOND' as class.
1304         (scondd): Likewise.
1305         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1306         (scondd): Likewise.
1307
1308 2020-01-06  Alan Modra  <amodra@gmail.com>
1309
1310         * m32c-ibld.c: Regenerate.
1311
1312 2020-01-06  Alan Modra  <amodra@gmail.com>
1313
1314         PR 25344
1315         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1316         Peek at next byte to prevent recursion on repeated prefix bytes.
1317         Ensure uninitialised "mybuf" is not accessed.
1318         (print_insn_z80): Don't zero n_fetch and n_used here,..
1319         (print_insn_z80_buf): ..do it here instead.
1320
1321 2020-01-04  Alan Modra  <amodra@gmail.com>
1322
1323         * m32r-ibld.c: Regenerate.
1324
1325 2020-01-04  Alan Modra  <amodra@gmail.com>
1326
1327         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1328
1329 2020-01-04  Alan Modra  <amodra@gmail.com>
1330
1331         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1332
1333 2020-01-04  Alan Modra  <amodra@gmail.com>
1334
1335         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1336
1337 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1338
1339         * aarch64-tbl.h (aarch64_opcode_table): Use
1340         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1341
1342 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1343
1344         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1345         forms of SUDOT and USDOT.
1346
1347 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1348
1349         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1350         uzip{1,2}.
1351         * opcodes/aarch64-dis-2.c: Re-generate.
1352
1353 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1354
1355         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1356         FMMLA encoding.
1357         * opcodes/aarch64-dis-2.c: Re-generate.
1358
1359 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1360
1361         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1362
1363 2020-01-01  Alan Modra  <amodra@gmail.com>
1364
1365         Update year range in copyright notice of all files.
1366
1367 For older changes see ChangeLog-2019
1368 \f
1369 Copyright (C) 2020 Free Software Foundation, Inc.
1370
1371 Copying and distribution of this file, with or without modification,
1372 are permitted in any medium without royalty provided the copyright
1373 notice and this notice are preserved.
1374
1375 Local Variables:
1376 mode: change-log
1377 left-margin: 8
1378 fill-column: 74
1379 version-control: never
1380 End: