opcodes/ChangeLog

   1 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
   2
   3         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
   4         ISA-specific "break" encoding.
   5
   6 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
   7
   8         * arm-opc.h: Fix typo in comment.
   9
  10 2004-07-11  Andreas Schwab  <schwab@suse.de>
  11
  12         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
  13
  14 2004-07-09  Andreas Schwab  <schwab@suse.de>
  15
  16         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
  17
  18 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
  19
  20         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
  21         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
  22         (crx-dis.lo): New target.
  23         (crx-opc.lo): Likewise.
  24         * Makefile.in: Regenerate.
  25         * configure.in: Handle bfd_crx_arch.
  26         * configure: Regenerate.
  27         * crx-dis.c: New file.
  28         * crx-opc.c: New file.
  29         * disassemble.c (ARCH_crx): Define.
  30         (disassembler): Handle ARCH_crx.
  31
  32 2004-06-29  James E Wilson  <wilson@specifixinc.com>
  33
  34         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
  35         * ia64-asmtab.c: Regnerate.
  36
  37 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
  38
  39         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
  40         (extract_fxm): Don't test dialect.
  41         (XFXFXM_MASK): Include the power4 bit.
  42         (XFXM): Add p4 param.
  43         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
  44
  45 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
  46
  47         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
  48         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
  49
  50 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
  51
  52         * ppc-opc.c (BH, XLBH_MASK): Define.
  53         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
  54
  55 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
  56
  57         * i386-dis.c (x_mode): Comment.
  58         (two_source_ops): File scope.
  59         (float_mem): Correct fisttpll and fistpll.
  60         (float_mem_mode): New table.
  61         (dofloat): Use it.
  62         (OP_E): Correct intel mode PTR output.
  63         (ptr_reg): Use open_char and close_char.
  64         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
  65         operands.  Set two_source_ops.
  66
  67 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
  68
  69         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
  70         instead of _raw_size.
  71
  72 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
  73
  74         * ia64-gen.c (in_iclass): Handle more postinc st
  75         and ld variants.
  76         * ia64-asmtab.c: Rebuilt.
  77
  78 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
  79
  80         * s390-opc.txt: Correct architecture mask for some opcodes.
  81         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
  82         in the esa mode as well.
  83
  84 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
  85
  86         * sh-dis.c (target_arch): Make unsigned.
  87         (print_insn_sh): Replace (most of) switch with a call to
  88         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
  89         * sh-opc.h: Redefine architecture flags values.
  90         Add sh3-nommu architecture.
  91         Reorganise <arch>_up macros so they make more visual sense.
  92         (SH_MERGE_ARCH_SET): Define new macro.
  93         (SH_VALID_BASE_ARCH_SET): Likewise.
  94         (SH_VALID_MMU_ARCH_SET): Likewise.
  95         (SH_VALID_CO_ARCH_SET): Likewise.
  96         (SH_VALID_ARCH_SET): Likewise.
  97         (SH_MERGE_ARCH_SET_VALID): Likewise.
  98         (SH_ARCH_SET_HAS_FPU): Likewise.
  99         (SH_ARCH_SET_HAS_DSP): Likewise.
 100         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 101         (sh_get_arch_from_bfd_mach): Add prototype.
 102         (sh_get_arch_up_from_bfd_mach): Likewise.
 103         (sh_get_bfd_mach_from_arch_set): Likewise.
 104         (sh_merge_bfd_arc): Likewise.
 105
 106 2004-05-24  Peter Barada  <peter@the-baradas.com>
 107
 108         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 109         into new match_insn_m68k function.  Loop over canidate
 110         matches and select first that completely matches.
 111         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 112         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 113         to verify addressing for MAC/EMAC.
 114         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 115         reigster halves since 'fpu' and 'spl' look misleading.
 116         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 117         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 118         first, tighten up match masks.
 119         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 120         'size' from special case code in print_insn_m68k to
 121         determine decode size of insns.
 122
 123 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 124
 125         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 126         well as when -mpower4.
 127
 128 2004-05-13  Nick Clifton  <nickc@redhat.com>
 129
 130         * po/fr.po: Updated French translation.
 131
 132 2004-05-05  Peter Barada  <peter@the-baradas.com>
 133
 134         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 135         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 136         * m68k-op.c: Switch from ColdFire chips to core variants.
 137
 138 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 139
 140         PR 147.
 141         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 142
 143 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 144
 145         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 146         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 147
 148 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 149
 150         * sh-dis.c (print_insn_sh): Print the value in constant pool
 151         as a symbol if it looks like a symbol.
 152
 153 2004-04-22  Peter Barada <peter@the-baradas.com>
 154
 155         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 156         appropriate ColdFire architectures.
 157         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 158         mask addressing.
 159         Add EMAC instructions, fix MAC instructions. Remove
 160         macmw/macml/msacmw/msacml instructions since mask addressing now
 161         supported.
 162
 163 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 164
 165         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 166         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 167         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 168         macro.  Adjust all users.
 169
 170 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 171
 172         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 173         separately.
 174
 175 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 176
 177         * m32r-asm.c: Regenerate.
 178
 179 2004-03-29  Stan Shebs  <shebs@apple.com>
 180
 181         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 182         used.
 183
 184 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 185
 186         * aclocal.m4: Regenerate.
 187         * config.in: Regenerate.
 188         * configure: Regenerate.
 189         * po/POTFILES.in: Regenerate.
 190         * po/opcodes.pot: Regenerate.
 191
 192 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 193
 194         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 195         PPC_OPERANDS_GPR_0.
 196         * ppc-opc.c (RA0): Define.
 197         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 198         (RAOPT): Rename from RAO.  Update all uses.
 199         (powerpc_opcodes): Use RA0 as appropriate.
 200
 201 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 202
 203         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 204
 205 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 206
 207         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 208
 209 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 210
 211         * i386-dis.c (GRPPLOCK): Delete.
 212         (grps): Delete GRPPLOCK entry.
 213
 214 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 215
 216         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 217         (M, Mp): Use OP_M.
 218         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 219         (GRPPADLCK): Define.
 220         (dis386): Use NOP_Fixup on "nop".
 221         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 222         (twobyte_has_modrm): Set for 0xa7.
 223         (padlock_table): Delete.  Move to..
 224         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 225         and clflush.
 226         (print_insn): Revert PADLOCK_SPECIAL code.
 227         (OP_E): Delete sfence, lfence, mfence checks.
 228
 229 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 230
 231         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 232         (INVLPG_Fixup): New function.
 233         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 234
 235 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 236
 237         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 238         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 239         (padlock_table): New struct with PadLock instructions.
 240         (print_insn): Handle PADLOCK_SPECIAL.
 241
 242 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 243
 244         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 245         (OP_E): Twiddle clflush to sfence here.
 246
 247 2004-03-08  Nick Clifton  <nickc@redhat.com>
 248
 249         * po/de.po: Updated German translation.
 250
 251 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 252
 253         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 254         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 255         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 256         accordingly.
 257
 258 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 259
 260         * frv-asm.c: Regenerate.
 261         * frv-desc.c: Regenerate.
 262         * frv-desc.h: Regenerate.
 263         * frv-dis.c: Regenerate.
 264         * frv-ibld.c: Regenerate.
 265         * frv-opc.c: Regenerate.
 266         * frv-opc.h: Regenerate.
 267
 268 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 269
 270         * frv-desc.c, frv-opc.c: Regenerate.
 271
 272 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 273
 274         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 275
 276 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 277
 278         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 279         Also correct mistake in the comment.
 280
 281 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 282
 283         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 284         ensure that double registers have even numbers.
 285         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 286         that reserved instruction 0xfffd does not decode the same
 287         as 0xfdfd (ftrv).
 288         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 289         REG_N refers to a double register.
 290         Add REG_N_B01 nibble type and use it instead of REG_NM
 291         in ftrv.
 292         Adjust the bit patterns in a few comments.
 293
 294 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 295
 296         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 297
 298 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 299
 300         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 301
 302 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 303
 304         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 305
 306 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 307
 308         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 309         mtivor32, mtivor33, mtivor34.
 310
 311 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 312
 313         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 314
 315 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 316
 317         * arm-opc.h Maverick accumulator register opcode fixes.
 318
 319 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 320
 321         * m32r-dis.c: Regenerate.
 322
 323 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 324
 325         * sh-opc.h (sh_table): "fsrra", not "fssra".
 326
 327 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 328
 329         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 330         contraints.
 331
 332 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 333
 334         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 335
 336 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 337
 338         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 339         1.  Don't print scale factor on AT&T mode when index missing.
 340
 341 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 342
 343         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 344         when loaded into XR registers.
 345
 346 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 347
 348         * frv-desc.h: Regenerate.
 349         * frv-desc.c: Regenerate.
 350         * frv-opc.c: Regenerate.
 351
 352 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 353
 354         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 355
 356 2004-01-09  Paul Brook  <paul@codesourcery.com>
 357
 358         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 359         specific opcodes.
 360
 361 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 362
 363         * Makefile.am (libopcodes_la_DEPENDENCIES)
 364         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 365         comment about the problem.
 366         * Makefile.in: Regenerate.
 367
 368 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 369
 370         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 371         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 372         cut&paste errors in shifting/truncating numerical operands.
 373         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 374         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 375         (parse_uslo16): Likewise.
 376         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 377         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 378         (parse_s12): Likewise.
 379         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 380         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 381         (parse_uslo16): Likewise.
 382         (parse_uhi16): Parse gothi and gotfuncdeschi.
 383         (parse_d12): Parse got12 and gotfuncdesc12.
 384         (parse_s12): Likewise.
 385
 386 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 387
 388         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 389         instruction which looks similar to an 'rla' instruction.
 390
 391 For older changes see ChangeLog-0203
 392 \f
 393 Local Variables:
 394 mode: change-log
 395 left-margin: 8
 396 fill-column: 74
 397 version-control: never
 398 End: