opcodes/ChangeLog

   1 2021-04-01  Alan Modra  <amodra@gmail.com>
   2
   3         PR 27675
   4         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
   5
   6 2021-03-31  Alan Modra  <amodra@gmail.com>
   7
   8         * sysdep.h (POISON_BFD_BOOLEAN): Define.
   9         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
  10         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
  11         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
  12         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
  13         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
  14         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
  15         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
  16         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
  17         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
  18         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
  19         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
  20         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
  21         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
  22         and TRUE with true throughout.
  23
  24 2021-03-31  Alan Modra  <amodra@gmail.com>
  25
  26         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
  27         * aarch64-dis.h: Likewise.
  28         * aarch64-opc.c: Likewise.
  29         * avr-dis.c: Likewise.
  30         * csky-dis.c: Likewise.
  31         * nds32-asm.c: Likewise.
  32         * nds32-dis.c: Likewise.
  33         * nfp-dis.c: Likewise.
  34         * riscv-dis.c: Likewise.
  35         * s12z-dis.c: Likewise.
  36         * wasm32-dis.c: Likewise.
  37
  38 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  39
  40         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
  41         (i386_seg_prefixes): New.
  42         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
  43         (i386_seg_prefixes): Declare.
  44
  45 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
  48
  49 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
  52         * i386-reg.tbl (st): Move down.
  53         (st(0)): Delete. Extend comment.
  54         * i386-tbl.h: Re-generate.
  55
  56 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
  59         (cmpsd): Move next to cmps.
  60         (movsd): Move next to movs.
  61         (cmpxchg16b): Move to separate section.
  62         (fisttp, fisttpll): Likewise.
  63         (monitor, mwait): Likewise.
  64         * i386-tbl.h: Re-generate.
  65
  66 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl (psadbw): Add <sse2:comm>.
  69         (vpsadbw): Add C.
  70         * i386-tbl.h: Re-generate.
  71
  72 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
  75         pclmul, gfni): New templates. Use them wherever possible. Move
  76         SSE4.1 pextrw into respective section.
  77         * i386-tbl.h: Re-generate.
  78
  79 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
  82         strtoull(). Bump upper loop bound. Widen masks. Sanity check
  83         "length".
  84         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
  85         Convert all of their uses to representation in opcode.
  86
  87 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  88
  89         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
  90         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
  91         value of None. Shrink operands to 3 bits.
  92
  93 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  94
  95         * i386-gen.c (process_i386_opcode_modifier): New parameter
  96         "space".
  97         (output_i386_opcode): New local variable "space". Adjust
  98         process_i386_opcode_modifier() invocation.
  99         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 100         invocation.
 101         * i386-tbl.h: Re-generate.
 102
 103 2021-03-29  Alan Modra  <amodra@gmail.com>
 104
 105         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 106         (fp_qualifier_p, get_data_pattern): Likewise.
 107         (aarch64_get_operand_modifier_from_value): Likewise.
 108         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 109         (operand_variant_qualifier_p): Likewise.
 110         (qualifier_value_in_range_constraint_p): Likewise.
 111         (aarch64_get_qualifier_esize): Likewise.
 112         (aarch64_get_qualifier_nelem): Likewise.
 113         (aarch64_get_qualifier_standard_value): Likewise.
 114         (get_lower_bound, get_upper_bound): Likewise.
 115         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 116         (aarch64_print_operand): Likewise.
 117         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 118         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 119         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 120         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 121         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 122         (print_insn_tic6x): Likewise.
 123
 124 2021-03-29  Alan Modra  <amodra@gmail.com>
 125
 126         * arc-dis.c (extract_operand_value): Correct NULL cast.
 127         * frv-opc.h: Regenerate.
 128
 129 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 132         MMX form.
 133         * i386-tbl.h: Re-generate.
 134
 135 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 136
 137         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 138         immediate in br.n instruction.
 139
 140 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-dis.c (XMGatherD, VexGatherD): New.
 143         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 144         (print_insn): Check masking for S/G insns.
 145         (OP_E_memory): New local variable check_gather. Extend mandatory
 146         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 147         Extend check for disallowed 16-bit addressing.
 148         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 149         if()s to switch(). Check register conflicts for (VEX-encoded)
 150         gathers. Drop no longer reachable cases.
 151         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 152         vgatherdp*.
 153
 154 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 157         zeroing-masking without masking.
 158
 159 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 162         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 163         single-operand forms as deprecated.
 164         * i386-tbl.h: Re-generate.
 165
 166 2021-03-25  Alan Modra  <amodra@gmail.com>
 167
 168         PR 27647
 169         * ppc-opc.c (XLOCB_MASK): Delete.
 170         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 171         XLBH_MASK.
 172         (powerpc_opcodes): Accept a BH field on all extended forms of
 173         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 174
 175 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-gen.c (output_i386_opcode): Drop processing of
 178         opcode_length. Calculate length from base_opcode. Adjust prefix
 179         encoding determination.
 180         (process_i386_opcodes): Drop output of fake opcode_length.
 181         * i386-opc.h (struct insn_template): Drop opcode_length field.
 182         * i386-opc.tbl: Drop opcode length field from all templates.
 183         * i386-tbl.h: Re-generate.
 184
 185 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 188         parameter "prefix". Drop local variable "regular_encoding".
 189         Record prefix setting / check for consistency.
 190         (output_i386_opcode): Parse opcode_length and base_opcode
 191         earlier. Derive prefix encoding. Drop no longer applicable
 192         consistency checking. Adjust process_i386_opcode_modifier()
 193         invocation.
 194         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 195         invocation.
 196         * i386-tbl.h: Re-generate.
 197
 198 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 199
 200         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 201         check.
 202         * i386-opc.h (Prefix_*): Move #define-s.
 203         * i386-opc.tbl: Move pseudo prefix enumerator values to
 204         extension opcode field. Introduce pseudopfx template.
 205         * i386-tbl.h: Re-generate.
 206
 207 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 210         comment.
 211         * i386-tbl.h: Re-generate.
 212
 213 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.h (struct insn_template): Move cpu_flags field past
 216         opcode_modifier one.
 217         * i386-tbl.h: Re-generate.
 218
 219 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 222         * i386-opc.h (OpcodeSpace): New enumerator.
 223         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 224         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 225         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 226         (struct i386_opcode_modifier): New field opcodespace. Shrink
 227         opcodeprefix field.
 228         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 229         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 230         OpcodePrefix uses.
 231         * i386-tbl.h: Re-generate.
 232
 233 2021-03-22  Martin Liska  <mliska@suse.cz>
 234
 235         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 236         * arc-dis.c (parse_option): Likewise.
 237         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 238         * cris-dis.c (print_with_operands): Likewise.
 239         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 240         * i386-dis.c (print_insn): Likewise.
 241         * ia64-gen.c (fetch_insn_class): Likewise.
 242         (parse_resource_users): Likewise.
 243         (in_iclass): Likewise.
 244         (lookup_specifier): Likewise.
 245         (insert_opcode_dependencies): Likewise.
 246         * mips-dis.c (parse_mips_ase_option): Likewise.
 247         (parse_mips_dis_option): Likewise.
 248         * s390-dis.c (disassemble_init_s390): Likewise.
 249         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 250
 251 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 252
 253         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 254
 255 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 256
 257         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 258         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 259
 260 2021-03-12  Alan Modra  <amodra@gmail.com>
 261
 262         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 263
 264 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-dis.c (OP_XMM): Re-order checks.
 267
 268 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 269
 270         * i386-dis.c (putop): Drop need_vex check when also checking
 271         vex.evex.
 272         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 273         checking vex.b.
 274
 275 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 278         checks. Move case label past broadcast check.
 279
 280 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 281
 282         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 283         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 284         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 285         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 286         EVEX_W_0F38C7_M_0_L_2): Delete.
 287         (REG_EVEX_0F38C7_M_0_L_2): New.
 288         (intel_operand_size): Handle VEX and EVEX the same for
 289         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 290         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 291         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 292         vex_vsib_q_w_d_mode uses.
 293         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 294         0F38A1, and 0F38A3 entries.
 295         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 296         entry.
 297         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 298         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 299         0F38A3 entries.
 300
 301 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 302
 303         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 304         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 305         MOD_VEX_0FXOP_09_12): Rename to ...
 306         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 307         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 308         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 309         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 310         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 311         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 312         (reg_table): Adjust comments.
 313         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 314         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 315         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 316         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 317         (vex_len_table): Adjust opcode 0A_12 entry.
 318         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 319         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 320         (rm_table): Move hreset entry.
 321
 322 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 323
 324         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 325         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 326         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 327         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 328         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 329         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 330         (get_valid_dis386): Also handle 512-bit vector length when
 331         vectoring into vex_len_table[].
 332         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 333         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 334         entries.
 335         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 336         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 337         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 338         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 339         entries.
 340
 341 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 342
 343         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 344         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 345         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 346         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 347         entries.
 348         * i386-dis-evex-len.h (evex_len_table): Likewise.
 349         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 350
 351 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 352
 353         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 354         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 355         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 356         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 357         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 358         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 359         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 360         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 361         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 362         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 363         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 364         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 365         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 366         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 367         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 368         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 369         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 370         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 371         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 372         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 373         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 374         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 375         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 376         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 377         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 378         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 379         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 380         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 381         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 382         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 383         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 384         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 385         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 386         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 387         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 388         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 389         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 390         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 391         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 392         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 393         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 394         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 395         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 396         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 397         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 398         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 399         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 400         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 401         EVEX_W_0F3A43_L_n): New.
 402         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 403         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 404         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 405         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 406         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 407         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 408         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 409         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 410         0F385B, 0F38C6, and 0F38C7 entries.
 411         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 412         0F38C6 and 0F38C7.
 413         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 414         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 415         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 416         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 417
 418 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 419
 420         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 421         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 422         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 423         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 424         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 425         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 426         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 427         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 428         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 429         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 430         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 431         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 432         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 433         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 434         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 435         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 436         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 437         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 438         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 439         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 440         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 441         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 442         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 443         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 444         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 445         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 446         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 447         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 448         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 449         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 450         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 451         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 452         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 453         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 454         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 455         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 456         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 457         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 458         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 459         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 460         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 461         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 462         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 463         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 464         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 465         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 466         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 467         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 468         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 469         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 470         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 471         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 472         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 473         VEX_W_0F99_P_2_LEN_0): Delete.
 474         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 475         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 476         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 477         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 478         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 479         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 480         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 481         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 482         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 483         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 484         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 485         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 486         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 487         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 488         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 489         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 490         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 491         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 492         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 493         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 494         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 495         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 496         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 497         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 498         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 499         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 500         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 501         (prefix_table): No longer link to vex_len_table[] for opcodes
 502         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 503         0F92, 0F93, 0F98, and 0F99.
 504         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 505         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 506         0F98, and 0F99.
 507         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 508         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 509         0F98, and 0F99.
 510         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 511         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 512         0F98, and 0F99.
 513         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 514         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 515         0F98, and 0F99.
 516
 517 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 518
 519         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 520         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 521         REG_VEX_0F73_M_0 respectively.
 522         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 523         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 524         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 525         MOD_VEX_0F73_REG_7): Delete.
 526         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 527         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 528         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 529         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 530         PREFIX_VEX_0F3AF0_L_0 respectively.
 531         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 532         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 533         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 534         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 535         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 536         VEX_LEN_0F38F7): New.
 537         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 538         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 539         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 540         0F38F3.
 541         (prefix_table): No longer link to vex_len_table[] for opcodes
 542         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 543         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 544         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 545         0F38F6, 0F38F7, and 0F3AF0.
 546         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 547         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 548         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 549         0F73.
 550
 551 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 552
 553         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 554         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 555         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 556         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 557         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 558         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 559         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 560         73.
 561         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 562         0F72, and 0F73.
 563         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 564         0F73.
 565
 566 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 567
 568         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 569         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 570         (reg_table): Don't link to mod_table[] where not needed. Add
 571         PREFIX_IGNORED to nop entries.
 572         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 573         (mod_table): Add nop entries next to prefetch ones. Drop
 574         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 575         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 576         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 577         PREFIX_OPCODE from endbr* entries.
 578         (get_valid_dis386): Also consider entry's name when zapping
 579         vindex.
 580         (print_insn): Handle PREFIX_IGNORED.
 581
 582 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 583
 584         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 585         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 586         element.
 587         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 588         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 589         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 590         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 591         (struct i386_opcode_modifier): Delete notrackprefixok,
 592         islockable, hleprefixok, and repprefixok fields. Add prefixok
 593         field.
 594         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 595         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 596         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 597         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 598         Replace HLEPrefixOk.
 599         * opcodes/i386-tbl.h: Re-generate.
 600
 601 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 602
 603         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 604         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 605         64-bit form.
 606         * opcodes/i386-tbl.h: Re-generate.
 607
 608 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 611         for {} instead of {0}. Don't look for '0'.
 612         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 613         size specifiers.
 614
 615 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 616
 617         PR 27158
 618         * riscv-dis.c (print_insn_args): Updated encoding macros.
 619         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 620         (match_c_addi16sp): Updated encoding macros.
 621         (match_c_lui): Likewise.
 622         (match_c_lui_with_hint): Likewise.
 623         (match_c_addi4spn): Likewise.
 624         (match_c_slli): Likewise.
 625         (match_slli_as_c_slli): Likewise.
 626         (match_c_slli64): Likewise.
 627         (match_srxi_as_c_srxi): Likewise.
 628         (riscv_insn_types): Added .insn css/cl/cs.
 629
 630 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 631
 632         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 633         (default_priv_spec): Updated type to riscv_spec_class.
 634         (parse_riscv_dis_option): Updated.
 635         * riscv-opc.c: Moved stuff and make the file tidy.
 636
 637 2021-02-17  Alan Modra  <amodra@gmail.com>
 638
 639         * wasm32-dis.c: Include limits.h.
 640         (CHAR_BIT): Provide backup define.
 641         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 642         Correct signed overflow checking.
 643
 644 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 645
 646         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 647         * i386-tbl.h: Re-generate.
 648
 649 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 652         Oword.
 653         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 654
 655 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 656
 657         * s390-mkopc.c (main): Accept arch14 as cpu string.
 658         * s390-opc.txt: Add new arch14 instructions.
 659
 660 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 661
 662         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 663         favour of LIBINTL.
 664         * configure: Regenerated.
 665
 666 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 667
 668         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 669         * tic54x-opc.c (regs): Rename to ...
 670         (tic54x_regs): ... this.
 671         (mmregs): Rename to ...
 672         (tic54x_mmregs): ... this.
 673         (condition_codes): Rename to ...
 674         (tic54x_condition_codes): ... this.
 675         (cc2_codes): Rename to ...
 676         (tic54x_cc2_codes): ... this.
 677         (cc3_codes): Rename to ...
 678         (tic54x_cc3_codes): ... this.
 679         (status_bits): Rename to ...
 680         (tic54x_status_bits): ... this.
 681         (misc_symbols): Rename to ...
 682         (tic54x_misc_symbols): ... this.
 683
 684 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 685
 686         * riscv-opc.c (MASK_RVB_IMM): Removed.
 687         (riscv_opcodes): Removed zb* instructions.
 688         (riscv_ext_version_table): Removed versions for zb*.
 689
 690 2021-01-26  Alan Modra  <amodra@gmail.com>
 691
 692         * i386-gen.c (parse_template): Ensure entire template_instance
 693         is initialised.
 694
 695 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 696
 697         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 698         (riscv_fpr_names_abi): Likewise.
 699         (riscv_opcodes): Likewise.
 700         (riscv_insn_types): Likewise.
 701
 702 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 703
 704         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 705
 706 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 707
 708         * riscv-dis.c: Comments tidy and improvement.
 709         * riscv-opc.c: Likewise.
 710
 711 2021-01-13  Alan Modra  <amodra@gmail.com>
 712
 713         * Makefile.in: Regenerate.
 714
 715 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 716
 717         PR binutils/26792
 718         * configure.ac: Use GNU_MAKE_JOBSERVER.
 719         * aclocal.m4: Regenerated.
 720         * configure: Likewise.
 721
 722 2021-01-12  Nick Clifton  <nickc@redhat.com>
 723
 724         * po/sr.po: Updated Serbian translation.
 725
 726 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 727
 728         PR ld/27173
 729         * configure: Regenerated.
 730
 731 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 732
 733         * aarch64-asm-2.c: Regenerate.
 734         * aarch64-dis-2.c: Likewise.
 735         * aarch64-opc-2.c: Likewise.
 736         * aarch64-opc.c (aarch64_print_operand):
 737         Delete handling of AARCH64_OPND_CSRE_CSR.
 738         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 739         (CSRE): Likewise.
 740         (_CSRE_INSN): Likewise.
 741         (aarch64_opcode_table): Delete csr.
 742
 743 2021-01-11  Nick Clifton  <nickc@redhat.com>
 744
 745         * po/de.po: Updated German translation.
 746         * po/fr.po: Updated French translation.
 747         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 748         * po/sv.po: Updated Swedish translation.
 749         * po/uk.po: Updated Ukranian translation.
 750
 751 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 752
 753         * configure: Regenerated.
 754
 755 2021-01-09  Nick Clifton  <nickc@redhat.com>
 756
 757         * configure: Regenerate.
 758         * po/opcodes.pot: Regenerate.
 759
 760 2021-01-09  Nick Clifton  <nickc@redhat.com>
 761
 762         * 2.36 release branch crated.
 763
 764 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 765
 766         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 767         (DW, (XRC_MASK): Define.
 768         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 769
 770 2021-01-09  Alan Modra  <amodra@gmail.com>
 771
 772         * configure: Regenerate.
 773
 774 2021-01-08  Nick Clifton  <nickc@redhat.com>
 775
 776         * po/sv.po: Updated Swedish translation.
 777
 778 2021-01-08  Nick Clifton  <nickc@redhat.com>
 779
 780         PR 27129
 781         * aarch64-dis.c (determine_disassembling_preference): Move call to
 782         aarch64_match_operands_constraint outside of the assertion.
 783         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 784         Replace with a return of FALSE.
 785
 786         PR 27139
 787         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 788         core system register.
 789
 790 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 791
 792         * configure: Regenerate.
 793
 794 2021-01-07  Nick Clifton  <nickc@redhat.com>
 795
 796         * po/fr.po: Updated French translation.
 797
 798 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 799
 800         * m68k-opc.c (chkl): Change minimum architecture requirement to
 801         m68020.
 802
 803 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 804
 805         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 806
 807 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 808             Jim Wilson  <jimw@sifive.com>
 809             Andrew Waterman  <andrew@sifive.com>
 810             Maxim Blinov  <maxim.blinov@embecosm.com>
 811             Kito Cheng  <kito.cheng@sifive.com>
 812             Nelson Chu  <nelson.chu@sifive.com>
 813
 814         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 815         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 816
 817 2021-01-01  Alan Modra  <amodra@gmail.com>
 818
 819         Update year range in copyright notice of all files.
 820
 821 For older changes see ChangeLog-2020
 822 \f
 823 Copyright (C) 2021 Free Software Foundation, Inc.
 824
 825 Copying and distribution of this file, with or without modification,
 826 are permitted in any medium without royalty provided the copyright
 827 notice and this notice are preserved.
 828
 829 Local Variables:
 830 mode: change-log
 831 left-margin: 8
 832 fill-column: 74
 833 version-control: never
 834 End: