opcodes/ChangeLog

   1 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): Add dfb.
   4         (thumb32_opcodes): Add dfb.
   5
   6 2020-06-08  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-opc.h (reg_entry): Const-qualify reg_name field.
   9
  10 2020-06-06  Alan Modra  <amodra@gmail.com>
  11
  12         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
  13
  14 2020-06-05  Alan Modra  <amodra@gmail.com>
  15
  16         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
  17         size is large enough.
  18
  19 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
  20
  21         * disassemble.c (disassemble_init_for_target): Set endian_code for
  22         bpf targets.
  23         * bpf-desc.c: Regenerate.
  24         * bpf-opc.c: Likewise.
  25         * bpf-dis.c: Likewise.
  26
  27 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
  28
  29         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
  30         (cgen_put_insn_value): Likewise.
  31         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
  32         * cgen-dis.in (print_insn): Likewise.
  33         * cgen-ibld.in (insert_1): Likewise.
  34         (insert_1): Likewise.
  35         (insert_insn_normal): Likewise.
  36         (extract_1): Likewise.
  37         * bpf-dis.c: Regenerate.
  38         * bpf-ibld.c: Likewise.
  39         * bpf-ibld.c: Likewise.
  40         * cgen-dis.in: Likewise.
  41         * cgen-ibld.in: Likewise.
  42         * cgen-opc.c: Likewise.
  43         * epiphany-dis.c: Likewise.
  44         * epiphany-ibld.c: Likewise.
  45         * fr30-dis.c: Likewise.
  46         * fr30-ibld.c: Likewise.
  47         * frv-dis.c: Likewise.
  48         * frv-ibld.c: Likewise.
  49         * ip2k-dis.c: Likewise.
  50         * ip2k-ibld.c: Likewise.
  51         * iq2000-dis.c: Likewise.
  52         * iq2000-ibld.c: Likewise.
  53         * lm32-dis.c: Likewise.
  54         * lm32-ibld.c: Likewise.
  55         * m32c-dis.c: Likewise.
  56         * m32c-ibld.c: Likewise.
  57         * m32r-dis.c: Likewise.
  58         * m32r-ibld.c: Likewise.
  59         * mep-dis.c: Likewise.
  60         * mep-ibld.c: Likewise.
  61         * mt-dis.c: Likewise.
  62         * mt-ibld.c: Likewise.
  63         * or1k-dis.c: Likewise.
  64         * or1k-ibld.c: Likewise.
  65         * xc16x-dis.c: Likewise.
  66         * xc16x-ibld.c: Likewise.
  67         * xstormy16-dis.c: Likewise.
  68         * xstormy16-ibld.c: Likewise.
  69
  70 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
  71
  72         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
  73         (print_insn_): Handle instruction endian.
  74         * bpf-dis.c: Regenerate.
  75         * bpf-desc.c: Regenerate.
  76         * epiphany-dis.c: Likewise.
  77         * epiphany-desc.c: Likewise.
  78         * fr30-dis.c: Likewise.
  79         * fr30-desc.c: Likewise.
  80         * frv-dis.c: Likewise.
  81         * frv-desc.c: Likewise.
  82         * ip2k-dis.c: Likewise.
  83         * ip2k-desc.c: Likewise.
  84         * iq2000-dis.c: Likewise.
  85         * iq2000-desc.c: Likewise.
  86         * lm32-dis.c: Likewise.
  87         * lm32-desc.c: Likewise.
  88         * m32c-dis.c: Likewise.
  89         * m32c-desc.c: Likewise.
  90         * m32r-dis.c: Likewise.
  91         * m32r-desc.c: Likewise.
  92         * mep-dis.c: Likewise.
  93         * mep-desc.c: Likewise.
  94         * mt-dis.c: Likewise.
  95         * mt-desc.c: Likewise.
  96         * or1k-dis.c: Likewise.
  97         * or1k-desc.c: Likewise.
  98         * xc16x-dis.c: Likewise.
  99         * xc16x-desc.c: Likewise.
 100         * xstormy16-dis.c: Likewise.
 101         * xstormy16-desc.c: Likewise.
 102
 103 2020-06-03  Nick Clifton  <nickc@redhat.com>
 104
 105         * po/sr.po: Updated Serbian translation.
 106
 107 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 108
 109         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 110         (riscv_get_priv_spec_class): Likewise.
 111
 112 2020-06-01  Alan Modra  <amodra@gmail.com>
 113
 114         * bpf-desc.c: Regenerate.
 115
 116 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 117             David Faust <david.faust@oracle.com>
 118
 119         * bpf-desc.c: Regenerate.
 120         * bpf-opc.h: Likewise.
 121         * bpf-opc.c: Likewise.
 122         * bpf-dis.c: Likewise.
 123
 124 2020-05-28  Alan Modra  <amodra@gmail.com>
 125
 126         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 127         values.
 128
 129 2020-05-28  Alan Modra  <amodra@gmail.com>
 130
 131         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 132         immediates.
 133         (print_insn_ns32k): Revert last change.
 134
 135 2020-05-28  Nick Clifton  <nickc@redhat.com>
 136
 137         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 138         static.
 139
 140 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 141
 142         Fix extraction of signed constants in nios2 disassembler (again).
 143
 144         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 145         extractions of signed fields.
 146
 147 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 148
 149         * s390-opc.txt: Relocate vector load/store instructions with
 150         additional alignment parameter and change architecture level
 151         constraint from z14 to z13.
 152
 153 2020-05-21  Alan Modra  <amodra@gmail.com>
 154
 155         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 156         * sparc-dis.c: Likewise.
 157         * tic4x-dis.c: Likewise.
 158         * xtensa-dis.c: Likewise.
 159         * bpf-desc.c: Regenerate.
 160         * epiphany-desc.c: Regenerate.
 161         * fr30-desc.c: Regenerate.
 162         * frv-desc.c: Regenerate.
 163         * ip2k-desc.c: Regenerate.
 164         * iq2000-desc.c: Regenerate.
 165         * lm32-desc.c: Regenerate.
 166         * m32c-desc.c: Regenerate.
 167         * m32r-desc.c: Regenerate.
 168         * mep-asm.c: Regenerate.
 169         * mep-desc.c: Regenerate.
 170         * mt-desc.c: Regenerate.
 171         * or1k-desc.c: Regenerate.
 172         * xc16x-desc.c: Regenerate.
 173         * xstormy16-desc.c: Regenerate.
 174
 175 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 176
 177         * riscv-opc.c (riscv_ext_version_table): The table used to store
 178         all information about the supported spec and the corresponding ISA
 179         versions.  Currently, only Zicsr is supported to verify the
 180         correctness of Z sub extension settings.  Others will be supported
 181         in the future patches.
 182         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 183         classes and the corresponding strings.
 184         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 185         spec class by giving a ISA spec string.
 186         * riscv-opc.c (struct priv_spec_t): New structure.
 187         (struct priv_spec_t priv_specs): List for all supported privilege spec
 188         classes and the corresponding strings.
 189         (riscv_get_priv_spec_class): New function.  Get the corresponding
 190         privilege spec class by giving a spec string.
 191         (riscv_get_priv_spec_name): New function.  Get the corresponding
 192         privilege spec string by giving a CSR version class.
 193         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 194         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 195         according to the chosen version.  Build a hash table riscv_csr_hash to
 196         store the valid CSR for the chosen pirv verison.  Dump the direct
 197         CSR address rather than it's name if it is invalid.
 198         (parse_riscv_dis_option_without_args): New function.  Parse the options
 199         without arguments.
 200         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 201         parse the options without arguments first, and then handle the options
 202         with arguments.  Add the new option -Mpriv-spec, which has argument.
 203         * riscv-dis.c (print_riscv_disassembler_options): Add description
 204         about the new OBJDUMP option.
 205
 206 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 207
 208         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 209         WC values on POWER10 sync, dcbf  and wait instructions.
 210         (insert_pl, extract_pl): New functions.
 211         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 212         (LS3): New , 3-bit L for sync.
 213         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 214         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 215         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 216         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 217         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 218         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 219         <wait>: Enable PL operand on POWER10.
 220         <dcbf>: Enable L3OPT operand on POWER10.
 221         <sync>: Enable SC2 operand on POWER10.
 222
 223 2020-05-19  Stafford Horne  <shorne@gmail.com>
 224
 225         PR 25184
 226         * or1k-asm.c: Regenerate.
 227         * or1k-desc.c: Regenerate.
 228         * or1k-desc.h: Regenerate.
 229         * or1k-dis.c: Regenerate.
 230         * or1k-ibld.c: Regenerate.
 231         * or1k-opc.c: Regenerate.
 232         * or1k-opc.h: Regenerate.
 233         * or1k-opinst.c: Regenerate.
 234
 235 2020-05-11  Alan Modra  <amodra@gmail.com>
 236
 237         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 238         xsmaxcqp, xsmincqp.
 239
 240 2020-05-11  Alan Modra  <amodra@gmail.com>
 241
 242         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 243         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 244
 245 2020-05-11  Alan Modra  <amodra@gmail.com>
 246
 247         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 248
 249 2020-05-11  Alan Modra  <amodra@gmail.com>
 250
 251         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 252         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 253
 254 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 255
 256         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 257         mnemonics.
 258
 259 2020-05-11  Alan Modra  <amodra@gmail.com>
 260
 261         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 262         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 263         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 264         (prefix_opcodes): Add xxeval.
 265
 266 2020-05-11  Alan Modra  <amodra@gmail.com>
 267
 268         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 269         xxgenpcvwm, xxgenpcvdm.
 270
 271 2020-05-11  Alan Modra  <amodra@gmail.com>
 272
 273         * ppc-opc.c (MP, VXVAM_MASK): Define.
 274         (VXVAPS_MASK): Use VXVA_MASK.
 275         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 276         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 277         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 278         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 279
 280 2020-05-11  Alan Modra  <amodra@gmail.com>
 281             Peter Bergner  <bergner@linux.ibm.com>
 282
 283         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 284         New functions.
 285         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 286         YMSK2, XA6a, XA6ap, XB6a entries.
 287         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 288         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 289         (PPCVSX4): Define.
 290         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 291         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 292         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 293         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 294         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 295         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 296         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 297         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 298         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 299         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 300         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 301         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 302         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 303         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 304
 305 2020-05-11  Alan Modra  <amodra@gmail.com>
 306
 307         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 308         (insert_xts, extract_xts): New functions.
 309         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 310         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 311         (VXRC_MASK, VXSH_MASK): Define.
 312         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 313         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 314         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 315         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 316         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 317         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 318         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 319
 320 2020-05-11  Alan Modra  <amodra@gmail.com>
 321
 322         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 323         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 324         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 325         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 326         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 327
 328 2020-05-11  Alan Modra  <amodra@gmail.com>
 329
 330         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 331         (XTP, DQXP, DQXP_MASK): Define.
 332         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 333         (prefix_opcodes): Add plxvp and pstxvp.
 334
 335 2020-05-11  Alan Modra  <amodra@gmail.com>
 336
 337         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 338         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 339         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 340
 341 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 342
 343         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 344
 345 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 346
 347         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 348         (L1OPT): Define.
 349         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 350
 351 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 352
 353         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 354
 355 2020-05-11  Alan Modra  <amodra@gmail.com>
 356
 357         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 358
 359 2020-05-11  Alan Modra  <amodra@gmail.com>
 360
 361         * ppc-dis.c (ppc_opts): Add "power10" entry.
 362         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 363         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 364
 365 2020-05-11  Nick Clifton  <nickc@redhat.com>
 366
 367         * po/fr.po: Updated French translation.
 368
 369 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 370
 371         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 372         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 373         (operand_general_constraint_met_p): validate
 374         AARCH64_OPND_UNDEFINED.
 375         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 376         for FLD_imm16_2.
 377         * aarch64-asm-2.c: Regenerated.
 378         * aarch64-dis-2.c: Regenerated.
 379         * aarch64-opc-2.c: Regenerated.
 380
 381 2020-04-29  Nick Clifton  <nickc@redhat.com>
 382
 383         PR 22699
 384         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 385         and SETRC insns.
 386
 387 2020-04-29  Nick Clifton  <nickc@redhat.com>
 388
 389         * po/sv.po: Updated Swedish translation.
 390
 391 2020-04-29  Nick Clifton  <nickc@redhat.com>
 392
 393         PR 22699
 394         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 395         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 396         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 397         IMM0_8U case.
 398
 399 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 400
 401         PR 25848
 402         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 403         cmpi only on m68020up and cpu32.
 404
 405 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 406
 407         * aarch64-asm.c (aarch64_ins_none): New.
 408         * aarch64-asm.h (ins_none): New declaration.
 409         * aarch64-dis.c (aarch64_ext_none): New.
 410         * aarch64-dis.h (ext_none): New declaration.
 411         * aarch64-opc.c (aarch64_print_operand): Update case for
 412         AARCH64_OPND_BARRIER_PSB.
 413         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 414         (AARCH64_OPERANDS): Update inserter/extracter for
 415         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 416         * aarch64-asm-2.c: Regenerated.
 417         * aarch64-dis-2.c: Regenerated.
 418         * aarch64-opc-2.c: Regenerated.
 419
 420 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 421
 422         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 423         (aarch64_feature_ras, RAS): Likewise.
 424         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 425         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 426         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 427         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 428         * aarch64-asm-2.c: Regenerated.
 429         * aarch64-dis-2.c: Regenerated.
 430         * aarch64-opc-2.c: Regenerated.
 431
 432 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 433
 434         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 435         (print_insn_neon): Support disassembly of conditional
 436         instructions.
 437
 438 2020-02-16  David Faust  <david.faust@oracle.com>
 439
 440         * bpf-desc.c: Regenerate.
 441         * bpf-desc.h: Likewise.
 442         * bpf-opc.c: Regenerate.
 443         * bpf-opc.h: Likewise.
 444
 445 2020-04-07  Lili Cui  <lili.cui@intel.com>
 446
 447         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 448         (prefix_table): New instructions (see prefixes above).
 449         (rm_table): Likewise
 450         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 451         CPU_ANY_TSXLDTRK_FLAGS.
 452         (cpu_flags): Add CpuTSXLDTRK.
 453         * i386-opc.h (enum): Add CpuTSXLDTRK.
 454         (i386_cpu_flags): Add cputsxldtrk.
 455         * i386-opc.tbl: Add XSUSPLDTRK insns.
 456         * i386-init.h: Regenerate.
 457         * i386-tbl.h: Likewise.
 458
 459 2020-04-02  Lili Cui  <lili.cui@intel.com>
 460
 461         * i386-dis.c (prefix_table): New instructions serialize.
 462         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 463         CPU_ANY_SERIALIZE_FLAGS.
 464         (cpu_flags): Add CpuSERIALIZE.
 465         * i386-opc.h (enum): Add CpuSERIALIZE.
 466         (i386_cpu_flags): Add cpuserialize.
 467         * i386-opc.tbl: Add SERIALIZE insns.
 468         * i386-init.h: Regenerate.
 469         * i386-tbl.h: Likewise.
 470
 471 2020-03-26  Alan Modra  <amodra@gmail.com>
 472
 473         * disassemble.h (opcodes_assert): Declare.
 474         (OPCODES_ASSERT): Define.
 475         * disassemble.c: Don't include assert.h.  Include opintl.h.
 476         (opcodes_assert): New function.
 477         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 478         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 479         calculate maxlen.  Omit insn decoding when insn length exceeds
 480         maxlen.  Exit from nibble loop when looking for E, before
 481         accessing next data byte.  Move processing of E outside loop.
 482         Replace tests of maxlen in loop with assertions.
 483
 484 2020-03-26  Alan Modra  <amodra@gmail.com>
 485
 486         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 487
 488 2020-03-25  Alan Modra  <amodra@gmail.com>
 489
 490         * z80-dis.c (suffix): Init mybuf.
 491
 492 2020-03-22  Alan Modra  <amodra@gmail.com>
 493
 494         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 495         successflly read from section.
 496
 497 2020-03-22  Alan Modra  <amodra@gmail.com>
 498
 499         * arc-dis.c (find_format): Use ISO C string concatenation rather
 500         than line continuation within a string.  Don't access needs_limm
 501         before testing opcode != NULL.
 502
 503 2020-03-22  Alan Modra  <amodra@gmail.com>
 504
 505         * ns32k-dis.c (print_insn_arg): Update comment.
 506         (print_insn_ns32k): Reduce size of index_offset array, and
 507         initialize, passing -1 to print_insn_arg for args that are not
 508         an index.  Don't exit arg loop early.  Abort on bad arg number.
 509
 510 2020-03-22  Alan Modra  <amodra@gmail.com>
 511
 512         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 513         * s12z-opc.c: Formatting.
 514         (operands_f): Return an int.
 515         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 516         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 517         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 518         (exg_sex_discrim): Likewise.
 519         (create_immediate_operand, create_bitfield_operand),
 520         (create_register_operand_with_size, create_register_all_operand),
 521         (create_register_all16_operand, create_simple_memory_operand),
 522         (create_memory_operand, create_memory_auto_operand): Don't
 523         segfault on malloc failure.
 524         (z_ext24_decode): Return an int status, negative on fail, zero
 525         on success.
 526         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 527         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 528         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 529         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 530         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 531         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 532         (loop_primitive_decode, shift_decode, psh_pul_decode),
 533         (bit_field_decode): Similarly.
 534         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 535         to return value, update callers.
 536         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 537         Don't segfault on NULL operand.
 538         (decode_operation): Return OP_INVALID on first fail.
 539         (decode_s12z): Check all reads, returning -1 on fail.
 540
 541 2020-03-20  Alan Modra  <amodra@gmail.com>
 542
 543         * metag-dis.c (print_insn_metag): Don't ignore status from
 544         read_memory_func.
 545
 546 2020-03-20  Alan Modra  <amodra@gmail.com>
 547
 548         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 549         Initialize parts of buffer not written when handling a possible
 550         2-byte insn at end of section.  Don't attempt decoding of such
 551         an insn by the 4-byte machinery.
 552
 553 2020-03-20  Alan Modra  <amodra@gmail.com>
 554
 555         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 556         partially filled buffer.  Prevent lookup of 4-byte insns when
 557         only VLE 2-byte insns are possible due to section size.  Print
 558         ".word" rather than ".long" for 2-byte leftovers.
 559
 560 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 561
 562         PR 25641
 563         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 564
 565 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-dis.c (X86_64_0D): Rename to ...
 568         (X86_64_0E): ... this.
 569
 570 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 571
 572         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 573         * Makefile.in: Regenerated.
 574
 575 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 578         3-operand pseudos.
 579         * i386-tbl.h: Re-generate.
 580
 581 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 584         vprot*, vpsha*, and vpshl*.
 585         * i386-tbl.h: Re-generate.
 586
 587 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 590         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 591         * i386-tbl.h: Re-generate.
 592
 593 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 594
 595         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 596         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 597         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 598         * i386-tbl.h: Re-generate.
 599
 600 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-gen.c (struct template_arg, struct template_instance,
 603         struct template_param, struct template, templates,
 604         parse_template, expand_templates): New.
 605         (process_i386_opcodes): Various local variables moved to
 606         expand_templates. Call parse_template and expand_templates.
 607         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 608         * i386-tbl.h: Re-generate.
 609
 610 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 613         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 614         register and memory source templates. Replace VexW= by VexW*
 615         where applicable.
 616         * i386-tbl.h: Re-generate.
 617
 618 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 619
 620         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 621         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 622         * i386-tbl.h: Re-generate.
 623
 624 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 625
 626         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 627         * i386-tbl.h: Re-generate.
 628
 629 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 632         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 633         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 634         VexW0 on SSE2AVX variants.
 635         (vmovq): Drop NoRex64 from XMM/XMM variants.
 636         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 637         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 638         applicable use VexW0.
 639         * i386-tbl.h: Re-generate.
 640
 641 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 644         * i386-opc.h (Rex64): Delete.
 645         (struct i386_opcode_modifier): Remove rex64 field.
 646         * i386-opc.tbl (crc32): Drop Rex64.
 647         Replace Rex64 with Size64 everywhere else.
 648         * i386-tbl.h: Re-generate.
 649
 650 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 651
 652         * i386-dis.c (OP_E_memory): Exclude recording of used address
 653         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 654         addressed memory operands for MPX insns.
 655
 656 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 657
 658         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 659         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 660         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 661         (ptwrite): Split into non-64-bit and 64-bit forms.
 662         * i386-tbl.h: Re-generate.
 663
 664 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 665
 666         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 667         template.
 668         * i386-tbl.h: Re-generate.
 669
 670 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 673         (prefix_table): Move vmmcall here. Add vmgexit.
 674         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 675         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 676         (cpu_flags): Add CpuSEV_ES entry.
 677         * i386-opc.h (CpuSEV_ES): New.
 678         (union i386_cpu_flags): Add cpusev_es field.
 679         * i386-opc.tbl (vmgexit): New.
 680         * i386-init.h, i386-tbl.h: Re-generate.
 681
 682 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 683
 684         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 685         with MnemonicSize.
 686         * i386-opc.h (IGNORESIZE): New.
 687         (DEFAULTSIZE): Likewise.
 688         (IgnoreSize): Removed.
 689         (DefaultSize): Likewise.
 690         (MnemonicSize): New.
 691         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 692         mnemonicsize.
 693         * i386-opc.tbl (IgnoreSize): New.
 694         (DefaultSize): Likewise.
 695         * i386-tbl.h: Regenerated.
 696
 697 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 698
 699         PR 25627
 700         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 701         instructions.
 702
 703 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         PR gas/25622
 706         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 707         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 708         * i386-tbl.h: Regenerated.
 709
 710 2020-02-26  Alan Modra  <amodra@gmail.com>
 711
 712         * aarch64-asm.c: Indent labels correctly.
 713         * aarch64-dis.c: Likewise.
 714         * aarch64-gen.c: Likewise.
 715         * aarch64-opc.c: Likewise.
 716         * alpha-dis.c: Likewise.
 717         * i386-dis.c: Likewise.
 718         * nds32-asm.c: Likewise.
 719         * nfp-dis.c: Likewise.
 720         * visium-dis.c: Likewise.
 721
 722 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 723
 724         * arc-regs.h (int_vector_base): Make it available for all ARC
 725         CPUs.
 726
 727 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 728
 729         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 730         changed.
 731
 732 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 733
 734         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 735         c.mv/c.li if rs1 is zero.
 736
 737 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 738
 739         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 740         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 741         CPU_POPCNT_FLAGS.
 742         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 743         * i386-opc.h (CpuABM): Removed.
 744         (CpuPOPCNT): New.
 745         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 746         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 747         popcnt.  Remove CpuABM from lzcnt.
 748         * i386-init.h: Regenerated.
 749         * i386-tbl.h: Likewise.
 750
 751 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 754         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 755         VexW1 instead of open-coding them.
 756         * i386-tbl.h: Re-generate.
 757
 758 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl (AddrPrefixOpReg): Define.
 761         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 762         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 763         templates. Drop NoRex64.
 764         * i386-tbl.h: Re-generate.
 765
 766 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 767
 768         PR gas/6518
 769         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 770         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 771         into Intel syntax instance (with Unpsecified) and AT&T one
 772         (without).
 773         (vcvtneps2bf16): Likewise, along with folding the two so far
 774         separate ones.
 775         * i386-tbl.h: Re-generate.
 776
 777 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 780         CPU_ANY_SSE4A_FLAGS.
 781
 782 2020-02-17  Alan Modra  <amodra@gmail.com>
 783
 784         * i386-gen.c (cpu_flag_init): Correct last change.
 785
 786 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 787
 788         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 789         CPU_ANY_SSE4_FLAGS.
 790
 791 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 792
 793         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 794         (movzx): Likewise.
 795
 796 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 797
 798         PR gas/25438
 799         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 800         destination for Cpu64-only variant.
 801         (movzx): Fold patterns.
 802         * i386-tbl.h: Re-generate.
 803
 804 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 807         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 808         CPU_ANY_SSE4_FLAGS entry.
 809         * i386-init.h: Re-generate.
 810
 811 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 812
 813         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 814         with Unspecified, making the present one AT&T syntax only.
 815         * i386-tbl.h: Re-generate.
 816
 817 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 820         * i386-tbl.h: Re-generate.
 821
 822 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 823
 824         PR gas/24546
 825         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 826         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 827         Amd64 and Intel64 templates.
 828         (call, jmp): Likewise for far indirect variants. Dro
 829         Unspecified.
 830         * i386-tbl.h: Re-generate.
 831
 832 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 835         * i386-opc.h (ShortForm): Delete.
 836         (struct i386_opcode_modifier): Remove shortform field.
 837         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 838         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 839         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 840         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 841         Drop ShortForm.
 842         * i386-tbl.h: Re-generate.
 843
 844 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 845
 846         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 847         fucompi): Drop ShortForm from operand-less templates.
 848         * i386-tbl.h: Re-generate.
 849
 850 2020-02-11  Alan Modra  <amodra@gmail.com>
 851
 852         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 853         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 854         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 855         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 856         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 857
 858 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 859
 860         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 861         (cde_opcodes): Add VCX* instructions.
 862
 863 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 864             Matthew Malcomson  <matthew.malcomson@arm.com>
 865
 866         * arm-dis.c (struct cdeopcode32): New.
 867         (CDE_OPCODE): New macro.
 868         (cde_opcodes): New disassembly table.
 869         (regnames): New option to table.
 870         (cde_coprocs): New global variable.
 871         (print_insn_cde): New
 872         (print_insn_thumb32): Use print_insn_cde.
 873         (parse_arm_disassembler_options): Parse coprocN args.
 874
 875 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         PR gas/25516
 878         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 879         with ISA64.
 880         * i386-opc.h (AMD64): Removed.
 881         (Intel64): Likewose.
 882         (AMD64): New.
 883         (INTEL64): Likewise.
 884         (INTEL64ONLY): Likewise.
 885         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 886         * i386-opc.tbl (Amd64): New.
 887         (Intel64): Likewise.
 888         (Intel64Only): Likewise.
 889         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 890         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 891         * i386-tbl.h: Regenerated.
 892
 893 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 894
 895         PR 25469
 896         * z80-dis.c: Add support for GBZ80 opcodes.
 897
 898 2020-02-04  Alan Modra  <amodra@gmail.com>
 899
 900         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 901
 902 2020-02-03  Alan Modra  <amodra@gmail.com>
 903
 904         * m32c-ibld.c: Regenerate.
 905
 906 2020-02-01  Alan Modra  <amodra@gmail.com>
 907
 908         * frv-ibld.c: Regenerate.
 909
 910 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 911
 912         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 913         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 914         (OP_E_memory): Replace xmm_mdq_mode case label by
 915         vex_scalar_w_dq_mode one.
 916         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 917
 918 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 921         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 922         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 923         (intel_operand_size): Drop vex_w_dq_mode case label.
 924
 925 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 926
 927         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 928         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 929
 930 2020-01-30  Alan Modra  <amodra@gmail.com>
 931
 932         * m32c-ibld.c: Regenerate.
 933
 934 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 935
 936         * bpf-opc.c: Regenerate.
 937
 938 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 941         (dis386): Use them to replace C2/C3 table entries.
 942         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 943         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 944         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 945         * i386-tbl.h: Re-generate.
 946
 947 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 948
 949         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 950         forms.
 951         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 952         DefaultSize.
 953         * i386-tbl.h: Re-generate.
 954
 955 2020-01-30  Alan Modra  <amodra@gmail.com>
 956
 957         * tic4x-dis.c (tic4x_dp): Make unsigned.
 958
 959 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 960             Jan Beulich  <jbeulich@suse.com>
 961
 962         PR binutils/25445
 963         * i386-dis.c (MOVSXD_Fixup): New function.
 964         (movsxd_mode): New enum.
 965         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 966         (intel_operand_size): Handle movsxd_mode.
 967         (OP_E_register): Likewise.
 968         (OP_G): Likewise.
 969         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 970         register on movsxd.  Add movsxd with 16-bit destination register
 971         for AMD64 and Intel64 ISAs.
 972         * i386-tbl.h: Regenerated.
 973
 974 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 975
 976         PR 25403
 977         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 978         * aarch64-asm-2.c: Regenerate
 979         * aarch64-dis-2.c: Likewise.
 980         * aarch64-opc-2.c: Likewise.
 981
 982 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl (sysret): Drop DefaultSize.
 985         * i386-tbl.h: Re-generate.
 986
 987 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 990         Dword.
 991         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 992         * i386-tbl.h: Re-generate.
 993
 994 2020-01-20  Nick Clifton  <nickc@redhat.com>
 995
 996         * po/de.po: Updated German translation.
 997         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 998         * po/uk.po: Updated Ukranian translation.
 999
1000 2020-01-20  Alan Modra  <amodra@gmail.com>
1001
1002         * hppa-dis.c (fput_const): Remove useless cast.
1003
1004 2020-01-20  Alan Modra  <amodra@gmail.com>
1005
1006         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1007
1008 2020-01-18  Nick Clifton  <nickc@redhat.com>
1009
1010         * configure: Regenerate.
1011         * po/opcodes.pot: Regenerate.
1012
1013 2020-01-18  Nick Clifton  <nickc@redhat.com>
1014
1015         Binutils 2.34 branch created.
1016
1017 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1018
1019         * opintl.h: Fix spelling error (seperate).
1020
1021 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1022
1023         * i386-opc.tbl: Add {vex} pseudo prefix.
1024         * i386-tbl.h: Regenerated.
1025
1026 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1027
1028         PR 25376
1029         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1030         (neon_opcodes): Likewise.
1031         (select_arm_features): Make sure we enable MVE bits when selecting
1032         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1033         any architecture.
1034
1035 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-opc.tbl: Drop stale comment from XOP section.
1038
1039 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1040
1041         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1042         (extractps): Add VexWIG to SSE2AVX forms.
1043         * i386-tbl.h: Re-generate.
1044
1045 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1046
1047         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1048         Size64 from and use VexW1 on SSE2AVX forms.
1049         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1050         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1051         * i386-tbl.h: Re-generate.
1052
1053 2020-01-15  Alan Modra  <amodra@gmail.com>
1054
1055         * tic4x-dis.c (tic4x_version): Make unsigned long.
1056         (optab, optab_special, registernames): New file scope vars.
1057         (tic4x_print_register): Set up registernames rather than
1058         malloc'd registertable.
1059         (tic4x_disassemble): Delete optable and optable_special.  Use
1060         optab and optab_special instead.  Throw away old optab,
1061         optab_special and registernames when info->mach changes.
1062
1063 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1064
1065         PR 25377
1066         * z80-dis.c (suffix): Use .db instruction to generate double
1067         prefix.
1068
1069 2020-01-14  Alan Modra  <amodra@gmail.com>
1070
1071         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1072         values to unsigned before shifting.
1073
1074 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1075
1076         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1077         flow instructions.
1078         (print_insn_thumb16, print_insn_thumb32): Likewise.
1079         (print_insn): Initialize the insn info.
1080         * i386-dis.c (print_insn): Initialize the insn info fields, and
1081         detect jumps.
1082
1083 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1084
1085         * arc-opc.c (C_NE): Make it required.
1086
1087 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1088
1089         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1090         reserved register name.
1091
1092 2020-01-13  Alan Modra  <amodra@gmail.com>
1093
1094         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1095         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1096
1097 2020-01-13  Alan Modra  <amodra@gmail.com>
1098
1099         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1100         result of wasm_read_leb128 in a uint64_t and check that bits
1101         are not lost when copying to other locals.  Use uint32_t for
1102         most locals.  Use PRId64 when printing int64_t.
1103
1104 2020-01-13  Alan Modra  <amodra@gmail.com>
1105
1106         * score-dis.c: Formatting.
1107         * score7-dis.c: Formatting.
1108
1109 2020-01-13  Alan Modra  <amodra@gmail.com>
1110
1111         * score-dis.c (print_insn_score48): Use unsigned variables for
1112         unsigned values.  Don't left shift negative values.
1113         (print_insn_score32): Likewise.
1114         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1115
1116 2020-01-13  Alan Modra  <amodra@gmail.com>
1117
1118         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1119
1120 2020-01-13  Alan Modra  <amodra@gmail.com>
1121
1122         * fr30-ibld.c: Regenerate.
1123
1124 2020-01-13  Alan Modra  <amodra@gmail.com>
1125
1126         * xgate-dis.c (print_insn): Don't left shift signed value.
1127         (ripBits): Formatting, use 1u.
1128
1129 2020-01-10  Alan Modra  <amodra@gmail.com>
1130
1131         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1132         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1133
1134 2020-01-10  Alan Modra  <amodra@gmail.com>
1135
1136         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1137         and XRREG value earlier to avoid a shift with negative exponent.
1138         * m10200-dis.c (disassemble): Similarly.
1139
1140 2020-01-09  Nick Clifton  <nickc@redhat.com>
1141
1142         PR 25224
1143         * z80-dis.c (ld_ii_ii): Use correct cast.
1144
1145 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1146
1147         PR 25224
1148         * z80-dis.c (ld_ii_ii): Use character constant when checking
1149         opcode byte value.
1150
1151 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-dis.c (SEP_Fixup): New.
1154         (SEP): Define.
1155         (dis386_twobyte): Use it for sysenter/sysexit.
1156         (enum x86_64_isa): Change amd64 enumerator to value 1.
1157         (OP_J): Compare isa64 against intel64 instead of amd64.
1158         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1159         forms.
1160         * i386-tbl.h: Re-generate.
1161
1162 2020-01-08  Alan Modra  <amodra@gmail.com>
1163
1164         * z8k-dis.c: Include libiberty.h
1165         (instr_data_s): Make max_fetched unsigned.
1166         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1167         Don't exceed byte_info bounds.
1168         (output_instr): Make num_bytes unsigned.
1169         (unpack_instr): Likewise for nibl_count and loop.
1170         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1171         idx unsigned.
1172         * z8k-opc.h: Regenerate.
1173
1174 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1175
1176         * arc-tbl.h (llock): Use 'LLOCK' as class.
1177         (llockd): Likewise.
1178         (scond): Use 'SCOND' as class.
1179         (scondd): Likewise.
1180         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1181         (scondd): Likewise.
1182
1183 2020-01-06  Alan Modra  <amodra@gmail.com>
1184
1185         * m32c-ibld.c: Regenerate.
1186
1187 2020-01-06  Alan Modra  <amodra@gmail.com>
1188
1189         PR 25344
1190         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1191         Peek at next byte to prevent recursion on repeated prefix bytes.
1192         Ensure uninitialised "mybuf" is not accessed.
1193         (print_insn_z80): Don't zero n_fetch and n_used here,..
1194         (print_insn_z80_buf): ..do it here instead.
1195
1196 2020-01-04  Alan Modra  <amodra@gmail.com>
1197
1198         * m32r-ibld.c: Regenerate.
1199
1200 2020-01-04  Alan Modra  <amodra@gmail.com>
1201
1202         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1203
1204 2020-01-04  Alan Modra  <amodra@gmail.com>
1205
1206         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1207
1208 2020-01-04  Alan Modra  <amodra@gmail.com>
1209
1210         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1211
1212 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1213
1214         * aarch64-tbl.h (aarch64_opcode_table): Use
1215         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1216
1217 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1218
1219         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1220         forms of SUDOT and USDOT.
1221
1222 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1223
1224         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1225         uzip{1,2}.
1226         * opcodes/aarch64-dis-2.c: Re-generate.
1227
1228 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1229
1230         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1231         FMMLA encoding.
1232         * opcodes/aarch64-dis-2.c: Re-generate.
1233
1234 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1235
1236         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1237
1238 2020-01-01  Alan Modra  <amodra@gmail.com>
1239
1240         Update year range in copyright notice of all files.
1241
1242 For older changes see ChangeLog-2019
1243 \f
1244 Copyright (C) 2020 Free Software Foundation, Inc.
1245
1246 Copying and distribution of this file, with or without modification,
1247 are permitted in any medium without royalty provided the copyright
1248 notice and this notice are preserved.
1249
1250 Local Variables:
1251 mode: change-log
1252 left-margin: 8
1253 fill-column: 74
1254 version-control: never
1255 End: