opcodes/ChangeLog

   1 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
   2
   3         * arc-regs.h (int_vector_base): Make it available for all ARC
   4         CPUs.
   5
   6 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
   7
   8         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
   9         changed.
  10
  11 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  12
  13         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  14         c.mv/c.li if rs1 is zero.
  15
  16 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  17
  18         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  19         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  20         CPU_POPCNT_FLAGS.
  21         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  22         * i386-opc.h (CpuABM): Removed.
  23         (CpuPOPCNT): New.
  24         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  25         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  26         popcnt.  Remove CpuABM from lzcnt.
  27         * i386-init.h: Regenerated.
  28         * i386-tbl.h: Likewise.
  29
  30 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  33         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  34         VexW1 instead of open-coding them.
  35         * i386-tbl.h: Re-generate.
  36
  37 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-opc.tbl (AddrPrefixOpReg): Define.
  40         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  41         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  42         templates. Drop NoRex64.
  43         * i386-tbl.h: Re-generate.
  44
  45 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  46
  47         PR gas/6518
  48         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  49         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  50         into Intel syntax instance (with Unpsecified) and AT&T one
  51         (without).
  52         (vcvtneps2bf16): Likewise, along with folding the two so far
  53         separate ones.
  54         * i386-tbl.h: Re-generate.
  55
  56 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  59         CPU_ANY_SSE4A_FLAGS.
  60
  61 2020-02-17  Alan Modra  <amodra@gmail.com>
  62
  63         * i386-gen.c (cpu_flag_init): Correct last change.
  64
  65 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  68         CPU_ANY_SSE4_FLAGS.
  69
  70 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  73         (movzx): Likewise.
  74
  75 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  76
  77         PR gas/25438
  78         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  79         destination for Cpu64-only variant.
  80         (movzx): Fold patterns.
  81         * i386-tbl.h: Re-generate.
  82
  83 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  84
  85         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  86         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  87         CPU_ANY_SSE4_FLAGS entry.
  88         * i386-init.h: Re-generate.
  89
  90 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  93         with Unspecified, making the present one AT&T syntax only.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  99         * i386-tbl.h: Re-generate.
 100
 101 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 102
 103         PR gas/24546
 104         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 105         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 106         Amd64 and Intel64 templates.
 107         (call, jmp): Likewise for far indirect variants. Dro
 108         Unspecified.
 109         * i386-tbl.h: Re-generate.
 110
 111 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 114         * i386-opc.h (ShortForm): Delete.
 115         (struct i386_opcode_modifier): Remove shortform field.
 116         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 117         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 118         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 119         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 120         Drop ShortForm.
 121         * i386-tbl.h: Re-generate.
 122
 123 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 126         fucompi): Drop ShortForm from operand-less templates.
 127         * i386-tbl.h: Re-generate.
 128
 129 2020-02-11  Alan Modra  <amodra@gmail.com>
 130
 131         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 132         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 133         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 134         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 135         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 136
 137 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 138
 139         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 140         (cde_opcodes): Add VCX* instructions.
 141
 142 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 143             Matthew Malcomson  <matthew.malcomson@arm.com>
 144
 145         * arm-dis.c (struct cdeopcode32): New.
 146         (CDE_OPCODE): New macro.
 147         (cde_opcodes): New disassembly table.
 148         (regnames): New option to table.
 149         (cde_coprocs): New global variable.
 150         (print_insn_cde): New
 151         (print_insn_thumb32): Use print_insn_cde.
 152         (parse_arm_disassembler_options): Parse coprocN args.
 153
 154 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 155
 156         PR gas/25516
 157         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 158         with ISA64.
 159         * i386-opc.h (AMD64): Removed.
 160         (Intel64): Likewose.
 161         (AMD64): New.
 162         (INTEL64): Likewise.
 163         (INTEL64ONLY): Likewise.
 164         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 165         * i386-opc.tbl (Amd64): New.
 166         (Intel64): Likewise.
 167         (Intel64Only): Likewise.
 168         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 169         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 170         * i386-tbl.h: Regenerated.
 171
 172 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 173
 174         PR 25469
 175         * z80-dis.c: Add support for GBZ80 opcodes.
 176
 177 2020-02-04  Alan Modra  <amodra@gmail.com>
 178
 179         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 180
 181 2020-02-03  Alan Modra  <amodra@gmail.com>
 182
 183         * m32c-ibld.c: Regenerate.
 184
 185 2020-02-01  Alan Modra  <amodra@gmail.com>
 186
 187         * frv-ibld.c: Regenerate.
 188
 189 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 192         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 193         (OP_E_memory): Replace xmm_mdq_mode case label by
 194         vex_scalar_w_dq_mode one.
 195         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 196
 197 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 200         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 201         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 202         (intel_operand_size): Drop vex_w_dq_mode case label.
 203
 204 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 205
 206         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 207         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 208
 209 2020-01-30  Alan Modra  <amodra@gmail.com>
 210
 211         * m32c-ibld.c: Regenerate.
 212
 213 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 214
 215         * bpf-opc.c: Regenerate.
 216
 217 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 218
 219         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 220         (dis386): Use them to replace C2/C3 table entries.
 221         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 222         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 223         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 224         * i386-tbl.h: Re-generate.
 225
 226 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 229         forms.
 230         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 231         DefaultSize.
 232         * i386-tbl.h: Re-generate.
 233
 234 2020-01-30  Alan Modra  <amodra@gmail.com>
 235
 236         * tic4x-dis.c (tic4x_dp): Make unsigned.
 237
 238 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 239             Jan Beulich  <jbeulich@suse.com>
 240
 241         PR binutils/25445
 242         * i386-dis.c (MOVSXD_Fixup): New function.
 243         (movsxd_mode): New enum.
 244         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 245         (intel_operand_size): Handle movsxd_mode.
 246         (OP_E_register): Likewise.
 247         (OP_G): Likewise.
 248         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 249         register on movsxd.  Add movsxd with 16-bit destination register
 250         for AMD64 and Intel64 ISAs.
 251         * i386-tbl.h: Regenerated.
 252
 253 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 254
 255         PR 25403
 256         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 257         * aarch64-asm-2.c: Regenerate
 258         * aarch64-dis-2.c: Likewise.
 259         * aarch64-opc-2.c: Likewise.
 260
 261 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-opc.tbl (sysret): Drop DefaultSize.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 269         Dword.
 270         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 271         * i386-tbl.h: Re-generate.
 272
 273 2020-01-20  Nick Clifton  <nickc@redhat.com>
 274
 275         * po/de.po: Updated German translation.
 276         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 277         * po/uk.po: Updated Ukranian translation.
 278
 279 2020-01-20  Alan Modra  <amodra@gmail.com>
 280
 281         * hppa-dis.c (fput_const): Remove useless cast.
 282
 283 2020-01-20  Alan Modra  <amodra@gmail.com>
 284
 285         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 286
 287 2020-01-18  Nick Clifton  <nickc@redhat.com>
 288
 289         * configure: Regenerate.
 290         * po/opcodes.pot: Regenerate.
 291
 292 2020-01-18  Nick Clifton  <nickc@redhat.com>
 293
 294         Binutils 2.34 branch created.
 295
 296 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 297
 298         * opintl.h: Fix spelling error (seperate).
 299
 300 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * i386-opc.tbl: Add {vex} pseudo prefix.
 303         * i386-tbl.h: Regenerated.
 304
 305 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 306
 307         PR 25376
 308         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 309         (neon_opcodes): Likewise.
 310         (select_arm_features): Make sure we enable MVE bits when selecting
 311         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 312         any architecture.
 313
 314 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl: Drop stale comment from XOP section.
 317
 318 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 319
 320         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 321         (extractps): Add VexWIG to SSE2AVX forms.
 322         * i386-tbl.h: Re-generate.
 323
 324 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 325
 326         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 327         Size64 from and use VexW1 on SSE2AVX forms.
 328         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 329         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 330         * i386-tbl.h: Re-generate.
 331
 332 2020-01-15  Alan Modra  <amodra@gmail.com>
 333
 334         * tic4x-dis.c (tic4x_version): Make unsigned long.
 335         (optab, optab_special, registernames): New file scope vars.
 336         (tic4x_print_register): Set up registernames rather than
 337         malloc'd registertable.
 338         (tic4x_disassemble): Delete optable and optable_special.  Use
 339         optab and optab_special instead.  Throw away old optab,
 340         optab_special and registernames when info->mach changes.
 341
 342 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 343
 344         PR 25377
 345         * z80-dis.c (suffix): Use .db instruction to generate double
 346         prefix.
 347
 348 2020-01-14  Alan Modra  <amodra@gmail.com>
 349
 350         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 351         values to unsigned before shifting.
 352
 353 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 354
 355         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 356         flow instructions.
 357         (print_insn_thumb16, print_insn_thumb32): Likewise.
 358         (print_insn): Initialize the insn info.
 359         * i386-dis.c (print_insn): Initialize the insn info fields, and
 360         detect jumps.
 361
 362 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 363
 364         * arc-opc.c (C_NE): Make it required.
 365
 366 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 367
 368         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 369         reserved register name.
 370
 371 2020-01-13  Alan Modra  <amodra@gmail.com>
 372
 373         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 374         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 375
 376 2020-01-13  Alan Modra  <amodra@gmail.com>
 377
 378         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 379         result of wasm_read_leb128 in a uint64_t and check that bits
 380         are not lost when copying to other locals.  Use uint32_t for
 381         most locals.  Use PRId64 when printing int64_t.
 382
 383 2020-01-13  Alan Modra  <amodra@gmail.com>
 384
 385         * score-dis.c: Formatting.
 386         * score7-dis.c: Formatting.
 387
 388 2020-01-13  Alan Modra  <amodra@gmail.com>
 389
 390         * score-dis.c (print_insn_score48): Use unsigned variables for
 391         unsigned values.  Don't left shift negative values.
 392         (print_insn_score32): Likewise.
 393         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 394
 395 2020-01-13  Alan Modra  <amodra@gmail.com>
 396
 397         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 398
 399 2020-01-13  Alan Modra  <amodra@gmail.com>
 400
 401         * fr30-ibld.c: Regenerate.
 402
 403 2020-01-13  Alan Modra  <amodra@gmail.com>
 404
 405         * xgate-dis.c (print_insn): Don't left shift signed value.
 406         (ripBits): Formatting, use 1u.
 407
 408 2020-01-10  Alan Modra  <amodra@gmail.com>
 409
 410         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 411         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 412
 413 2020-01-10  Alan Modra  <amodra@gmail.com>
 414
 415         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 416         and XRREG value earlier to avoid a shift with negative exponent.
 417         * m10200-dis.c (disassemble): Similarly.
 418
 419 2020-01-09  Nick Clifton  <nickc@redhat.com>
 420
 421         PR 25224
 422         * z80-dis.c (ld_ii_ii): Use correct cast.
 423
 424 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 425
 426         PR 25224
 427         * z80-dis.c (ld_ii_ii): Use character constant when checking
 428         opcode byte value.
 429
 430 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-dis.c (SEP_Fixup): New.
 433         (SEP): Define.
 434         (dis386_twobyte): Use it for sysenter/sysexit.
 435         (enum x86_64_isa): Change amd64 enumerator to value 1.
 436         (OP_J): Compare isa64 against intel64 instead of amd64.
 437         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 438         forms.
 439         * i386-tbl.h: Re-generate.
 440
 441 2020-01-08  Alan Modra  <amodra@gmail.com>
 442
 443         * z8k-dis.c: Include libiberty.h
 444         (instr_data_s): Make max_fetched unsigned.
 445         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 446         Don't exceed byte_info bounds.
 447         (output_instr): Make num_bytes unsigned.
 448         (unpack_instr): Likewise for nibl_count and loop.
 449         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 450         idx unsigned.
 451         * z8k-opc.h: Regenerate.
 452
 453 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 454
 455         * arc-tbl.h (llock): Use 'LLOCK' as class.
 456         (llockd): Likewise.
 457         (scond): Use 'SCOND' as class.
 458         (scondd): Likewise.
 459         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 460         (scondd): Likewise.
 461
 462 2020-01-06  Alan Modra  <amodra@gmail.com>
 463
 464         * m32c-ibld.c: Regenerate.
 465
 466 2020-01-06  Alan Modra  <amodra@gmail.com>
 467
 468         PR 25344
 469         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 470         Peek at next byte to prevent recursion on repeated prefix bytes.
 471         Ensure uninitialised "mybuf" is not accessed.
 472         (print_insn_z80): Don't zero n_fetch and n_used here,..
 473         (print_insn_z80_buf): ..do it here instead.
 474
 475 2020-01-04  Alan Modra  <amodra@gmail.com>
 476
 477         * m32r-ibld.c: Regenerate.
 478
 479 2020-01-04  Alan Modra  <amodra@gmail.com>
 480
 481         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 482
 483 2020-01-04  Alan Modra  <amodra@gmail.com>
 484
 485         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 486
 487 2020-01-04  Alan Modra  <amodra@gmail.com>
 488
 489         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 490
 491 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 492
 493         * aarch64-tbl.h (aarch64_opcode_table): Use
 494         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 495
 496 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 497
 498         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 499         forms of SUDOT and USDOT.
 500
 501 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 502
 503         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 504         uzip{1,2}.
 505         * opcodes/aarch64-dis-2.c: Re-generate.
 506
 507 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 508
 509         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 510         FMMLA encoding.
 511         * opcodes/aarch64-dis-2.c: Re-generate.
 512
 513 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 514
 515         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 516
 517 2020-01-01  Alan Modra  <amodra@gmail.com>
 518
 519         Update year range in copyright notice of all files.
 520
 521 For older changes see ChangeLog-2019
 522 \f
 523 Copyright (C) 2020 Free Software Foundation, Inc.
 524
 525 Copying and distribution of this file, with or without modification,
 526 are permitted in any medium without royalty provided the copyright
 527 notice and this notice are preserved.
 528
 529 Local Variables:
 530 mode: change-log
 531 left-margin: 8
 532 fill-column: 74
 533 version-control: never
 534 End: