1 2018-06-26 Nick Clifton <nickc@redhat.com>
3 * po/uk.po: Updated Ukranian translation.
4 * po/de.po: Updated German translation.
5 * po/pt_BR.po: Updated Brazilian Portuguese translation.
7 2018-06-26 Nick Clifton <nickc@redhat.com>
9 * nfp-dis.c: Fix spelling mistake.
11 2018-06-24 Nick Clifton <nickc@redhat.com>
13 * configure: Regenerate.
14 * po/opcodes.pot: Regenerate.
16 2018-06-24 Nick Clifton <nickc@redhat.com>
20 2018-06-19 Tamar Christina <tamar.christina@arm.com>
22 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
23 * aarch64-asm-2.c: Regenerate.
24 * aarch64-dis-2.c: Likewise.
26 2018-06-21 Maciej W. Rozycki <macro@mips.com>
28 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
29 `-M ginv' option description.
31 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
34 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
37 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
39 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
40 * configure.ac: Remove AC_PREREQ.
41 * Makefile.in: Re-generate.
42 * aclocal.m4: Re-generate.
43 * configure: Re-generate.
45 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
47 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
49 (parse_mips_ase_option): Handle -Mginv option.
50 (print_mips_disassembler_options): Document -Mginv.
51 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
53 (mips_opcodes): Define ginvi and ginvt.
55 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
56 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
58 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
59 * mips-opc.c (CRC, CRC64): New macros.
60 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
61 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
64 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
67 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
68 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
70 2018-06-06 Alan Modra <amodra@gmail.com>
72 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
73 setjmp. Move init for some other vars later too.
75 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
77 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
78 (dis_private): Add new fields for property section tracking.
79 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
80 (xtensa_instruction_fits): New functions.
81 (fetch_data): Bump minimal fetch size to 4.
82 (print_insn_xtensa): Make struct dis_private static.
83 Load and prepare property table on section change.
84 Don't disassemble literals. Don't disassemble instructions that
85 cross property table boundaries.
87 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
89 * configure: Regenerated.
91 2018-06-01 Jan Beulich <jbeulich@suse.com>
93 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
94 * i386-tbl.h: Re-generate.
96 2018-06-01 Jan Beulich <jbeulich@suse.com>
98 * i386-opc.tbl (sldt, str): Add NoRex64.
99 * i386-tbl.h: Re-generate.
101 2018-06-01 Jan Beulich <jbeulich@suse.com>
103 * i386-opc.tbl (invpcid): Add Oword.
104 * i386-tbl.h: Re-generate.
106 2018-06-01 Alan Modra <amodra@gmail.com>
108 * sysdep.h (_bfd_error_handler): Don't declare.
109 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
110 * rl78-decode.opc: Likewise.
111 * msp430-decode.c: Regenerate.
112 * rl78-decode.c: Regenerate.
114 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
116 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
117 * i386-init.h : Regenerated.
119 2018-05-25 Alan Modra <amodra@gmail.com>
121 * Makefile.in: Regenerate.
122 * po/POTFILES.in: Regenerate.
124 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
126 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
127 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
128 (insert_bab, extract_bab, insert_btab, extract_btab,
129 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
130 (BAT, BBA VBA RBS XB6S): Delete macros.
131 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
132 (BB, BD, RBX, XC6): Update for new macros.
133 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
134 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
135 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
136 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
138 2018-05-18 John Darrington <john@darrington.wattle.id.au>
140 * Makefile.am: Add support for s12z architecture.
141 * configure.ac: Likewise.
142 * disassemble.c: Likewise.
143 * disassemble.h: Likewise.
144 * Makefile.in: Regenerate.
145 * configure: Regenerate.
146 * s12z-dis.c: New file.
149 2018-05-18 Alan Modra <amodra@gmail.com>
151 * nfp-dis.c: Don't #include libbfd.h.
152 (init_nfp3200_priv): Use bfd_get_section_contents.
153 (nit_nfp6000_mecsr_sec): Likewise.
155 2018-05-17 Nick Clifton <nickc@redhat.com>
157 * po/zh_CN.po: Updated simplified Chinese translation.
159 2018-05-16 Tamar Christina <tamar.christina@arm.com>
162 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
163 * aarch64-dis-2.c: Regenerate.
165 2018-05-15 Tamar Christina <tamar.christina@arm.com>
168 * aarch64-asm.c (opintl.h): Include.
169 (aarch64_ins_sysreg): Enforce read/write constraints.
170 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
171 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
172 (F_REG_READ, F_REG_WRITE): New.
173 * aarch64-opc.c (aarch64_print_operand): Generate notes for
175 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
176 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
177 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
178 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
179 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
180 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
181 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
182 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
183 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
184 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
185 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
186 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
187 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
188 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
189 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
190 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
191 msr (F_SYS_WRITE), mrs (F_SYS_READ).
193 2018-05-15 Tamar Christina <tamar.christina@arm.com>
196 * aarch64-dis.c (no_notes: New.
197 (parse_aarch64_dis_option): Support notes.
198 (aarch64_decode_insn, print_operands): Likewise.
199 (print_aarch64_disassembler_options): Document notes.
200 * aarch64-opc.c (aarch64_print_operand): Support notes.
202 2018-05-15 Tamar Christina <tamar.christina@arm.com>
205 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
206 and take error struct.
207 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
208 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
209 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
210 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
211 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
212 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
213 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
214 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
215 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
216 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
217 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
218 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
219 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
220 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
221 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
222 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
223 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
224 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
225 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
226 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
227 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
228 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
229 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
230 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
231 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
232 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
233 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
234 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
235 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
236 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
237 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
238 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
239 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
240 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
241 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
242 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
243 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
244 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
245 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
246 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
247 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
248 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
249 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
250 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
251 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
252 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
253 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
254 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
255 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
256 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
257 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
258 (determine_disassembling_preference, aarch64_decode_insn,
259 print_insn_aarch64_word, print_insn_data): Take errors struct.
260 (print_insn_aarch64): Use errors.
261 * aarch64-asm-2.c: Regenerate.
262 * aarch64-dis-2.c: Regenerate.
263 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
264 boolean in aarch64_insert_operan.
265 (print_operand_extractor): Likewise.
266 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
268 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
270 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
272 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
274 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
276 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
278 * cr16-opc.c (cr16_instruction): Comment typo fix.
279 * hppa-dis.c (print_insn_hppa): Likewise.
281 2018-05-08 Jim Wilson <jimw@sifive.com>
283 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
284 (match_c_slli64, match_srxi_as_c_srxi): New.
285 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
286 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
287 <c.slli, c.srli, c.srai>: Use match_s_slli.
288 <c.slli64, c.srli64, c.srai64>: New.
290 2018-05-08 Alan Modra <amodra@gmail.com>
292 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
293 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
294 partition opcode space for index lookup.
296 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
298 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
299 <insn_length>: ...with this. Update usage.
300 Remove duplicate call to *info->memory_error_func.
302 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
303 H.J. Lu <hongjiu.lu@intel.com>
305 * i386-dis.c (Gva): New.
306 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
307 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
308 (prefix_table): New instructions (see prefix above).
309 (mod_table): New instructions (see prefix above).
310 (OP_G): Handle va_mode.
311 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
313 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
314 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
315 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
316 * i386-opc.tbl: Add movidir{i,64b}.
317 * i386-init.h: Regenerated.
318 * i386-tbl.h: Likewise.
320 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
322 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
324 * i386-opc.h (AddrPrefixOp0): Renamed to ...
325 (AddrPrefixOpReg): This.
326 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
327 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
329 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
331 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
332 (vle_num_opcodes): Likewise.
333 (spe2_num_opcodes): Likewise.
334 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
336 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
337 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
340 2018-05-01 Tamar Christina <tamar.christina@arm.com>
342 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
344 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
346 Makefile.am: Added nfp-dis.c.
347 configure.ac: Added bfd_nfp_arch.
348 disassemble.h: Added print_insn_nfp prototype.
349 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
350 nfp-dis.c: New, for NFP support.
351 po/POTFILES.in: Added nfp-dis.c to the list.
352 Makefile.in: Regenerate.
353 configure: Regenerate.
355 2018-04-26 Jan Beulich <jbeulich@suse.com>
357 * i386-opc.tbl: Fold various non-memory operand AVX512VL
358 templates into their base ones.
359 * i386-tlb.h: Re-generate.
361 2018-04-26 Jan Beulich <jbeulich@suse.com>
363 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
364 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
365 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
366 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
367 * i386-init.h: Re-generate.
369 2018-04-26 Jan Beulich <jbeulich@suse.com>
371 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
372 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
373 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
374 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
376 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
378 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
380 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
381 cpuregzmm, and cpuregmask.
382 * i386-init.h: Re-generate.
383 * i386-tbl.h: Re-generate.
385 2018-04-26 Jan Beulich <jbeulich@suse.com>
387 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
388 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
389 * i386-init.h: Re-generate.
391 2018-04-26 Jan Beulich <jbeulich@suse.com>
393 * i386-gen.c (VexImmExt): Delete.
394 * i386-opc.h (VexImmExt, veximmext): Delete.
395 * i386-opc.tbl: Drop all VexImmExt uses.
396 * i386-tlb.h: Re-generate.
398 2018-04-25 Jan Beulich <jbeulich@suse.com>
400 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
402 * i386-tlb.h: Re-generate.
404 2018-04-25 Tamar Christina <tamar.christina@arm.com>
406 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
408 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
410 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
412 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
413 (cpu_flags): Add CpuCLDEMOTE.
414 * i386-init.h: Regenerate.
415 * i386-opc.h (enum): Add CpuCLDEMOTE,
416 (i386_cpu_flags): Add cpucldemote.
417 * i386-opc.tbl: Add cldemote.
418 * i386-tbl.h: Regenerate.
420 2018-04-16 Alan Modra <amodra@gmail.com>
422 * Makefile.am: Remove sh5 and sh64 support.
423 * configure.ac: Likewise.
424 * disassemble.c: Likewise.
425 * disassemble.h: Likewise.
426 * sh-dis.c: Likewise.
427 * sh64-dis.c: Delete.
428 * sh64-opc.c: Delete.
429 * sh64-opc.h: Delete.
430 * Makefile.in: Regenerate.
431 * configure: Regenerate.
432 * po/POTFILES.in: Regenerate.
434 2018-04-16 Alan Modra <amodra@gmail.com>
436 * Makefile.am: Remove w65 support.
437 * configure.ac: Likewise.
438 * disassemble.c: Likewise.
439 * disassemble.h: Likewise.
442 * Makefile.in: Regenerate.
443 * configure: Regenerate.
444 * po/POTFILES.in: Regenerate.
446 2018-04-16 Alan Modra <amodra@gmail.com>
448 * configure.ac: Remove we32k support.
449 * configure: Regenerate.
451 2018-04-16 Alan Modra <amodra@gmail.com>
453 * Makefile.am: Remove m88k support.
454 * configure.ac: Likewise.
455 * disassemble.c: Likewise.
456 * disassemble.h: Likewise.
457 * m88k-dis.c: Delete.
458 * Makefile.in: Regenerate.
459 * configure: Regenerate.
460 * po/POTFILES.in: Regenerate.
462 2018-04-16 Alan Modra <amodra@gmail.com>
464 * Makefile.am: Remove i370 support.
465 * configure.ac: Likewise.
466 * disassemble.c: Likewise.
467 * disassemble.h: Likewise.
468 * i370-dis.c: Delete.
469 * i370-opc.c: Delete.
470 * Makefile.in: Regenerate.
471 * configure: Regenerate.
472 * po/POTFILES.in: Regenerate.
474 2018-04-16 Alan Modra <amodra@gmail.com>
476 * Makefile.am: Remove h8500 support.
477 * configure.ac: Likewise.
478 * disassemble.c: Likewise.
479 * disassemble.h: Likewise.
480 * h8500-dis.c: Delete.
481 * h8500-opc.h: Delete.
482 * Makefile.in: Regenerate.
483 * configure: Regenerate.
484 * po/POTFILES.in: Regenerate.
486 2018-04-16 Alan Modra <amodra@gmail.com>
488 * configure.ac: Remove tahoe support.
489 * configure: Regenerate.
491 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
493 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
495 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
497 * i386-tbl.h: Regenerated.
499 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
501 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
502 PREFIX_MOD_1_0FAE_REG_6.
504 (OP_E_register): Use va_mode.
505 * i386-dis-evex.h (prefix_table):
506 New instructions (see prefixes above).
507 * i386-gen.c (cpu_flag_init): Add WAITPKG.
508 (cpu_flags): Likewise.
509 * i386-opc.h (enum): Likewise.
510 (i386_cpu_flags): Likewise.
511 * i386-opc.tbl: Add umonitor, umwait, tpause.
512 * i386-init.h: Regenerate.
513 * i386-tbl.h: Likewise.
515 2018-04-11 Alan Modra <amodra@gmail.com>
517 * opcodes/i860-dis.c: Delete.
518 * opcodes/i960-dis.c: Delete.
519 * Makefile.am: Remove i860 and i960 support.
520 * configure.ac: Likewise.
521 * disassemble.c: Likewise.
522 * disassemble.h: Likewise.
523 * Makefile.in: Regenerate.
524 * configure: Regenerate.
525 * po/POTFILES.in: Regenerate.
527 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
532 (print_insn): Clear vex instead of vex.evex.
534 2018-04-04 Nick Clifton <nickc@redhat.com>
536 * po/es.po: Updated Spanish translation.
538 2018-03-28 Jan Beulich <jbeulich@suse.com>
540 * i386-gen.c (opcode_modifiers): Delete VecESize.
541 * i386-opc.h (VecESize): Delete.
542 (struct i386_opcode_modifier): Delete vecesize.
543 * i386-opc.tbl: Drop VecESize.
544 * i386-tlb.h: Re-generate.
546 2018-03-28 Jan Beulich <jbeulich@suse.com>
548 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
549 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
550 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
551 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
552 * i386-tlb.h: Re-generate.
554 2018-03-28 Jan Beulich <jbeulich@suse.com>
556 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
558 * i386-tlb.h: Re-generate.
560 2018-03-28 Jan Beulich <jbeulich@suse.com>
562 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
563 (vex_len_table): Drop Y for vcvt*2si.
564 (putop): Replace plain 'Y' handling by abort().
566 2018-03-28 Nick Clifton <nickc@redhat.com>
569 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
570 instructions with only a base address register.
571 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
572 handle AARHC64_OPND_SVE_ADDR_R.
573 (aarch64_print_operand): Likewise.
574 * aarch64-asm-2.c: Regenerate.
575 * aarch64_dis-2.c: Regenerate.
576 * aarch64-opc-2.c: Regenerate.
578 2018-03-22 Jan Beulich <jbeulich@suse.com>
580 * i386-opc.tbl: Drop VecESize from register only insn forms and
581 memory forms not allowing broadcast.
582 * i386-tlb.h: Re-generate.
584 2018-03-22 Jan Beulich <jbeulich@suse.com>
586 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
587 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
588 sha256*): Drop Disp<N>.
590 2018-03-22 Jan Beulich <jbeulich@suse.com>
592 * i386-dis.c (EbndS, bnd_swap_mode): New.
593 (prefix_table): Use EbndS.
594 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
595 * i386-opc.tbl (bndmov): Move misplaced Load.
596 * i386-tlb.h: Re-generate.
598 2018-03-22 Jan Beulich <jbeulich@suse.com>
600 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
601 templates allowing memory operands and folded ones for register
603 * i386-tlb.h: Re-generate.
605 2018-03-22 Jan Beulich <jbeulich@suse.com>
607 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
608 256-bit templates. Drop redundant leftover Disp<N>.
609 * i386-tlb.h: Re-generate.
611 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
613 * riscv-opc.c (riscv_insn_types): New.
615 2018-03-13 Nick Clifton <nickc@redhat.com>
617 * po/pt_BR.po: Updated Brazilian Portuguese translation.
619 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
621 * i386-opc.tbl: Add Optimize to clr.
622 * i386-tbl.h: Regenerated.
624 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-gen.c (opcode_modifiers): Remove OldGcc.
627 * i386-opc.h (OldGcc): Removed.
628 (i386_opcode_modifier): Remove oldgcc.
629 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
630 instructions for old (<= 2.8.1) versions of gcc.
631 * i386-tbl.h: Regenerated.
633 2018-03-08 Jan Beulich <jbeulich@suse.com>
635 * i386-opc.h (EVEXDYN): New.
636 * i386-opc.tbl: Fold various AVX512VL templates.
637 * i386-tlb.h: Re-generate.
639 2018-03-08 Jan Beulich <jbeulich@suse.com>
641 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
642 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
643 vpexpandd, vpexpandq): Fold AFX512VF templates.
644 * i386-tlb.h: Re-generate.
646 2018-03-08 Jan Beulich <jbeulich@suse.com>
648 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
649 Fold 128- and 256-bit VEX-encoded templates.
650 * i386-tlb.h: Re-generate.
652 2018-03-08 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
655 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
656 vpexpandd, vpexpandq): Fold AVX512F templates.
657 * i386-tlb.h: Re-generate.
659 2018-03-08 Jan Beulich <jbeulich@suse.com>
661 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
662 64-bit templates. Drop Disp<N>.
663 * i386-tlb.h: Re-generate.
665 2018-03-08 Jan Beulich <jbeulich@suse.com>
667 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
668 and 256-bit templates.
669 * i386-tlb.h: Re-generate.
671 2018-03-08 Jan Beulich <jbeulich@suse.com>
673 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
674 * i386-tlb.h: Re-generate.
676 2018-03-08 Jan Beulich <jbeulich@suse.com>
678 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
680 * i386-tlb.h: Re-generate.
682 2018-03-08 Jan Beulich <jbeulich@suse.com>
684 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
685 * i386-tlb.h: Re-generate.
687 2018-03-08 Jan Beulich <jbeulich@suse.com>
689 * i386-gen.c (opcode_modifiers): Delete FloatD.
690 * i386-opc.h (FloatD): Delete.
691 (struct i386_opcode_modifier): Delete floatd.
692 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
694 * i386-tlb.h: Re-generate.
696 2018-03-08 Jan Beulich <jbeulich@suse.com>
698 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
700 2018-03-08 Jan Beulich <jbeulich@suse.com>
702 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
703 * i386-tlb.h: Re-generate.
705 2018-03-08 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
709 * i386-tlb.h: Re-generate.
711 2018-03-07 Alan Modra <amodra@gmail.com>
713 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
715 * disassemble.h (print_insn_rs6000): Delete.
716 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
717 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
718 (print_insn_rs6000): Delete.
720 2018-03-03 Alan Modra <amodra@gmail.com>
722 * sysdep.h (opcodes_error_handler): Define.
723 (_bfd_error_handler): Declare.
724 * Makefile.am: Remove stray #.
725 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
727 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
728 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
729 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
730 opcodes_error_handler to print errors. Standardize error messages.
731 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
732 and include opintl.h.
733 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
734 * i386-gen.c: Standardize error messages.
735 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
736 * Makefile.in: Regenerate.
737 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
738 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
739 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
740 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
741 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
742 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
743 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
744 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
745 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
746 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
747 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
748 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
749 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
751 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
753 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
754 vpsub[bwdq] instructions.
755 * i386-tbl.h: Regenerated.
757 2018-03-01 Alan Modra <amodra@gmail.com>
759 * configure.ac (ALL_LINGUAS): Sort.
760 * configure: Regenerate.
762 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
764 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
765 macro by assignements.
767 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
770 * i386-gen.c (opcode_modifiers): Add Optimize.
771 * i386-opc.h (Optimize): New enum.
772 (i386_opcode_modifier): Add optimize.
773 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
774 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
775 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
776 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
777 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
779 * i386-tbl.h: Regenerated.
781 2018-02-26 Alan Modra <amodra@gmail.com>
783 * crx-dis.c (getregliststring): Allocate a large enough buffer
784 to silence false positive gcc8 warning.
786 2018-02-22 Shea Levy <shea@shealevy.com>
788 * disassemble.c (ARCH_riscv): Define if ARCH_all.
790 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-opc.tbl: Add {rex},
793 * i386-tbl.h: Regenerated.
795 2018-02-20 Maciej W. Rozycki <macro@mips.com>
797 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
798 (mips16_opcodes): Replace `M' with `m' for "restore".
800 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
802 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
804 2018-02-13 Maciej W. Rozycki <macro@mips.com>
806 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
807 variable to `function_index'.
809 2018-02-13 Nick Clifton <nickc@redhat.com>
812 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
813 about truncation of printing.
815 2018-02-12 Henry Wong <henry@stuffedcow.net>
817 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
819 2018-02-05 Nick Clifton <nickc@redhat.com>
821 * po/pt_BR.po: Updated Brazilian Portuguese translation.
823 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
825 * i386-dis.c (enum): Add pconfig.
826 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
827 (cpu_flags): Add CpuPCONFIG.
828 * i386-opc.h (enum): Add CpuPCONFIG.
829 (i386_cpu_flags): Add cpupconfig.
830 * i386-opc.tbl: Add PCONFIG instruction.
831 * i386-init.h: Regenerate.
832 * i386-tbl.h: Likewise.
834 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
836 * i386-dis.c (enum): Add PREFIX_0F09.
837 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
838 (cpu_flags): Add CpuWBNOINVD.
839 * i386-opc.h (enum): Add CpuWBNOINVD.
840 (i386_cpu_flags): Add cpuwbnoinvd.
841 * i386-opc.tbl: Add WBNOINVD instruction.
842 * i386-init.h: Regenerate.
843 * i386-tbl.h: Likewise.
845 2018-01-17 Jim Wilson <jimw@sifive.com>
847 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
849 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
851 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
852 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
853 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
854 (cpu_flags): Add CpuIBT, CpuSHSTK.
855 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
856 (i386_cpu_flags): Add cpuibt, cpushstk.
857 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
858 * i386-init.h: Regenerate.
859 * i386-tbl.h: Likewise.
861 2018-01-16 Nick Clifton <nickc@redhat.com>
863 * po/pt_BR.po: Updated Brazilian Portugese translation.
864 * po/de.po: Updated German translation.
866 2018-01-15 Jim Wilson <jimw@sifive.com>
868 * riscv-opc.c (match_c_nop): New.
869 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
871 2018-01-15 Nick Clifton <nickc@redhat.com>
873 * po/uk.po: Updated Ukranian translation.
875 2018-01-13 Nick Clifton <nickc@redhat.com>
877 * po/opcodes.pot: Regenerated.
879 2018-01-13 Nick Clifton <nickc@redhat.com>
881 * configure: Regenerate.
883 2018-01-13 Nick Clifton <nickc@redhat.com>
887 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
889 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
890 * i386-tbl.h: Regenerate.
892 2018-01-10 Jan Beulich <jbeulich@suse.com>
894 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
895 * i386-tbl.h: Re-generate.
897 2018-01-10 Jan Beulich <jbeulich@suse.com>
899 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
900 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
901 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
902 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
903 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
904 Disp8MemShift of AVX512VL forms.
905 * i386-tbl.h: Re-generate.
907 2018-01-09 Jim Wilson <jimw@sifive.com>
909 * riscv-dis.c (maybe_print_address): If base_reg is zero,
910 then the hi_addr value is zero.
912 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
914 * arm-dis.c (arm_opcodes): Add csdb.
915 (thumb32_opcodes): Add csdb.
917 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
919 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
920 * aarch64-asm-2.c: Regenerate.
921 * aarch64-dis-2.c: Regenerate.
922 * aarch64-opc-2.c: Regenerate.
924 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
927 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
928 Remove AVX512 vmovd with 64-bit operands.
929 * i386-tbl.h: Regenerated.
931 2018-01-05 Jim Wilson <jimw@sifive.com>
933 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
936 2018-01-03 Alan Modra <amodra@gmail.com>
938 Update year range in copyright notice of all files.
940 2018-01-02 Jan Beulich <jbeulich@suse.com>
942 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
943 and OPERAND_TYPE_REGZMM entries.
945 For older changes see ChangeLog-2017
947 Copyright (C) 2018 Free Software Foundation, Inc.
949 Copying and distribution of this file, with or without modification,
950 are permitted in any medium without royalty provided the copyright
951 notice and this notice are preserved.
957 version-control: never